JPH02275378A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the setting of a state easily at an optional level in a short time by a method wherein a shift register circuit for testing is provided to output a specified level of signal to each corresponding output terminal based on a test data signal and a clock signal in a test mode. CONSTITUTION:When a test mode is set by a mode setting signal 101, a shift register data signal 102 to be inputted at a terminal 52 is taken into a shift register circuit 1 for testing through a shift register clock signal 103. Then, A, B and C test data signals 104-106 are outputted in parallel to be sent to A, B and C output signal switching circuits 2-4. Thus, output signals 110-112 are obtained corresponding to the signals 104-106 from output terminals 54-56 of the circuits 2-4. This enables testing easily in a short time with a sequential outputting of specified levels to the output terminals 54-56.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that improves the measurement of electrical characteristics of an output terminal.

[Conventional technology]

In conventional semiconductor integrated circuits, when measuring the electrical characteristics of an output terminal, the level at the output terminal is generally fixed at the ``H'' level or the ``L'' level. For example, as seen in the conventional example shown in FIG. 3, P-type MO3)-
When measuring the on-resistance value of Ranjistaro, use P type M
Only the OS transistor 6 is turned on and the output terminal 65 is fixed at "H" level. Next, when a voltage lower than the power supply voltage applied to the terminal 63 is applied to the output terminal 65, a "°H°" level output current flows out from the output terminal 65, so the current value and potential difference at this time are using P
! HMO3) The on-resistance value of Ranjistaro is calculated.

Similarly, when measuring the on-resistance value of the N-type 14OS transistor 8, only the N-type MOS transistor 8 is turned on and the level of the output terminal 65 is fixed at the L'' level.
By applying a voltage higher than the ground point to the output terminal 65, an "L" level output current flows out from the output terminal 65, so the current value and potential difference at this time cause the N-type M
O3) - The on-resistance value of transistor 8 is determined. This means that P-type 1 TIOS transistor 7 and N-type 14
05) The same applies to the case of the output terminal 66 corresponding to the transistor 9.

In this way, when measuring the electrical characteristics of the output terminal of a semiconductor integrated circuit, in order to fix the level value of the output terminal, it is actually necessary to use a complex combination of input information corresponding to the state setting of the internal circuit 5. In need of.

For example, in the case of a microcomputer, first, as a test mode, a mode is set in which the internal circuit 5 is operated by command input information from the outside, not by command information generated and output from the internal ROM. Next, command input information for setting arbitrary level values is input to the output terminals 65 and 66, respectively, to put the internal circuit 5 into an operating state, and the output terminals 65 and 66 are set to "H". ” level and “L” level are set. Thereafter, by holding the command input information as it is, the level state of each output terminal is held, and the electrical characteristics of each output terminal are measured.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, the output data at the output terminal is determined after operating the internal circuit,
The level value of the corresponding output terminal is set. For this reason, it requires a complex combination of input information to the semiconductor integrated circuit, and also has the disadvantage that it takes a considerable amount of time to set the conditions necessary to measure the characteristics of the output terminal.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention takes in a predetermined shift register data signal input from the outside via a shift register clock signal input from the outside during a test mode corresponding to an output terminal test. a test shift register circuit that outputs test data signals corresponding to predetermined output terminals in parallel via the input shift register data signals; and a data signal during normal operation corresponding to the output terminals; and an output signal switching circuit that receives the test data signal in the test mode, selects the test data signal, and outputs the selected test data signal to the corresponding output terminal in the test mode.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of test-related peripheral parts in one embodiment of the present invention. As shown in FIG. 1, the test-related peripheral parts of this embodiment include a test shift register circuit 1,
A output signal switching circuit 2, day output signal switching circuit 3, and C
The output signal switching circuit 4 is configured to include an output signal switching circuit 4.

In FIG. 1, a mode setting signal 101 having a switching function between a normal mode and a test mode is sent from a terminal 51 to a test shift register circuit 1. A output signal switching circuit 2, day output signal switching circuit 3, and C output signal switching circuit 4
is input. In the normal mode, the test shift register circuit is in a reset state, but in the test mode, the shift register data signal 102 input from the terminal 52 is the shift register clock signal input from the terminal 53. 103 to the test shift register circuit 1, and this captured data is sent to the A test data signal 104 and the B test data signal 10.
5 and C test data signals 106, and are sent to the A output signal switching circuit 2, the day output signal switching circuit 3, and the C output signal switching circuit 4, respectively.

A output from the output terminal 54 of the A output signal switching circuit 2
As the output signal 110, the A test data signal 104 is output in the test mode, and the A data signal 107 generated from a predetermined internal circuit (not shown) and input through the terminal 57 is output in the normal mode. . Similarly, in the B output signal switching circuit 3 and the C output signal switching circuit 4, the above-mentioned C Test data signal 105 and C test data signal 106 are output, and in normal mode, terminals 58 and 59, respectively.
A B data signal 108 and a C data signal 109 inputted through are output.

Figure 2 (a), (b), (c), (d), (e), (f
), (g), (h), (i).

(j>, (k), and (1) show examples of timing diagrams of each of the above signals in normal mode and test mode.

As is clear from FIG. 2, the mode setting signal 101 is L
“During the normal mode set to
(see Figure 2 (j)), B output signal 111 (see Figure 2 (k)), B output signal 111 (see Figure 2 (k)
)> and C output signal 112 (see second diagram 1))
, respectively, the A data signal 107 (Fig. 2(b)
), a B data signal 108 (see FIG. 2(c)), and a C data signal 109 (see FIG. 2(d)) are output.

Hereinafter, in the test mode, each level at the output terminals 54, 55 and 56 is set to H'.

The operation when setting the level, "L" level, and "H" level will be explained.

First, when the mode setting signal 101 is set to "H" level, the A test data signal 10 is output from the output terminal 54 as the A output signal 110 by the A output signal switching circuit 2.
4 is output. Also from the output terminals 55 and 56, as a B output signal 111 and a C output signal 112, respectively,
The B output signal switching circuit 3 and the C output signal switching circuit 4 output a C test data signal 105 and a C test data signal 106, respectively. Further, in this case, the test shift register circuit 1 is in the reset/sort release state because the mode setting signal 101 is set to the H'' level.

Next, in order to set the output terminal 56 to the 'f(' level, the shift register data signal 102 is set to the 'H' level, and the test shift register circuit is activated by the first clock of the shift register clock signal 103). takes in the shift register data signal 102. As a result,
The A test data signal 104 becomes "H" level. Next, in order to set the output terminal 55 to the "L" level, the shift register data signal 102 is set to the "L" level, and the shift register data signal 102 is set to the "L" level by the second clock of the shift register clock signal 103. The data signal 102 is taken in. At this time, the A test data signal 104 becomes the "L" level, and the C test data signal 105 becomes the "H" level by shifting the level value of the A test data signal 104.

Next, in order to set the output terminal 54 to the "H" level, shift 1 to register data signals 102 are set to the "L" level, and the third clock of the shift register clock signal 103 turns on the test shift signal. The shift register data signal 102 is taken into the registration circuit 1. When this data is taken in, the A test data signal 104 goes to "H" level, and the C test data signal 105 becomes the same as the previous A test data signal 104. The data is shifted to the PA level. Also, the C test data signal 106 is
The data of the test data signal 105 is shifted
As a result of the 4゛Y4゛ level or more, the A test data signal 10 is output to the output terminal 54.
4 is output, the output terminal 54 is set to the 'H' level, and the C test data signal 105 is output to the output terminal 55, so the output terminal 55 is set to the 'L°' level, and the output terminal 56 is set to the 'L°' level. Since the C test pig signal 106 is output, the output terminal 56 is set to the "H" level.

Therefore, in this embodiment, in the test mode, a test shift register circuit is provided which operates by inputting two types of signals, a shift register data signal and a shift register clock signal, and a predetermined output signal is sent to each output terminal. By outputting to each output terminal, it becomes possible to easily set the level value of ('EX) to each of the output terminals.

〔Effect of the invention〕

As described above in detail, the present invention provides five shift register data signals and a shift register data signal in the test mode.
It is equipped with a test shift register circuit that operates by inputting two types of clock signals, and outputs the test data signal output from the test shift register circuit to each corresponding output terminal, thereby reducing the In this case, there is an effect that an arbitrary level value can be easily set to each of the output terminals.

signal switching circuit, 4...C output signal switching circuit, 5.
......Internal circuit, 6,7...--P type l
ll0S transistor, 8°9...N type 14O
S transistor.

Claims (1)

[Scope of Claims] During a test mode corresponding to an output terminal test, a predetermined shift register data signal inputted from the outside is taken in via a shift register clock signal inputted from the outside, A test shift register circuit that outputs test data signals corresponding to predetermined output terminals in parallel via a shift register data signal; a data signal during normal operation corresponding to the output terminal; and a test data signal during normal operation corresponding to the output terminal; 1. A semiconductor integrated circuit comprising: an output signal switching circuit that receives the test data signal and selects the test data signal and outputs the selected test data signal to a corresponding output terminal in a test mode.