JPH02276386A - Jitter processing circuit - Google Patents

Abstract

PURPOSE:To attain the correct detection of jitter by continuing the A/D conversion with only a phase modulated clock having no switching for detection of the jitter value and controlling the phase shift value of the phase modulated clock in accordance with the detected jitter value and the jitter value corrected before 1H. CONSTITUTION:The synchronizing separator pulses are inputted to a burst flag generating circuit 10 and a tape H delay circuit 11. These circuits 10 and 11 produce and output the burst flag pulse and the delay pulse in consideration of the delay value produced by a video delay circuit 3. The A/D conversion output which is delayed and outputted from the circuit 3 is inputted to a jitter fluctuation detecting circuit 9'. Then the jitter fluctuation data is detected based on the value of the A/D conversion output set against a specific reference clock of a burst period. The jitter correction value is kept within a prescribed range by an emitter 22 for production of the jitter correction data. Thus the A/D conversion is usually carried out by only a phase modulated clock. As a result, the stable and sure jitter correction is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an improvement of a jitter processing circuit with a simplified configuration.

(b) Conventional technology A jitter correction circuit that can be used in a video tape recorder is disclosed in Japanese Patent Laid-Open No. 124385/1985 (I(04N5).
/95). FIG. 3 is a circuit block diagram of the main part of the jitter correction circuit disclosed in this prior art. This conventional technology changes the writing start timing of input video information (AD conversion data) for each line for large jitter components, and changes the AD conversion timing of human video signals for small jitter components. . The input video signal includes a negative horizontal synchronization signal and a color burst signal during the horizontal blanking period, and during the generation period of the burst flag pulse formed by delaying the horizontal synchronization separation output, the reference clock The amount of jitter is detected from the level of the color burst that has been AD converted. That is, the jitter correction circuit (6) performs AD conversion on the input video signal in synchronization with the reference clock using the second AD conversion circuit (7), and this AD conversion data is input to the synchronization separation circuit (8). Horizontal synchronization timing is detected. At this synchronization timing, the burst flag generation circuit (10) and tape H delay circuit (11) start counting the reference clock.

As a result, a burst flag pulse is derived during the burst generation period, and a delayed pulse is derived at a timing after jitter detection, before the start timing of the video period. The jitter detection circuit (9) detects the amount of jitter (phase shift) by detecting the AD conversion output level at a specific timing during the burst flag pulse generation period. However, it is assumed that the detected amount of jitter is in the range of ±n clocks when the reference clock frequency is 2n times the color subcarrier frequency, and jitter occurs within this range. The clock phase of the clock phase modulation circuit (12) is immediately controlled based on the lower-order data of the detected jitter detection data. That is, the clock phase modulation circuit (12) controls the amount of phase shift of the reference clock based on lower-order data. Incidentally, the higher-order data of the jitter detection is input to a write start control circuit (13) to be described later.

A first AD conversion circuit (1) to which an input video signal is input performs AD conversion in synchronization with a phase modulation clock, and an AD conversion output is input to a timing circuit (2). This timing circuit (2) is arranged in consideration of the fact that data transfer processing becomes difficult when the phase modulation clock and the reference clock have a special phase relationship. The relationship is detected and the transfer timing of AD conversion data is changed. The timing circuit output is input to the memory (4) via a video delay circuit (3) for compensating for a time delay due to jitter detection, which will be described later, but the write start timing of this memory is determined by the write start control. defined by circuit (13). This write start control circuit (13) delays the reference clock by counting the aforementioned delay pulse into the upper bits of the jitter detection data according to the content. Therefore, this write start pulse is issued in synchronization with the video start point of each line, and only the video information of each line is input to the memory (4) based on the output of the write control circuit (14). The video information stored in this memory (4) is controlled by a readout control circuit (16) which specifies the readout start timing of each line by a readout generation circuit (15) and reads out the data in synchronization with the reference clock. 4). The read video information is converted into an analog signal in a DA converter circuit (5) synchronized with a reference clock, and is derived as an output video signal. Note that (17) in the figure indicates a reference clock generation circuit (17).

Although the above-mentioned conventional technology provides two AD conversion circuits, it is not necessary for both AD conversion circuits to operate at the same time, and if the input clocks are switched at separate timings, only one DA conversion circuit is required. Therefore, the above-mentioned conventional technology is further
We also propose a jitter correction circuit as shown in the figure. This jitter correction circuit differs from the circuit shown in Fig. 3 in that it does not include the second AD conversion circuit (7) and inputs the output of the timing circuit (2) to the jitter detection circuit (9) and synchronous separation circuit (8). AD conversion circuit (1) and timing circuit (2)
The clock to be input to the timing circuit (2) is selected by the first switch (Sl), and the jitter detection data to be input to the timing circuit (2) is selected by the second switch (S2). (18) is executed. Therefore, according to this prior art, the clock switching circuit (18) switches both switches (Sl) (S2) to the b side during the horizontal blanking period in conjunction with the synchronization timing. As a result, the input video signal is AD converted by the reference clock and input to the jitter detection circuit (9) via the timing circuit (2). The jitter detection circuit (9) detects the amount of jitter from the value of the AD conversion data at a specific timing during the burst period, as in the conventional example described above, generates jitter detection data, and determines the writing start timing to the memory using the upper data. The amount of phase shift of the phase modulation clock is defined by the lower data. As a result, the first switch (S
1) supplies the phase-shifted phase modulated clock to the AD conversion circuit, and the second switch (S2) inputs the lower bits of the detected data to the timing circuit (2). As described above, in the conventional circuit shown in FIG. 4, the amount of jitter is detected based on the reference clock during the horizontal blanking period, AD conversion is performed using the corrected clock during the video period, and the memory write start timing is specified. ing.

(c) Problems to be Solved by the Invention In the prior art described above, when switching is performed with the switches (Sl) (S2), the timing circuit (2) does not respond quickly immediately after switching, and the subsequent This caused the circuit to malfunction. In particular, it has been confirmed that if the synchronization separation circuit malfunctions, the burst period cannot be detected and jitter cannot be detected correctly.

(d) Means for Solving the Problems Therefore, in view of the above-mentioned points, the present invention detects the jitter amount by continuously performing AD conversion only by the phase modulation clock without switching, and compares the detected jitter amount with the IH before IH. The present invention is characterized in that the amount of phase shift of the phase modulation clock is controlled according to the amount of jitter correction.

(E) Accordingly, according to the present invention, the amount of jitter detected by the phase modulation clock whose phase is corrected before IH is the amount of change in jitter, and the amount of jitter should be corrected by subtracting the amount of change from the amount of correction before IH. The amount of jitter is calculated.

(f) Example The present invention will be described below with reference to illustrative embodiments.

The first is a circuit block diagram showing a first embodiment in which the present invention is applied to a video disk recorder for recording and reproducing high-quality video signals, in which the recording signal includes a negative horizontal synchronizing signal, a burst signal, and a time axis signal in one line period. Compressed line-sequential color signals and time-axis compressed luminance signals are arranged in order. Note that the burst signal is a constant frequency wave for jitter correction, and its frequency is selected to be six times the reference clock. In this embodiment, an input video signal is AD-converted using a phase modulation clock, and the AD-converted output is supplied to a timing circuit (2) which is always in operation to derive an AD-converted output in synchronization with a reference clock. . A sync separation circuit (8) which receives this AD conversion output detects a negative horizontal sync signal and generates a sync separation pulse. This synchronization separation pulse is connected to the burst flag generation circuit (10) and the tape H.
The signal is input to the delay circuit (11). In this embodiment, both circuits (10) and (11) form and derive burst flag pulses and delay pulses in consideration of the amount of delay caused by the video delay circuit (3). The AD conversion output that is delayed and derived by the video delay circuit (3) is sent to the jitter fluctuation detection circuit (
9'), and the value of the AD conversion output for a specific reference clock during the burst period is subjected to AD conversion to detect the amount of jitter with respect to the modulation clock, that is, the fluctuation data of jitter. In order to form jitter correction data based on this thick fluctuation data, in this embodiment, the jitter correction data before IH is obtained from the IH delay circuit (20), and the IH correction data is obtained from the IH delay circuit (20). The jitter correction amount is obtained by subtracting the rejitter fluctuation data from the jitter correction data before H. This jitter correction amount is kept within a predetermined range by a limiter (22) to form jitter correction data. The limit range of this limiter (22) is set narrower than the response range of the write start control circuit (13), but if this response range is wide, the limiter (22) is unnecessary. The jitter correction data obtained from the limiter is stored in the above-mentioned IH delay circuit (20), and is also stored in the clock phase modulation circuit (12) and timing circuit (2).
and is used as a control input of the write start control circuit (13). The clock phase modulation circuit (12) detects jitter correction data below (lower) l clocks and controls the amount of phase shift of the reference clock, and the timing circuit (2) detects a special amount of phase shift and uses it as the reference signal. The timing has been corrected. Furthermore, the write start control circuit (13) counts reference clocks based on jitter correction data higher than the delay pulse generation timing, and generates a write start pulse synchronized with the input timing of video data. The write control circuit (14) receives this write start pulse and writes the AD conversion output into the memory (4) line by line. The memory (4) stores AD conversion data in synchronization with the horizontal synchronization signal of the input video signal,
Reading is performed at a constant cycle, and the read H generation circuit (15) which inputs the reference clock emits a read start pulse at a constant cycle (line cycle), and the read control circuit (16) outputs a read start pulse every line cycle. AD conversion data is being read. The read AD conversion data has jitter removed and the DA
The conversion circuit (5) converts the signal into an analog signal and derives the signal.

Although not shown in the figure, if the time-axis compressed line-sequential color signal or luminance signal is time-axis expanded and synchronized to perform various processes digitally, those processing means are D.
It is necessary to provide it before the A conversion circuit.

In the example described above, the output of the video delay circuit (3) is input to the jitter detection circuit (9) in order to compensate for the delay in the operation of the synchronization separation circuit (8), that is, the delay in the generation of the synchronization separation pulse. If the delay time of the video delay circuit (3) is short, it is predicted that the timing of generation of the bust flag pulse will be delayed, making it impossible to correctly detect jitter. So the second
As shown in the figure, if the output of the timing circuit (2) is input to an independently provided delay circuit (23) and this delayed output is input to the jitter conversion detection circuit (9゛), there is some freedom. It is possible to set the delay time of the delay circuit (23) to accurately detect jitter.

The second embodiment shown in FIG. 2 is substantially the same as that in FIG. 1, so the same components are given the same reference numerals, and a description of the operation will be omitted.

In all of the embodiments described above, the phase is intermittently changed at the beginning of a line, and it is not possible to follow the jitter that varies during the video period of each line.

Therefore, in the third embodiment, the phase of the clock is continuously changed during the video period in accordance with the predicted jitter fluctuation, and FIG. 5 shows a circuit diagram of the main part thereof. This embodiment is further modified from the second embodiment shown in FIG. 2 to include horizontal period detection means (24), speed error prediction means (25), correction signal generation means (26), and addition means (27). It is characterized by adding.

The horizontal period detection means (24) accurately detects the horizontal synchronization period and derives horizontal period data. This horizontal period detection circuit (24) includes means for roughly counting the horizontal synchronization period and means for finely counting the variation.
It is characterized by arithmetic processing of both.

First, in order to roughly count the horizontal synchronization period, the synchronization separation output generated in synchronization with the reference clock is first input to the tape H delay circuit (11) and further delayed by an integer number of reference clocks. This tape H delay output is generated near the end of the horizontal blanking period in synchronization with the reference clock, and is detected by the counter (24) in the horizontal period detecting means (24).
At the same time as the reset input of a) is input, the latch circuit (24b
) is used as a latch input. The counter (24a) is
The tape [I output is counted using a reference clock, and the counted value is latched in a latch circuit (24b) at the timing of completion of counting. Therefore, the latch data corresponds to the period of the horizontal period separation output. In this embodiment, during the horizontal synchronization period, the clock phase modulation circuit (12) is specified to be in a non-modulated state, and the AD conversion timing is performed in the same phase as the reference clock.

On the other hand, in order to finely count horizontal synchronization fluctuations, the timing output is input to a delay circuit (23), where it is delayed by the time required for synchronization separation processing and converted into a delayed signal synchronized with the reference clock to the jitter fluctuation detection circuit. (9゛) is input. Further, the burst flag generation circuit (10) counts a fixed number of reference clocks starting from the synchronized separated output synchronized with the reference clock, and generates burst flag pulses of a predetermined time width synchronized with the reference clock with jitter fluctuations. It has already been input to the detection circuit (lO). The burst signal period is set to six times the reference clock period, and the jitter fluctuation detection circuit (10) determines the synchronization separation output timing based on the level of the delayed signal latched during the burst flag pulse generation period and its fluctuation. The phase shift amount of the burst signal is detected, and the detection range is ±3 clocks, and the detection accuracy is 1/32 clocks. Therefore, the jitter fluctuation detection output is formed within a range of ±3 clocks with an accuracy of 5 bits below the decimal point. It is input to the horizontal period detection circuit (24).

The jitter fluctuation detection output is input to the LH delay circuit (24C) and the subtraction circuit (24d).The subtraction circuit (24d) subtracts the jitter fluctuation detection output before IH from the input jitter fluctuation detection output to achieve fine horizontal synchronization. The period fluctuation amount is calculated, and the horizontal synchronization period is calculated with high accuracy in the next stage adding circuit (24e).

This horizontal period detection output is sent to the next stage speed error prediction circuit (2
5). This speed error prediction circuit (25) is
To predict the horizontal period Tn of the line from the horizontal period detection output (Tlli) (T, -*) (T', 1-s) of the previous line, the second line, and the third line, T , , = 3 T , -+-3T ll-, +T
Perform the calculation a-1, and calculate the horizontal synchronization period Tn of the line
Predict. Next, the reference horizontal synchronization period TO is subtracted from the predicted horizontal synchronization period Tn to derive speed error prediction data ΔTn.

This prediction error data ΔTn is generated by the correction signal generation circuit (26
) is input. This correction signal generation circuit (26) has a counter (26a) which receives the write start control signal as a reset input.
), and a predetermined number of reference clocks are counted during the video period. The multiplication circuit (26b) is
The speed error prediction data, this counter output, and a constant number are multiplied, and the multiplication output, which increases continuously from 0 to the value of the prediction error data during each video period, is derived as a correction signal (Figure 8). reference).

The adder circuit (6) adds the value below the decimal point in the jitter detection output and this correction signal, and outputs the clock phase modulation circuit (1).
2) and the timing circuit (2), and the clock phase modulation circuit (12) is in an unmodulated state until the jitter detection output is generated, and after the jitter detection output is generated, the clock phase modulation circuit (12) changes the clock phase at the start point of the video period. and its phase is changed in proportion to the speed error prediction data in the subsequent video period. It should be noted that the phase modulation step of the Crochet phase modulation circuit (12) is 16 steps.

Therefore, according to the third embodiment, the phase modulation clock changes continuously in each video period, making it possible to naturally correct jitter in the response.

In addition, even in the third embodiment shown in FIG. 5, the same reference numerals are used for the same components as in FIG.

(g) Effects of the Invention According to the present invention, stable and reliable jitter correction is possible by simply performing AD conversion only using a phase modulation clock, and the effect is great.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing the first embodiment of the present invention, FIG. 2 is a circuit block diagram of the second embodiment, FIG. 3 is a circuit block diagram of a different form of the conventional circuit, and FIG. A circuit block diagram of the third embodiment, FIG. 6 is a circuit block diagram of the horizontal period detection circuit of the same embodiment, FIG. 7 is a circuit block diagram of the correction signal generation circuit of the same embodiment, and FIG. 8 is the same main part. The signal waveform diagrams are shown respectively. (9゛)...Jitter fluctuation detection circuit, (21)...Subtraction circuit, (20)...IH delay circuit

Claims (1)

[Claims] (1) AD convert the input video signal in synchronization with a phase modulation clock synchronized with the jitter component, store the video information being output from the AD conversion in a memory in synchronization with the horizontal synchronization timing, and synchronize with the reference clock. In a jitter processing circuit that eliminates jitter in the input video signal by reading an AD conversion output from the memory, the jitter processing circuit eliminates jitter in the input video signal by reading the AD conversion output from the memory. A jitter fluctuation detection circuit that detects jitter fluctuations that occur during a synchronization period and forms and derives jitter fluctuation data, and an operation that forms and derives new jitter correction data based on jitter correction data one horizontal synchronization period before and the jitter fluctuation data. a write start control circuit that defines the writing start timing of the AD conversion data to the memory based on the upper jitter correction data; and a write start control circuit that determines the phase of the phase modulation clock based on the lower jitter correction data. A jitter processing circuit consisting of a clock phase conversion circuit and a controlling clock phase conversion circuit.