JPH0227736U - - Google Patents
Info
- Publication number
- JPH0227736U JPH0227736U JP10568888U JP10568888U JPH0227736U JP H0227736 U JPH0227736 U JP H0227736U JP 10568888 U JP10568888 U JP 10568888U JP 10568888 U JP10568888 U JP 10568888U JP H0227736 U JPH0227736 U JP H0227736U
- Authority
- JP
- Japan
- Prior art keywords
- plastic
- polymer substrate
- semiconductor element
- sealed
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 229920000307 polymer substrate Polymers 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000001746 injection moulding Methods 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 claims 1
- 238000001721 transfer moulding Methods 0.000 claims 1
- 238000007796 conventional method Methods 0.000 description 2
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案による樹脂封止５した状態を示
す斜視図である。第２図は半導体素子４を電極パ
ターン３に接続した基板の平面略図である。第３
図は本考案における第１図のＡ―Ａ′断面図であ
る。第４図は従来の方法におけるＡ―Ａ′断面図
である。第５図は従来方法による樹脂封止５を施
した状態を示す斜視図である。
１……接着剤、２……基板、３……電極パター
ン、４……半導体素子、５……封止樹脂、６……
樹脂コート、７……封止樹脂のバリ、８……デバ
イス穴、１２……高分子基板。
FIG. 1 is a perspective view showing a resin-sealed state according to the present invention. FIG. 2 is a schematic plan view of a substrate in which a semiconductor element 4 is connected to an electrode pattern 3. As shown in FIG. Third
The figure is a sectional view taken along the line AA' in FIG. 1 according to the present invention. FIG. 4 is a sectional view taken along line AA' in the conventional method. FIG. 5 is a perspective view showing a state in which resin sealing 5 is applied by a conventional method. DESCRIPTION OF SYMBOLS 1... Adhesive, 2... Substrate, 3... Electrode pattern, 4... Semiconductor element, 5... Sealing resin, 6...
Resin coat, 7...Flash of sealing resin, 8...Device hole, 12...Polymer substrate.
Claims (1)
て固定し、トランスフアーモールドや射出成型で
プラスチツク封止する構造において、前記高分子
基板の全面もしくはプラスチツク封止の外周部の
電極パターンの上面が、基板を構成する接着剤も
しくは樹脂コート剤の上面と同一平面となる前記
高分子基板を用いて、半導体素子を電気的に接合
した後、成型機を用いてプラスチツク封止した事
を特徴とするプラスチツクパツケージの構造。 In a structure in which a semiconductor element is fixed on a polymer substrate via connection wiring and sealed in plastic by transfer molding or injection molding, the upper surface of the electrode pattern on the entire surface of the polymer substrate or the outer periphery of the plastic sealing is , the semiconductor element is electrically bonded using the polymer substrate that is flush with the upper surface of the adhesive or resin coating agent constituting the substrate, and then sealed in plastic using a molding machine. Structure of plastic packaging.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10568888U JPH0227736U (en) | 1988-08-10 | 1988-08-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10568888U JPH0227736U (en) | 1988-08-10 | 1988-08-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0227736U true JPH0227736U (en) | 1990-02-22 |
Family
ID=31338527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10568888U Pending JPH0227736U (en) | 1988-08-10 | 1988-08-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0227736U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5493456A (en) * | 1977-12-29 | 1979-07-24 | Tanazawa Hakkosha Kk | Smooth printed circuit board and method of making same |
| JPS55157236A (en) * | 1979-05-28 | 1980-12-06 | Nec Corp | Semiconductor device |
-
1988
- 1988-08-10 JP JP10568888U patent/JPH0227736U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5493456A (en) * | 1977-12-29 | 1979-07-24 | Tanazawa Hakkosha Kk | Smooth printed circuit board and method of making same |
| JPS55157236A (en) * | 1979-05-28 | 1980-12-06 | Nec Corp | Semiconductor device |