JPH02278877A - Epitaxial gate turn off thyristor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an emitter layer of a second conductivity type distributed on a base layer of a first conductivity type on which a gate electrode is provided, using an epitaxial technique. Epitaxial gate turn-off formed through a layer of first conductivity type with low impurity concentration
(GTO) Regarding Cyrisk.

[Conventional technology]

It is desired that the GTO thyristor has a large maximum control current. Generally, in order to improve the maximum control current of a GTO thyristor, there are methods to reduce the gate impedance or to increase the reverse breakdown voltage between the gate and cathode so that the reverse bias voltage applied between the gate and cathode can be increased at turn-off. It is being In a GTO thyristor in which an n-emitter and a p-base are formed by a diffusion method, there is a mutually contradictory relationship between the reverse breakdown voltage between the gate and cathode and the gate impedance.

'In other words, in order to reduce the gate impedance, the concentration of the p-base layer in the gate part must be high. However, in order to increase the reverse breakdown voltage between the gate and cathode, the concentration of the p-base layer must be low. In order to solve these contradictory characteristics, an epitaxial GTO thyristor has been devised in which a low concentration p- layer is provided between the p base layer and the n emitter layer by epitaxial technology.

The structure of this epitaxial GTO thyristor will be explained below with reference to the drawings. A conventional epitaxial GTO thyristor has a cross-sectional structure as shown in FIG. 2, and the silicon substrate has a p-emitter layer.

n base layer 2. p9 base layer 3. Grow p- epitaxial base layer 4 + n emitter layer 5, and grow n emitter layer 5
The p-epitaxial base layer 4 is formed as a large number of island-like segments surrounded by the D'' base layer 3.
An anode electrode 6 and a cathode electrode 7 are applied to the emitter layer 1 and the n-emitter layer 5, respectively, and are connected to a main terminal, for example via a pressure contact electrode body. Further, a gate electrode 8 is attached to the p'' base layer 3. The side surfaces of the island-like segments are covered with an oxide film 9 as a protective film.

In such an epitaxial GTO thyristor, when the voltage of the anode electrode 6 is positive with respect to the cathode electrode 7, when a current is applied to the gate electrode 8 between the cathode electrode 7 and the gate electrode ai8, the state changes from the off state to the on state. On the other hand, when the current is extracted from the gate electrode 8, the ON state changes to the OFF state.

(Problem to be Solved by the Invention) Now, looking again at the point of improving the controllable current, the epitaxial GTO thyristor mentioned above is provided with a p-epitaxial base layer, so the gate and The concentration at the junction between the cathodes is low, and the reverse breakdown voltage can be improved to between 100V and 150V. Since the voltage between the gate and cathode of a conventional general GTO thyristor is 20V to 30V, theoretically it is possible to secure about 5 times the controllable current, but in reality it is 1.5
It may have doubled, but never more than doubled. When we investigated this matter closely, we found that variations in the reverse withstand voltage between the gate and cathode of the cathode segments arranged in large numbers on the cathode surface of the epitaxial GTO thyristor caused a drop from the theoretical controllable current. I understand. That is, since the cathode segment structure of the conventional epitaxial GTO thyristor is made in a mesa type as shown in FIG. The reverse breakdown voltage varies by about 30% due to
% variation, the reverse breakdown voltage of the segment varies, for example, in the range of toov to 130V, and at the final stage of turn-off, current concentrates in a portion where the breakdown voltage is not applied at 100VL, leading to breakdown. Such a problem also occurs in an epitaxial GTO thyristor in which the gate is provided in the n-base layer and the p-emitter layer is surrounded by the gate and arranged in a distributed manner.

An object of the present invention is to provide an epitaxial GTO thyristor in which variations in reverse breakdown voltage between the gate and emitter bridge, which are necessary for improving the current, are reduced between dispersed emitter electrodes.

[Means to solve the problem]

An epitaxial method in which an emitter layer of a second conductivity type, which is distributed over a base layer of a first conductivity type in which a gate electrode is provided, is formed via a layer of a first conductivity type with a low impurity concentration using epitaxial layer technology. In the Nakaru GTO thyristor,
It is assumed that the pn junction between the emitter layer of the second conductivity type and the layer of the first conductivity type with a low impurity concentration is exposed on the surface of the epitaxial layer.

[Effect]

When an emitter layer of the second conductivity type is formed on the base layer of the first conductivity type by selective diffusion, the impurity concentration of the base layer in contact with the pn junction between them differs between the part near the surface and the part away from the surface, and is growing exponentially. Therefore, in order to equalize the concentration at the junction between the gate main electrodes and to equalize the reverse breakdown voltage, it was necessary to etch down the high concentration portion of the gate. However, in an epitaxial layer in which the impurity concentration is the same everywhere, there is no need to etch down the gate, and a planar structure can be obtained in which the surface of the pn junction is left exposed. Therefore, since there is no problem of variations in the shape of mesa etching, there is no variation in the reverse breakdown voltage between the gate and emitter electrodes within the emitter electrode surface.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. In this GTo thyristor, a p emitter layer 1 and a p0 base layer 3 are formed in an n-type silicon substrate by impurity diffusion, and the original layer portion of the substrate remains as an n base layer 2. A p-epitaxial layer 4 with a low impurity concentration is laminated on this substrate, and an n-emitter layer 5 is formed in this layer by diffusion of impurities from the surface. Up to this point, the manufacturing process is similar to that of the GTO thyristor shown in FIG. Thereafter, a p° contact layer 10 is formed surrounding the n emitter layer 5 and reaching the p° base layer 3 from the surface of the epitaxial layer 4 without performing gate etching down. Therefore, the pn junction between the p'' layer 4 and the n emitter layer 5 is exposed on the surface of the epitaxial layer and has a brainer structure protected by the oxide film 9. A cathode electrode 7 is in contact with the p''' contact layer 10, a gate electrode 8 is in contact with the p''' contact layer 10, and an anode electrode 6 is in contact with the p emitter layer 1. Each electrode is formed by M. Since the gate electrode 8 is connected to the p0 diffused base layer 3 via the p4 contact layer 10, the gate impedance is reduced.

FIG. 3 shows another embodiment of the invention, in which a step is provided between the cathode electrode 7 and the gate electrode 8. FIG. This is because when the electrode body comes into pressure contact with the cathode electrode 7,
This is to prevent the gate-cathode connection from being short-circuited due to contact with the gate electrode 8. Since the gate electrode 8 is in direct contact with the p diffusion base layer 3, the gate impedance is low.
In this case as well, the exposed pn junction between the p′ epitaxial layer 4n emitter layer 5 is protected by the oxide film 9;
Further, the top thereof is covered with a conductive film, for example, an amorphous silicon film 11 as a field plate for mitigating an electric field when a reverse voltage is applied. By relaxing the surface electric field by the field plate, the breakdown voltage between the gate and the cathode can be further increased.

In the above embodiments, the gate electrode is provided on the p base layer, but the gate electrode is provided on the n base layer, and the GTO thyristor has an n-epitaxial layer laminated on the n base layer to increase the controllable current. This can also be done in the same way.

〔Effect of the invention〕

According to the present invention, the gate of a GTO thyristor has an epitaxial base layer with a low impurity concentration interposed between a base layer provided with a gate electrode and an adjacent dispersed emitter layer of opposite conductivity type in order to improve the am current. - Variation in the reverse breakdown voltage between emitter electrodes within the plane of the emitter layer can be reduced by forming the epitaxial layer and the emitter layer into a brainer structure. As a result, the reverse withstand voltage between the gate and emitter electrodes can be adjusted to a high value of, for example, 120v±194V, and compared to the conventional epitaxial GTO thyristor with a mesa structure, it is possible to obtain more than twice the performance with controllable current. became possible.

[Brief explanation of drawings]

Figure 1 shows an epitaxial GTO which is an embodiment of the present invention.
A cross-sectional view of a portion surrounding one n-emitter layer of a thyristor,
FIG. 2 is a cross-sectional view of a portion surrounding one n-emitter layer of a conventional epitaxial GTO thyristor, and FIG. 3 is a cross-sectional view of a portion surrounding one n-emitter layer of an epitaxial GTO thyristor according to another embodiment of the present invention. It is. 1: p emitter layer, 2: n base layer, 3: p base layer,
4: p-epitaxial layer, 5: n emitter layer, 6: anode electrode, 7: cathode electrode, 8: gate electrode, 1o
op' contact layer.

Claims (1)

[Claims] 1) An emitter layer of a second conductivity type distributed over a base layer of a first conductivity type in which a gate electrode is provided is formed via a layer of a first conductivity type with a low impurity concentration using epitaxial layer technology. An epitaxial gate turn-off thyristor characterized in that a pn junction between an emitter layer of a second conductivity type and a layer of a first conductivity type with a low impurity concentration is exposed at the surface of the epitaxial layer.