JPH02280334A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH02280334A JPH02280334A JP10206789A JP10206789A JPH02280334A JP H02280334 A JPH02280334 A JP H02280334A JP 10206789 A JP10206789 A JP 10206789A JP 10206789 A JP10206789 A JP 10206789A JP H02280334 A JPH02280334 A JP H02280334A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- bump
- transparent
- transparent conductive
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000011347 resin Substances 0.000 claims abstract description 41
- 229920005989 resin Polymers 0.000 claims abstract description 41
- 239000011231 conductive filler Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000206 photolithography Methods 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 5
- 239000011324 bead Substances 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000012508 resin bead Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 33
- MYRTYDVEIRVNKP-UHFFFAOYSA-N 1,2-Divinylbenzene Chemical compound C=CC1=CC=CC=C1C=C MYRTYDVEIRVNKP-UHFFFAOYSA-N 0.000 abstract description 4
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 4
- 239000002904 solvent Substances 0.000 abstract description 4
- 238000007747 plating Methods 0.000 abstract description 3
- 229920001971 elastomer Polymers 0.000 abstract description 2
- RRHGJUQNOFWUDK-UHFFFAOYSA-N Isoprene Chemical compound CC(=C)C=C RRHGJUQNOFWUDK-UHFFFAOYSA-N 0.000 abstract 1
- 239000000945 filler Substances 0.000 abstract 1
- 238000004528 spin coating Methods 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000004020 conductor Substances 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000000843 powder Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910021357 chromium silicide Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006355 external stress Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 241001600434 Plectroglyphidodon lacrymatus Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical class [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 235000008429 bread Nutrition 0.000 description 1
- -1 but as is well known Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 150000002815 nickel Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920002857 polybutadiene Polymers 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 239000010948 rhodium Substances 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 239000011882 ultra-fine particle Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置(以下ICと記す)の構造とその製
造方法に関し、特に外部接続電極である突出電極(以下
バンプと記す)の構造と、その製造方法に関するもので
、おもに半導体工業で利用されるものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of a semiconductor device (hereinafter referred to as IC) and its manufacturing method, and particularly relates to the structure of a protruding electrode (hereinafter referred to as bump) which is an external connection electrode. , relates to its manufacturing method and is mainly used in the semiconductor industry.
ICチップとリードフレーム或は回路基板等とを電気的
に接続する方法で一般的なものとしては、金、アルミニ
ウム、銅などの微細なワイヤを超音波或は熱圧着によっ
て接続するいわゆるワイヤボンディングが周知であり現
在に於いても主流をなしている。A common method for electrically connecting IC chips and lead frames or circuit boards is so-called wire bonding, which connects fine wires made of gold, aluminum, copper, etc. using ultrasonic waves or thermocompression bonding. It is well known and is still mainstream today.
しかしながら、近年ますます要求の強い「軽薄短小」と
いう言葉に代表される小型・薄型・高密度に加え、低コ
ストという観点からみるならばワイヤボンディングに係
るコストが実装費用の大半を占めている現状は時勢にそ
ぐわないものとなってきており、高密度実装に即した低
コストな実装技術の開発が望まれている。However, in recent years, in addition to compactness, thinness, and high density, which are typified by the words "light, thin, short, and small," which have been increasingly demanded, wire bonding costs account for the majority of mounting costs from the viewpoint of low cost. has become unsatisfactory with the times, and there is a need for the development of low-cost mounting technology suitable for high-density mounting.
この様な要求を満たし得るものとしてICチップの表面
に種々のバンプな設げ、このバンプを介してICチップ
を回路基板等に直接実装するワ°イヤレスボンディング
が提案され技術開発が進んでおり、一部実用に至ってい
る。Wireless bonding, in which various bumps are provided on the surface of an IC chip and the IC chip is directly mounted on a circuit board etc. via the bumps, has been proposed as a way to meet these demands, and technological development is progressing. Some of them have been put into practical use.
例えばフリップチップ方式では、外部接続電極として一
般的には半田バンプを形成し、接続する回路基板に位置
合わせした後、加熱による半田リフローによって接続す
るというものである。For example, in the flip-chip method, solder bumps are generally formed as external connection electrodes, aligned with the circuit board to be connected, and then connected by solder reflow by heating.
第5図は従来の一般的なフリップチップ接続のための半
田バンプを形成したICの断面図である。FIG. 5 is a cross-sectional view of an IC on which solder bumps are formed for conventional general flip-chip connection.
半導体基板1上にアルミニウムで電極パッド2を形成し
、この電極パッド2上に形成した絶縁膜6を開口し、さ
らにアルミニウム・クロム・銅より成るバリヤ層9を介
して半田バンプ10を形成したものである。An electrode pad 2 made of aluminum is formed on a semiconductor substrate 1, an insulating film 6 formed on the electrode pad 2 is opened, and a solder bump 10 is further formed through a barrier layer 9 made of aluminum, chromium, and copper. It is.
第6図は従来の一般的なフリップチップ方式で接続した
ICの断面図で、絶縁基板12上に、IC上の半田バン
プとの接続に対応した位置へ導体パターン11を形成し
、半田レジスト層16を設けた配線基板にICチップ1
6を位置合わせ後、全体を加熱し、半田をリフローして
接続する。FIG. 6 is a cross-sectional view of an IC connected by a conventional general flip-chip method, in which a conductive pattern 11 is formed on an insulating substrate 12 at a position corresponding to the connection with a solder bump on the IC, and a solder resist layer is formed. IC chip 1 is placed on the wiring board provided with 16
After positioning 6, heat the whole and reflow the solder to connect.
その他の方式として代表的なものにTAB(Tape
Automated Bonding )方式がある。Another typical method is TAB (Tape).
There is an automated bonding method.
第7図は従来の一般的なTAB方式ICの断面図で、絶
縁基板12上に導体パターン11aを形成し、ICチッ
プとの接続端部の配線を絶縁基板より延長して錫メツキ
を施した配線基板と、金バンプ14を形成したICチッ
プ16とを位置合わせ後、ヒートツール15を用いて熱
圧着し、金錫共晶によって接続するものである。FIG. 7 is a cross-sectional view of a conventional general TAB type IC, in which a conductor pattern 11a is formed on an insulating substrate 12, and the wiring at the connection end with the IC chip is extended from the insulating substrate and tin-plated. After aligning the wiring board and the IC chip 16 on which the gold bumps 14 are formed, they are bonded by thermocompression using the heat tool 15 and connected by gold-tin eutectic.
他の技術としては例えば、特開昭63−9942号公報
に述べられているような金バンプを形成したICチップ
と回路基板とを、樹脂が硬化する際に生じる収縮応力で
圧接接続するという方法もある。Another technique, for example, is a method described in Japanese Patent Application Laid-Open No. 63-9942, in which an IC chip on which gold bumps are formed and a circuit board are pressure-connected by the shrinkage stress generated when the resin hardens. There is also.
以上述べたこれら種々の方式は、何れも、半田・金・銅
などの金属から成るバンプを介して接続することを特徴
としているが、周知のように金属バンプは剛性が高く、
応力緩和効果が小さいために外部から応力が加わった場
合、ICチップ内部の故障を招く場合があり、又、回路
基板等との接続部分に不都合を生じることがある。These various methods described above are all characterized by connection via bumps made of metal such as solder, gold, or copper, but as is well known, metal bumps have high rigidity;
Since the stress relaxation effect is small, if stress is applied from the outside, it may cause a failure inside the IC chip, and may also cause problems at the connection portion with a circuit board or the like.
即ち、ICチップ内部の断線或はバンプ接続部分の電熱
及び剥離等による接続不良である。又バンプ形成工程も
長く、これに係るコストも実装費用を引き上げる一因と
なっているという問題があり改善が望まれている。That is, it is a connection failure due to a disconnection inside the IC chip or electrical heating or peeling of the bump connection portion. Furthermore, the bump forming process is long, and the cost associated with this process is also a cause of increasing mounting costs, which is a problem that is desired to be improved.
この様な要求に対し、例えば、特開昭58−38769
号公報のような導電弾性接着剤をスクリーン印刷でバン
プ形成して接続するという提案がなされている。この従
来に於けるバンプ形成方法によれば工程が短縮され、振
動などの外部応力にも強い接続が出来るという長所があ
る半面、ペースト状の接着剤でバンプ形成を行う場合、
スクリーン印刷の手法は分解能が低いため、形成される
バンプの形状は、バンプ径が小さくなるに伴い、円錐状
または半球状に限られてくるうえ、バンプピッチもほぼ
250μm程度が実用限界という不具合があった。In response to such requests, for example, Japanese Patent Application Laid-Open No. 58-38769
A proposal has been made to form bumps using a conductive elastic adhesive and connect them by screen printing, as disclosed in Japanese Patent Publication No. This conventional bump forming method has the advantage of shortening the process and making a connection that is resistant to external stresses such as vibrations. However, when forming bumps with a paste adhesive,
Since the screen printing method has a low resolution, the shape of the bumps formed is limited to conical or hemispherical shapes as the bump diameter becomes smaller, and the practical limit of the bump pitch is approximately 250 μm. there were.
即ち、隣合った接着剤同士が短絡してしまうためにバン
プが形成出来ないという問題がある。That is, there is a problem that bumps cannot be formed because adjacent adhesives are short-circuited.
そこでこの様な課題に対して例えば、特開昭63−28
3144号公報にあるような提案がなされている。Therefore, for example, Japanese Patent Application Laid-Open No. 63-28
A proposal such as that described in Publication No. 3144 has been made.
これは感光性樹脂に金・パラジウム・ロジウム・金メツ
キしたニッケル等の金属粉を配しフォトリソ工程により
形成するというものである。This method involves disposing metal powder such as gold, palladium, rhodium, or gold-plated nickel on a photosensitive resin and forming it by a photolithography process.
しかしながら、光透過性の無い導電性粉体では、樹脂中
でのこの導電性粉体の占有率が高くなるに従い、フォト
リソグラフィの分解能は低下していくという不都合が生
じる。However, conductive powder without light transmittance has the disadvantage that as the occupancy of the conductive powder in the resin increases, the resolution of photolithography decreases.
さらに、導電性粉体の含有率が低くなるに従い、バンプ
自身の抵抗値は上昇し、外部との接続は不向きなものに
なるという問題がある。Furthermore, as the content of the conductive powder decreases, the resistance value of the bump itself increases, making it unsuitable for connection to the outside.
即ち、照射される紫外光が金属粉によって遮られ、電極
バンドに近い部分は充分に樹脂の化学反応が進行せず、
独立したバンプが形成出来ないという問題があるうえ、
前記のような貴金属粉の使用による実装費用の増大も無
視出来ない。しかしながら、高密度実装の必要からより
一層のマイクロピッチ化が要望されており、低コストで
信頼度の高い接続が求められている。In other words, the irradiated ultraviolet light is blocked by the metal powder, and the chemical reaction of the resin does not proceed sufficiently in the area near the electrode band.
In addition to the problem that independent bumps cannot be formed,
The increase in mounting costs due to the use of precious metal powder as described above cannot be ignored. However, due to the need for high-density packaging, there is a demand for further micropitch, and a low-cost and highly reliable connection is required.
本発明は上記従来の課題に鑑みなされたものであり、多
くの工程を必要とせずバンプ形成出来、かつ寸法精度が
高く接続信頼性に優れたバンプを持つ半導体装置及びそ
の製造方法を提供することが目的である。The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device having bumps that can form bumps without requiring many steps, have high dimensional accuracy, and excellent connection reliability, and a method for manufacturing the same. is the purpose.
上記目的を達成するため、本発明のバンプは以下に記載
の構造及び製造方法により形成する。In order to achieve the above object, the bump of the present invention is formed by the structure and manufacturing method described below.
(イ)素子を形成した後、外部との接続のための電極パ
ッドを形成した半導体基板に、この電極パッドに対応し
た位置に開口部を設けた絶縁膜を形成した後、この絶縁
膜を介して外部接続のための突出電極を形成した半導体
装置に於て、突出電極は、有機系樹脂からなる透明ビー
ズの表面に透明導電物質を被着した導電フィラーを混在
した感光性樹脂からなることを特徴とする。(a) After forming the element, an insulating film with openings corresponding to the electrode pads is formed on the semiconductor substrate on which electrode pads for connection with the outside are formed, and then the insulating film is In a semiconductor device in which a protruding electrode is formed for external connection, the protruding electrode is made of a photosensitive resin mixed with a conductive filler made by coating a transparent conductive substance on the surface of a transparent bead made of an organic resin. Features.
(ロ)半導体基板の電極パッド領域を開口した絶縁膜上
の全面に、透明な有機系樹脂ビーズの表面に透明導電物
質な被着した導電フィラーを混在した感光性樹脂からな
る導電性樹脂層を形成する工程と、フォトリソグラフィ
により該導電性樹脂層をバターニングし、弾性バンプを
形成する工程とを有することを特徴とする。(b) A conductive resin layer made of a photosensitive resin mixed with a conductive filler coated with a transparent conductive material on the surface of transparent organic resin beads is applied to the entire surface of the insulating film with openings in the electrode pad area of the semiconductor substrate. and a step of patterning the conductive resin layer by photolithography to form elastic bumps.
本発明によれば、バンプ形成の手段がフォトリソグラフ
ィであるため、従来のメツキ或は蒸着などの設備が不要
となり、形成に係る費用及び時間が大幅に短縮できる。According to the present invention, since the means for forming bumps is photolithography, conventional equipment such as plating or vapor deposition is not required, and the cost and time involved in forming bumps can be significantly reduced.
さらに、透明導電フィラーによって確実な露光・現像処
理が可能になる事及び、構成部材が主に樹脂であること
から、高精度で応力緩和性に優れた接続信頼性の高い弾
性バンプの形成が可能となる。Furthermore, because the transparent conductive filler enables reliable exposure and development processing, and because the component is mainly resin, it is possible to form elastic bumps with high precision, excellent stress relaxation properties, and high connection reliability. becomes.
以下図面に基づいて本発明の好適な実施例を説明する。 Preferred embodiments of the present invention will be described below based on the drawings.
第1図は本発明による半導体装置の一実施例を示した断
面図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.
半導体基板1上にアルミニウムとニッケルとを積層した
電極パッド2aを形成し、さらに絶縁膜6を介して感光
性樹脂5と透明導電フィラー6とから成る弾性バンプ4
を形成したものである。An electrode pad 2a made of laminated aluminum and nickel is formed on a semiconductor substrate 1, and an elastic bump 4 made of a photosensitive resin 5 and a transparent conductive filler 6 is further formed with an insulating film 6 interposed therebetween.
was formed.
第2図は弾性バンプ4の構成部材である透明導電フィラ
ー6の一実施例を示した断面図で、スチレン及びジビニ
ルベンゼンより成る透明樹脂球6aの表面に、インジウ
ム・錫オキサイド(以下ITOと記す)からなる透明導
電物質層6bを被着形成したものである。FIG. 2 is a sectional view showing an embodiment of the transparent conductive filler 6, which is a component of the elastic bump 4. Indium tin oxide (hereinafter referred to as ITO) is applied to the surface of the transparent resin sphere 6a made of styrene and divinylbenzene. ) is formed by depositing a transparent conductive material layer 6b.
この透明導電物質層6bは上記のITO以外に、錫オキ
サイド、クロムシリサイド等の透明導電物質であれば適
応できる。This transparent conductive material layer 6b can be made of any transparent conductive material other than the above-mentioned ITO, such as tin oxide or chromium silicide.
透明導電物質層6bの厚みは0.1μm〜0,3μmが
適当であり、0.1μm以下では接続抵抗が増大し、0
3μm以上になると透明度の減少によって露光及び現像
工程での分解能が悪くなる。The appropriate thickness of the transparent conductive material layer 6b is 0.1 μm to 0.3 μm, and if it is less than 0.1 μm, the connection resistance increases and the thickness is 0.1 μm to 0.3 μm.
If the thickness exceeds 3 μm, the resolution in the exposure and development steps will deteriorate due to a decrease in transparency.
この透明導電物質層6bは、ITOの超微小粒子を適当
な溶媒に分散した溶液に、透明樹脂球6aを浸漬して乾
燥し、熱処理を施すと得られるものである。This transparent conductive material layer 6b is obtained by immersing the transparent resin sphere 6a in a solution in which ultrafine particles of ITO are dispersed in a suitable solvent, drying it, and subjecting it to heat treatment.
又、錫オキサイドの場合も同様手法で形成出来るが、ク
ロムシリサイドの場合にはスパタリングによって形成す
る。Further, tin oxide can be formed using the same method, but chromium silicide can be formed by sputtering.
透明樹脂球6゛aの大きさは、形成するバンプの高さが
およそ20μm迄の場合には5μm程度、それ以上のバ
ンプ高さの場合には10μm程度のものを使用すると好
結果が得られる。The size of the transparent resin sphere 6a is about 5 μm if the height of the bump to be formed is up to about 20 μm, and if the height of the bump is higher than that, good results can be obtained by using a size of about 10 μm. .
第3図は半導体基板(シリコンウェハ)上に、本発明の
弾性バンプを形成する工程を示したものである。FIG. 3 shows the process of forming elastic bumps of the present invention on a semiconductor substrate (silicon wafer).
まず第3図(a)に示すように、電極パッド2及び絶縁
膜3を形成した半導体基板1に、透明導電フィラー6を
65重量%配し、溶媒を加えて粘度を調整したインプレ
ンゴム及びビスアジド系の感光性樹脂をスピンコーター
によって均一塗布し導電性樹脂層7を形成する。First, as shown in FIG. 3(a), 65% by weight of a transparent conductive filler 6 is placed on a semiconductor substrate 1 on which an electrode pad 2 and an insulating film 3 are formed, and a solvent is added to adjust the viscosity of imprene rubber and bisazide. A conductive resin layer 7 is formed by uniformly applying a photosensitive resin using a spin coater.
透明導電フィラー6の感光性樹脂に対する混合率は45
重量%〜70重量%が最も適当である。The mixing ratio of the transparent conductive filler 6 to the photosensitive resin is 45
% to 70% by weight is most suitable.
この感光性樹脂の場合、バンプ形成後の耐熱温度は15
0℃程度であるが、環化ブタジェン系の樹脂を使用した
場合には300℃程度の耐熱性のものが得られる。In the case of this photosensitive resin, the heat resistance temperature after bump formation is 15
The heat resistance is about 0°C, but if a cyclized butadiene resin is used, a heat resistant product of about 300°C can be obtained.
この感光性樹脂には、塗布に適するような一定の粘度を
保持するために、揮発性の溶媒を入れているが、これは
露光工程の前に温度80℃前後で行うブリ・ベーク処理
によって揮発消失してしまうものである。This photosensitive resin contains a volatile solvent in order to maintain a constant viscosity suitable for coating, but this is volatilized by the yellowtail bake treatment performed at a temperature of around 80°C before the exposure process. It is something that disappears.
従って、透明導電フィラー6の含有率は、半導体基板(
シリコンウェハ)へスピンコーター或はスクリーン印刷
機等によって塗布する時点では少なくとも70重量%以
下となっているものの、バンプ形成完了時点では45重
量%〜70重量%の範囲にあるように予め調整しておく
。Therefore, the content rate of the transparent conductive filler 6 is the same as that of the semiconductor substrate (
Although it is at least 70% by weight when applied to silicon wafers using a spin coater or screen printer, it is adjusted in advance so that it is within the range of 45% to 70% by weight when bump formation is completed. put.
次に第3図(b)に示すように、塗布した感光性の導電
性樹脂層7にガラスマスク8を介して紫外線を照射し、
ガラスマスク8のパターンを所定の位置に焼き付け、露
光処理を行う。Next, as shown in FIG. 3(b), the coated photosensitive conductive resin layer 7 is irradiated with ultraviolet rays through a glass mask 8.
The pattern of the glass mask 8 is printed at a predetermined position, and an exposure process is performed.
透明導電フィラー6を混入する感光性樹脂5がネガティ
ブ・タイプの場合には、紫外線照射を受けない所は、次
工程の現像処理によって除去される。If the photosensitive resin 5 mixed with the transparent conductive filler 6 is of negative type, the portions not exposed to ultraviolet rays are removed by the next development process.
第3図(b)では感光性樹脂5にネガティブ拳タイプを
使用した例を述べたが、ポジティブ・タイプの場合でも
露光の際のマスキングを反転させれば同様に使用出来る
。Although FIG. 3(b) shows an example in which a negative fist type photosensitive resin 5 is used, a positive type can also be used in the same way by reversing the masking during exposure.
次に第3図(C)に示すように、現像処理を行うと、前
述したように紫外線照射を受けた所は弾性バンプ4とな
って残る。Next, as shown in FIG. 3(C), when a development process is performed, the areas exposed to ultraviolet rays remain as elastic bumps 4 as described above.
本工程ではこの後、温度145℃前後でポストベーク処
理を行って感光性樹脂5を安定化させ弾性バンプ4を電
極パッド2a上に形成する。In this step, a post-baking process is then performed at a temperature of about 145° C. to stabilize the photosensitive resin 5 and form the elastic bumps 4 on the electrode pads 2a.
本発明による弾性バンプを有する半導体装置を他の回路
基板等に実装する方法としては、位置合わせ後に互いを
圧接したままポストベーク処理を行い、接着して接続す
る方法と、ポストベーク処理後に他の回路基板等へバネ
或は封止樹脂等で圧接固定して接続する方法とがある。As methods for mounting the semiconductor device having elastic bumps according to the present invention on other circuit boards, etc., there are two methods: After alignment, post-bake processing is performed while the semiconductor device is in pressure contact with each other, and the method is bonded and connected. There is a method of connecting to a circuit board or the like by pressing and fixing it with a spring or sealing resin.
前者の場合、145℃前後の熱が加わるため、回路基板
等の接続端子部には酸化防止のために金メツキ等を施し
ておくとよい。In the former case, since heat of around 145° C. is applied, it is advisable to apply gold plating or the like to the connection terminals of the circuit board and the like to prevent oxidation.
第4図は、ポストベーク処理を利用して接着接続した一
実施例の断面図を示したものである。FIG. 4 shows a cross-sectional view of an embodiment in which adhesive connection is made using post-bake processing.
この方法で接続した場合には、絶縁基板12上の導体パ
ターン11と半導体基板1上の弾性バンプ4との接続部
の保護及び接着信頼性を高めるために、全体を樹脂封止
することが望ましい。When connected using this method, it is desirable to seal the entire body with resin in order to protect the connection between the conductor pattern 11 on the insulating substrate 12 and the elastic bumps 4 on the semiconductor substrate 1 and to improve adhesion reliability. .
本発明では透明導電フィラー6が球体の実施例を述べた
が、透明導電フィラー6の形状はこれにとどまるもので
はなく、不完全球体、楕円体、立方体、直方体、その他
の多角体にも適応し、さらに透明樹脂球6aに代えて透
明なガラスピーズ或は透明な導電性プラスチック等にも
適応することは明らかである。In the present invention, an embodiment in which the transparent conductive filler 6 is a sphere has been described, but the shape of the transparent conductive filler 6 is not limited to this, and may also be applied to an incomplete sphere, an ellipsoid, a cube, a rectangular parallelepiped, and other polygons. Furthermore, it is obvious that transparent glass beads, transparent conductive plastics, etc. can be used in place of the transparent resin bulb 6a.
また、電極バッドの一般的な構成部材であるアルミニウ
ムは、表面に接触抵抗値を増大させる酸化膜を形成し易
く、プリベーク及びポストベーク等の熱処理によってこ
れがいっそう顕著になるため、本発明ではアルミニウム
上にニッケルを積層した電極バッド2aを介して弾性バ
ンプ4を形成している。In addition, aluminum, which is a common component of electrode pads, tends to form an oxide film on its surface that increases contact resistance, and this becomes even more noticeable after heat treatments such as pre-bake and post-bake. Elastic bumps 4 are formed via electrode pads 2a in which nickel is laminated on the electrode pads 2a.
このニッケルはアルミニウム表面の酸化防止が目的であ
るため、ポストベーク処理時にかかる150℃前後の温
度では酸化し難い他の物質、例えば金、銀、パラジウム
等を用いてもよい。Since the purpose of this nickel is to prevent oxidation of the aluminum surface, other substances such as gold, silver, palladium, etc., which are difficult to oxidize at temperatures of around 150° C. applied during post-baking treatment, may be used.
第8図は、第1図に於ける本実施例の電極パッド2aの
他の形成方法の一実施例を示した断面図である。FIG. 8 is a sectional view showing another embodiment of the method of forming the electrode pad 2a of this embodiment shown in FIG.
まず、第8図(a)に示すように、半導体基板1上に、
アルミニウムで電極バッド2を形成し、さらに絶縁膜6
を形成し電極バッド2を開口した後、ニッケルから成る
導電膜17を全面に被着形成する。その後全面に導電性
樹脂層を形成し、フォトリソグラフィにより弾性バンプ
を形成する。First, as shown in FIG. 8(a), on the semiconductor substrate 1,
An electrode pad 2 is formed of aluminum, and an insulating film 6 is further formed.
After forming the electrode pad 2 and opening the electrode pad 2, a conductive film 17 made of nickel is deposited over the entire surface. After that, a conductive resin layer is formed on the entire surface, and elastic bumps are formed by photolithography.
この導電膜17は第8図(b)に示すように、形成した
弾性バンプ4をエツチングマスクとし、バンプ下部以外
の導電膜17をエツチングによって除去することによっ
て導電層17aを形成する。As shown in FIG. 8(b), this conductive film 17 is formed by using the formed elastic bumps 4 as an etching mask and removing the conductive film 17 except under the bumps by etching, thereby forming a conductive layer 17a.
以上説明したように、本発明によれば、透明導電フィラ
ーを導入し、フォトリソグラフィを応用することにより
、従来の半導体製造設備をそのまま流用でき、従来に比
べ、バンプ形成に係る時間の大幅な短縮が可能となって
、高精度なバンプ形成の低コスト化が容易に行える。As explained above, according to the present invention, by introducing a transparent conductive filler and applying photolithography, conventional semiconductor manufacturing equipment can be used as is, and the time required for bump formation is significantly reduced compared to the conventional method. This makes it possible to easily form high-precision bumps at low cost.
さらに、バンプ高さの設計自由度が大きく、形成したバ
ンプが弾性に富む樹脂バンプであるため、外部からの応
力に対する緩和力が大きく、圧接による実装構造の場合
、接続信頼性が高い等の利点の他、バンプピッチ30μ
m以下が容易に実現できるため、ICチップの大幅な多
端子化が可能となる。Furthermore, there is a large degree of freedom in designing the bump height, and since the formed bumps are made of highly elastic resin bumps, they have a large ability to relax external stress, and in the case of a mounting structure using pressure welding, there are advantages such as high connection reliability. In addition, bump pitch 30μ
m or less can be easily achieved, making it possible to significantly increase the number of terminals in an IC chip.
第1図シま本発明による半導体装置の一実施例を示す断
面図、第2図は本発明におけるバンプを構成する部材の
一つである透明導電フィラーの一実施例を示す断面図、
第3図(a)〜(C)は本発明における半導体基板上へ
のバンプ形成を示す一実施例を工程順に示す断面図、第
4図は本発明における半導体装置をポストベーク処理を
利用して接着接続した一実施例を示もす断面図、第5図
は従来の一般的なフリップチップ接続のための半田バン
プを形成した半導体装置を示す断面図、第6図は従来の
一般的なフリップチップ方式で接続した半導体装置を示
す断面図、第7図は従来の一般的なTAB方式で接続し
た半導体装置を示す断面図、第8図(a)及びfb)は
本発明における半導体装置の形成方法の一実施例を示す
断面図である。
4・・・・・・弾性バンプ、6a・・・・・・透明樹脂
球。
5・・・・・・感光性樹脂、6b・・・・・・透明導電
物質層、6・・・・・・透明導電フィラー
第1図
1′
半導412反
(b)
第2図
(C)
4、弾性パン?
/
第5図
之ρ、牛日ノVンプ
+S停基汲
2電極パツド
第6図
第7図
12、結縛基板
+6.1c+プフ゛FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention; FIG. 2 is a sectional view showing an embodiment of a transparent conductive filler which is one of the members constituting the bump in the present invention;
3(a) to 3(C) are cross-sectional views illustrating an example of forming bumps on a semiconductor substrate according to the present invention in the order of steps, and FIG. FIG. 5 is a cross-sectional view showing a semiconductor device formed with solder bumps for conventional general flip-chip connection, and FIG. 6 is a cross-sectional view showing an example of a conventional general flip-chip connection. FIG. 7 is a cross-sectional view showing a semiconductor device connected by the chip method, FIG. 7 is a cross-sectional view showing a semiconductor device connected by the conventional general TAB method, and FIGS. 8(a) and fb) are the formation of the semiconductor device according to the present invention. FIG. 3 is a cross-sectional view illustrating an embodiment of the method. 4...Elastic bump, 6a...Transparent resin ball. 5...Photosensitive resin, 6b...Transparent conductive material layer, 6...Transparent conductive filler Fig. 1 1' Semiconductor 412 (b) Fig. 2 (C ) 4. Elastic bread? / Figure 5 ρ, Ushihi no V pump + S stop base pump 2 electrode pad Figure 6 Figure 7 Figure 12, binding board + 6.1c + pump
Claims (2)
ッドを形成した半導体基板に、該電極パッドに対応した
位置に開口部を設けた絶縁膜を形成し該絶縁膜を介して
外部接続のための突出電極を形成した半導体装置に於て
、前記突出電極は、有機系樹脂からなる微細な透明ビー
ズの表面に透明導電物質を被着した導電フィラーを混在
させた感光性樹脂からなることを特徴とする半導体装置
。(1) After forming an element, an insulating film with an opening at a position corresponding to the electrode pad is formed on the semiconductor substrate on which electrode pads for connection with the outside are formed, and an insulating film is formed to connect the external In a semiconductor device in which a protruding electrode for connection is formed, the protruding electrode is made of a photosensitive resin in which a conductive filler is mixed with a transparent conductive substance coated on the surface of fine transparent beads made of an organic resin. A semiconductor device characterized by:
の全面に、透明な有機系樹脂ビーズの表面に透明導電物
質を被着した導電フィラーを混在した感光性樹脂からな
る導電性樹脂層を形成する工程と、フォトリソグラフィ
により該導電性樹脂層をパターニングし、弾性バンプを
形成する工程とを有することを特徴とする半導体装置の
製造方法。(2) A conductive resin layer made of a photosensitive resin mixed with a conductive filler made by coating the surface of transparent organic resin beads with a transparent conductive substance is applied to the entire surface of the insulating film with openings in the electrode pad area of the semiconductor substrate. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming an elastic bump; and patterning the conductive resin layer by photolithography to form an elastic bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10206789A JPH02280334A (en) | 1989-04-21 | 1989-04-21 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10206789A JPH02280334A (en) | 1989-04-21 | 1989-04-21 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02280334A true JPH02280334A (en) | 1990-11-16 |
Family
ID=14317421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10206789A Pending JPH02280334A (en) | 1989-04-21 | 1989-04-21 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02280334A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0311740A (en) * | 1989-06-09 | 1991-01-21 | Ootex Kk | Formation of bump electrode of semiconductor element |
| US5846853A (en) * | 1991-12-11 | 1998-12-08 | Mitsubishi Denki Kabushiki Kaisha | Process for bonding circuit substrates using conductive particles and back side exposure |
| EP1018761A4 (en) * | 1997-08-21 | 2000-12-06 | Citizen Watch Co Ltd | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF |
| WO2008078478A1 (en) * | 2006-12-27 | 2008-07-03 | Panasonic Corporation | Conductive bump, method for manufacturing the conductive bump, semiconductor device and method for manufacturing the semiconductor device |
| WO2009028239A1 (en) * | 2007-08-27 | 2009-03-05 | Nec Corporation | Structure for mounting semiconductor device and method for mounting semiconductor device |
| JP2016115832A (en) * | 2014-12-16 | 2016-06-23 | 富士通株式会社 | Bump forming material, bump forming method and semiconductor device |
-
1989
- 1989-04-21 JP JP10206789A patent/JPH02280334A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0311740A (en) * | 1989-06-09 | 1991-01-21 | Ootex Kk | Formation of bump electrode of semiconductor element |
| US5846853A (en) * | 1991-12-11 | 1998-12-08 | Mitsubishi Denki Kabushiki Kaisha | Process for bonding circuit substrates using conductive particles and back side exposure |
| EP1018761A4 (en) * | 1997-08-21 | 2000-12-06 | Citizen Watch Co Ltd | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF |
| WO2008078478A1 (en) * | 2006-12-27 | 2008-07-03 | Panasonic Corporation | Conductive bump, method for manufacturing the conductive bump, semiconductor device and method for manufacturing the semiconductor device |
| JPWO2008078478A1 (en) * | 2006-12-27 | 2010-04-15 | パナソニック株式会社 | Conductive bump and method for forming the same, and semiconductor device and method for manufacturing the same |
| US7928566B2 (en) | 2006-12-27 | 2011-04-19 | Panasonic Corporation | Conductive bump, method for manufacturing the conductive bump, semiconductor device and method for manufacturing the semiconductor device |
| KR101155709B1 (en) * | 2006-12-27 | 2012-06-12 | 파나소닉 주식회사 | Conductive bump, method for manufacturing the conductive bump, semiconductor device and method for manufacturing the semiconductor device |
| JP5003689B2 (en) * | 2006-12-27 | 2012-08-15 | パナソニック株式会社 | Conductive bump |
| WO2009028239A1 (en) * | 2007-08-27 | 2009-03-05 | Nec Corporation | Structure for mounting semiconductor device and method for mounting semiconductor device |
| JP5333220B2 (en) * | 2007-08-27 | 2013-11-06 | 日本電気株式会社 | Semiconductor device mounting structure and semiconductor device mounting method |
| JP2016115832A (en) * | 2014-12-16 | 2016-06-23 | 富士通株式会社 | Bump forming material, bump forming method and semiconductor device |
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