JPH02280413A - Basic logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a basic logic circuit using a compound semiconductor FET, and particularly to an inverter circuit used in a gate array.

<Prior Art> A basic logic circuit applied to a compound semiconductor integrated circuit is reported in the Institute of Electronics and Communication Engineers Research Report 1CD87-a'1r15Q Gate GaAs Gate Array. Buffer 1-doped FET logic C is written as BFL. )It has been known. This BFL is composed of a compound semiconductor FET typically made of GaAs, which is a depression type FET that is easy to manufacture. In addition, BFLs have the characteristics of large operating margins and high-speed switching, and are one of the earliest circuits to be considered as basic circuits for compound semiconductor integrated circuits at the medium-scale integrated circuit (MSI) level. Various high speed integrated circuits have been realized.

FIG. 4 shows an inverter circuit using a BFL as a conventional example. The inverter section composed of the loads F, E T 4 and the switching FET 6 includes the switching FET 6
generates an inverted signal of the input signal applied to the input signal (IN). FET? , FET 9, and diode 8 amplify the output signal of the inverter section and drive the next stage circuit. Diode 8 is a level shift diode for matching the DC level of the output signal of the inverter section and the input signal level of the buffer 1 section,
This number is optimized depending on the threshold voltage of the FET constituting the inverter section, the power supply voltage (Vdd and Vss), etc. 1 to reduce power consumption as in the example shown in Figure 4.
A circuit optimized using one level shift diode can be integrated at the large scale integrated circuit (LSI) level, and attempts are being made to apply it to gate arrays and the like.

In addition, as an inverter circuit in which the inverter section is configured by a series connection of a switching FET and a depletion type FET as a load element, by using an enhancement type FETt as a switching FET,
Direct coupled FE without level shift circuit
Circuits such as T logic (DCFL) and Schottky diode FET logic (SDFL) using diode logic have also been put into practical use in compound semiconductor integrated circuits.

<Problems to be Solved by the Invention> In general, circuits that operate at high speed consume large amounts of power, while circuits that do not require high-speed operation consume less power. It is necessary to perform power optimization design. Usually, each functional circuit is optimized by adjusting the size of the elements constituting the circuit according to its power consumption. Therefore, when configuring an integrated circuit whose purpose and application are clear from the beginning, it is possible to optimize the function of each circuit in advance and determine the element size. However, in the case of integrated circuits, such as gate arrays, in which the elements that make up the circuit are built in from the beginning and the desired circuit function is achieved through wiring, it is not possible to optimize each functional circuit. However, it was necessary to configure the entire integrated circuit with circuits with high power consumption redundancy, or to partially incorporate low power consumption cells of different element sizes. This limits the degree of freedom in circuit design and reduces cell utilization.

The present invention has been made in view of the above problems, and provides a low power consumption type inverter circuit suitable for use in low power consumption basic logic circuits, especially gate arrays, thereby increasing flexibility in integrated circuit design. The purpose is to improve the cell utilization rate.

<Means for Solving the Problems> In order to achieve the above object, a basic logic circuit according to the present invention includes a switching FET, a load FET using a depletion type FET, and a load current limiting element. The load current limiting element is connected between the gate and source of the switching FET, and the switching FET is connected to the gate of the switching FET.
, and the source is used as an output terminal.

<Function> For example, in an inverter circuit, switching FET
When the resistance is low (ON state), current flows from high potential to low potential. At this time, in the basic logic circuit according to the present invention, the gate potential of the depletion type FET used as the load element is lowered due to the voltage drop caused by the load current limiting element. For this purpose, the load FE
Since T is in a high resistance state, power consumption is reduced.

<Example> FIG. 1 is a block diagram of a basic logic circuit of the present invention.

Depletion type F between high potential Vdd and low potential VSSO
A load FET I using an ET and a switching FET 3 are connected via a load current limiting element 2. This load current limiting element 2 is connected between the gate and source of the load FET 1, and uses the gate of the switching FET 8 as an input terminal (IN) and the source of the load FETI as an output terminal (OUT). As the load current limiting element 2, a resistor, a depression type FET with its gate and source shorted, a depression type FET with its gate and drain shorted, or a diode can be used.

When a low logic level is input to the input terminal (IN), the switching FET 8 has a high resistance, and the current flowing to the low potential Vss through the load current limiting element 2 is almost zero.

Therefore, the voltage drop caused by the load current limiting element 2 is almost zero, and the current consumed at this time is comparable to that of a conventional circuit in which the load element is a depletion type FET with its gate and source shorted.

When a high logic level is input to the input terminal IN, the switching FET 8 has a low resistance, so a current flows from the high potential Vdd to the low potential Vss. Most of the static power is consumed at this time in both the conventional circuit and the circuit according to the present invention, but in the case of the circuit according to the present invention, the voltage drop due to the load current limiting element 2 is caused by the voltage drop across the load FET 1. In order to lower the gate potential, the load F
ET1 has a high resistance and the current consumption of the circuit becomes small.

FIG. 2 shows an example in which a resistor of Ω is used for 2 as a load current limiting element in the basic logic circuit of the present invention and applied to a BFL. In this example, the number of level shift diodes is optimized to 1, so switching FET6
The threshold voltages of the load FET 4 and the load FET 4 are -0, 2v and -0, 5v, respectively. Also, if the power supply voltage is Vdd=OV
, Vss=-1.5V, Vpd--2V. The third example is the cono circuit ODC transfer characteristics and the current consumption of the inverter section.
As shown in the figure. In the figure, 81 indicates the current consumption of the inverter section, and 32 indicates the DC transfer characteristic. It can be seen that the current in the inverter section hardly flows when the input voltage is below the logic threshold, but begins to flow when the input voltage exceeds this.

For comparison, the characteristics of the conventional BFL circuit shown in FIG. 4 are shown in FIG. In the figure, 51 is the current consumption of the inverter section, and 52 is the DC transfer characteristic.

Note that the element constants and power supply voltage of the elements constituting one circuit other than the load current limiting element 5 are the same as those of the circuit of the present invention shown in FIG. Comparing 51 with al showing the current consumption of the inverter section in FIG. 3 and FIG. 5, it can be seen that the current consumption during the period when the inverter section outputs a low level is reduced to about half. Also, the DC transfer characteristics of both 32 and 52
A comparison shows that there is almost no difference in logic level, and it is possible for the circuit of the present invention and the conventional circuit to coexist.

In this example, a resistor is used as the load current limiting element, but other devices such as a depletion type FET with the gate and source shorted, a depletion type FET with the gate and drain shorted, or a diode can also be used. Similar effects can be expected even if the movement occurs.

<Effects of the Invention> As explained above, according to the present invention, the switching FE
When T is in the ON state, the gate potential of the load FET is lowered due to the voltage drop caused by the load current limiting element and the load FET enters a high resistance state, reducing the current consumption, thus forming a low power consumption basic logic circuit. can do. Also,
The power consumption of the basic logic circuit can be reduced by simply adding a load current limiting element without changing any element parameters such as element size, increasing the degree of freedom in circuit design and improving cell utilization.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of the basic logic circuit of the present invention, Figure 2 is a circuit diagram of an embodiment of the present invention, Figure 8 is a characteristic diagram of the embodiment of the present invention, and Figure 4 is a circuit diagram of a conventional example. , FIG. 5 is a characteristic diagram of a conventional example. 1.4... Load FET, 2... Load current limiting element, 8.6... Switch notching FET, 5... Resistor,
7.9... Paris 77FET, 8... Level shift diode, 81... Inverter section current consumption, 32.
...DC transmission characteristics. Agent Patent attorney Takeshi Sugiyama (1 other person) dd 1/, (5' 1/, 4 Vjn (V) Suitable figure 3 dd dd Pd Fig. 4

Claims (1)

[Claims] 1. A switching FET, a load FET using a depletion type FET, and a load current limiting element, the load current limiting element being connected between the gate and source of the load FET. A basic logic circuit characterized in that the switching FET is connected to the gate, and the source is used as an output terminal.