JPH0228266B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MIS type semiconductor integrated circuit.

Generally, in MIS type integrated circuits, the input gate of the MIS transistor is extremely vulnerable to electrostatic damage.
An electrostatic discharge protection circuit is provided between the external connection terminal and the internal operating circuit area to prevent the internal circuit from being destroyed by static electricity or surge pulses. For example, as a conventionally used protection circuit, see Figure 1a.
Alternatively, there is a circuit as shown in b. In the figure a, 11 is a bonding electrode, 12,
14 is a protection resistor, 13 is an MIS transistor whose gate is the upper wiring metal, 15 is a gate control diode, and 16 is an internal transistor. Furthermore, in Figure b, 17
represents a diffused layer resistor and a diode formed from the diffused layer and the substrate. The protection circuit shown on the A side of the figure protects the internal area shown on the B side from electrostatic damage, but in either case, the protection method is to prevent a large voltage drop by flowing current. By combining a resistive element that generates a high current and an active element that does not allow any current to flow at low applied voltages, but allows a large current to flow only when a voltage above a certain value is applied, and has reproducible deceptive characteristics, When a high voltage pulse is applied to the input terminal, by letting the false charge escape through the current path composed of the resistive element and the active element, the internal transistor has a voltage that is limited by the active element, that is, the breakdown voltage of the internal transistor. The first protection is to ensure that only a low voltage is applied to the
In the figure, 12 and 14 are the resistance elements.
The active elements 13, 15 or 17 play the role of deception.

These input protection circuits are generally designed to withstand applied pulses of about 200 to 300V, but if you are fooled, the value of the protective resistance element 12 is approximately 1kΩ.
In addition, in order to avoid melting or destruction of the resistor element due to the large current instantaneously flowing when a high voltage pulse is applied, it is necessary to increase the current capacity by increasing the pattern width. A considerable pattern area is required to form the pattern. For example, as a protective resistance element, layer resistance 20Ω/□
When using polycrystalline silicon of approximately
An area of 100 μm square is required. Therefore, as shown in FIG. 2, in the conventional MIS type semiconductor integrated circuit, a large number of bonding electrodes 21 and input protection circuits 22 are arranged around the chip, which reduces the area that can be used as an internal area. However, it had the disadvantage of poor chip utilization efficiency.

The present invention solves the above-mentioned drawbacks by using the available unused area under the bonding electrode in an MIS type semiconductor integrated circuit to form an input protection resistor, and improves the effective use of the chip. The present invention provides a semiconductor device that achieves reduction in area.

The contents of the present invention will be explained in detail below.

FIG. 3 shows an embodiment of the present invention and corresponds to FIG. 2 of the prior art. 31 in figure
3 represents a bonding electrode, 32 represents an input protection circuit, and an input protection resistor is formed in the region below 31 in the figure. A diffusion layer resistor may be considered as the input protection resistor, but this is not preferable because it increases the input capacitance and limits the operating speed in the input protection circuit portion. A resistive material formed on a diffusion layer such as polycrystalline silicon is preferable. Furthermore, it is possible to form not only the input protection resistor but also the entire input protection circuit under the bonding electrode, but in that case, the electrostatic protection effect may be reduced. Therefore, it is important to form only the input protection resistor under the bonding electrode.

FIG. 4 shows one specific embodiment of the present invention. This figure is a plan view of the vicinity of the bonding electrodes seen from above the chip, and is a realization of the input circuit shown in FIG. 1a. The pattern shown at 41 is a bonding electrode, a polycrystalline silicon resistor 42 runs under it, and a MIS transistor is connected via a contact 48 with a wiring electrode 43 as a gate and diffusion layers 44 and 46 as a drain and a source. Further, through a diffusion layer resistor 44, a gate control diode 45 whose gate is grounded is connected. 47 is a lead line to the internal transistor input gate. A cross section of the chip taken along line A-A' in the same figure is as shown in FIG. A MIS transistor having a drain and a source 53 as channel regions is arranged.

By using a deceptive configuration, it is possible to significantly reduce the area occupied on the chip by the input protection circuit of the MIS type semiconductor integrated circuit device, and what is more, only the input protection circuit is placed under the bonding electrode rather than the entire input protection circuit. Since only a resistor is used, the effect of preventing electrostatic damage is no different from the conventional one, and it is clear that the present invention has a great effect on electrostatic protection of the chip and reduction of the chip area. Therefore, it is possible to improve the yield of chips and further reduce manufacturing costs.

In the above embodiment, polycrystalline silicon is used as the input protection resistor, but other materials may be used. Further, although the case where the circuit shown in FIG. 1a is used as the input protection circuit is shown, other circuit configurations may be used. Furthermore, although not specifically indicated in the above description, the present invention can be applied to any of N-channel MIS integrated circuits, P-channel MIS integrated circuits, complementary MIS integrated circuits, or to semiconductor devices in which each of them is mixed. It can be applied even if Further, the application of the present invention is not limited to not only bulk type semiconductor devices but also thin film type semiconductor integrated circuit devices such as SOS, which shows the wide range of usefulness of the present invention.

[Brief explanation of drawings]

Figures 1a and b are diagrams of conventionally used input protection circuits, Figure 2 is a pattern diagram of a conventionally used input circuit, Figure 3 is a pattern diagram of an input circuit according to the present invention, and Figure 4. 5 is a plan view of an embodiment of the present invention, and FIG. 5 is a sectional view taken along line A-A' in FIG. 11... Bonding electrode, 12, 14...
Input protection resistor, 13...MIS transistor, 15
... Gate control diode, 16 ... Internal transistor, 17 ... Diffusion resistor and diode, 21, 31 ... Bonding electrode, 22,
32... Input protection circuit, 41... Bonding electrode, 42... Input protection resistor, 43... MIS transistor gate, 44... Diffusion layer, 45... Gate control diode region, 46... Grounding diffusion layer wiring , 47... Connection portion to internal transistor, 48... Contact, 51... Bonding electrode, 52... Input protection resistor, 53... MIS transistor region, 54... Diffusion layer, 55... Semiconductor substrate, 56 ...Field insulation film.

Claims (1)

[Claims] 1. a circuit element section formed inside the main surface of a semiconductor chip and having an insulated gate field effect transistor as an input section; a bonding electrode provided around the circuit element section of the semiconductor chip;
An input protection circuit is provided that is connected between the input section of the internal element section and the bonding electrode and has an input resistor made of polycrystalline silicon and a constant voltage element, and the polycrystalline silicon is connected to the input section of the internal element section and the bonding electrode. The bonding electrode is formed on the polycrystalline silicon via a second insulating film, and the constant voltage element is not covered with the bonding electrode and is connected to the input terminal. A semiconductor integrated circuit characterized by being connected to a portion of the semiconductor integrated circuit.