JPH0228267B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an integrated circuit device that includes a resistor and is required to operate at high frequency and at high speed.

(Prior art) Recent semiconductor devices are increasingly required to be highly integrated to reduce the number of parts and to increase speed to reduce power consumption. Since resistors having a junction capacitance are slow due to their junction capacitance, resistors made of polycrystalline silicon and having no junction are increasingly being used.

FIG. 1 shows a partial structural sectional view of a conventional device having a diffused resistor. In FIG. 1, 101 is a P type substrate, 102 is an N ⁺ type buried layer, 103 is an N type epitaxial layer, 104 is a P type insulating layer, and 105 is a P type substrate.
Type resistance region and base of NPN transistor, 1
Reference numeral 06 indicates the emitter and collector contacts of the NPN transistor, 107 indicates an insulating film, and 108 indicates an aluminum electrode. In such a structure, as described above, since the P-type impurity is diffused into the N-type epitaxial layer 103 to form the P-type resistance region 105, there is a junction capacitance, and the transistor operates at high speed. However, the problem arises that the resistor 105 limits the speed.

FIG. 2 shows an example in which polycrystalline silicon is used to improve this drawback. In FIG. 2, 201 is a P-type substrate, 202 is an N ⁺ type buried layer, 203 is an N-type epitaxial layer, 204 is a P-type separation layer, 205 is an insulating oxide film, 206 is a base region of an NPN transistor, 207 are the emitter and collector regions of the NPN transistor, 208 is a P-type or N-type resistor made of polycrystalline silicon, 209 is an insulating oxide film, 21
0 indicates an aluminum electrode, respectively.

In the case of such a structure, since the polycrystalline silicon resistor 208 is surrounded by the insulating films 205 and 209, it does not have a junction capacitance and has no voltage dependence, so it is excellent as a high-speed resistor. However, in this structure, the polycrystalline silicon body 208
After each region of the NPN transistor is formed, a step is created on the surface to form the resistor 208, for example by dry etching, resulting in a step break when it is desired to place an aluminum wiring over the resistor 208. Therefore, in order to smooth the side surfaces of the polycrystalline silicon 208, it is necessary to process the polycrystalline silicon 208 by applying phosphorus glass and performing high temperature treatment to smooth the surface. Moreover, due to this high temperature heat treatment, the element area of the previously formed NPN transistor changes and its characteristics fluctuate, resulting in a drawback that manufacturing conditions are limited. Furthermore, although it is desirable to form shallow junctions and achieve high speeds, NPN transistors have the disadvantage that heat treatment is added later, which makes the junctions deep and slows down the speeds.

(Object of the Invention) An object of the present invention is to provide a method of manufacturing a semiconductor device having a resistor that enables high-speed operation.

(Structure of the Invention) The present invention includes a step of forming a polycrystalline silicon resistor covered with a silicon oxide film on a silicon substrate, and forming an epitaxial layer on the exposed portion of the silicon substrate by a selective epitaxial growth method. , a process of growing the silicon oxide film on the surface of the polycrystalline silicon resistor to almost the same height as the surface, a process of forming an element region on the grown epitaxial layer, and a process of forming electrodes on the polycrystalline silicon resistor. It is characterized by comprising:

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

FIGS. 3a to 3f show an embodiment of the present invention in the order of manufacturing steps. That is, an N-type buried layer 302 with a layer resistance of about 10 to 30 Ω/□ is formed on a P-type silicon substrate 301 (FIG. 3a), and a silicon oxide film 303 with a thickness of 5000 Å to 10000 Å and polycrystalline silicon 30 is formed.
4 to about 5000 Å, and silicon oxide film 305 to 500 Å.
A silicon nitride film 306 having a thickness of about 1000 Å is sequentially formed (FIG. 3b). Next, the oxide film 305 and the silicon nitride film 306 of multiple parts to be used as resistors are
while leaving the oxide film 305 and the silicon oxide film 30 in other parts.
6 is removed and heat treated in an oxygen atmosphere to convert the polycrystalline silicon other than the resistor into an oxide film 307 (FIG. 3c). The remaining polycrystalline silicon 304,
After introducing impurities into 305 by thermal diffusion or ion implantation to convert it into the first conductivity type or the second conductivity type, the oxide films 303 and 30 on the N-type buried layer 302 are
7 is opened until it reaches the substrate by anisotropic dry etching to form an opening 308 (FIG. 3). Thereafter, epitaxial growth is performed under reduced pressure in an atmosphere containing hydrogen chloride gas to selectively grow an epitaxial layer 309 of about 1 Ω-cm in the opening 308 to the same height as the oxide film 307, and then an oxide film 310 is formed. (Figure 3 e). Before this epitaxial growth, a silicon oxide film or polycrystalline silicon may be grown and selectively epitaxially grown using anisotropic dry etching, leaving the silicon oxide film or polycrystalline silicon only on the side surfaces of the opening 308. Thereafter, a base region 31 is formed on the epitaxial layer 309 by a well-known method.
1. Emitter and collector contact region 31
2 is formed, a window for electrode extraction is opened in the oxide film 310, and an aluminum electrode 313 is attached to complete the process.

The semiconductor device of the present invention formed by the manufacturing method described above is a high-speed resistor that uses polycrystalline silicon 304 and 305 as a resistor and has no junction capacitance because it is surrounded by an insulating film. and meet the necessary conditions. Moreover, the resistor 304,3
05 is formed before epitaxial growth,
The heat treatment for forming the resistor does not affect the formation of the base and emitter of the transistor, and high-speed transistors can be manufactured independently. In addition, since epitaxial growth is selectively performed and the surfaces are made flat by matching their heights, there is no fear of breakage even when aluminum wiring is passed over the resistors 304 and 305. Furthermore, the insulation isolation between the devices is not by junction isolation but by an oxide film, which is advantageous for reducing capacitance and increasing speed. As described above, it can be said that the present invention is an extremely excellent device for flattening the surface and increasing speed, which are problems with conventional structures when forming large-scale integrated circuit devices.

In the embodiments of the present invention, the polycrystalline silicon resistor may be a mixture of the first conductivity type and the second conductivity type, or may be doped with impurities of the same conductivity type but different concentrations. The conductivity types of the substrate 301, buried layer 302, selective epitaxial layer 309, base region 311, emitter, and collector region 312 of the transistor may be reversed. In addition, the insulating oxide film 31
Of course, it is also possible to apply a silicon film on top of 0 and use it as a passivation film.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a conventional example of a device having a resistor. 101...P-type silicon substrate, 102...N ⁺
Type buried layer, 103...N type epitaxial layer, 1
04...P-type insulating separation layer, 105...P-type NPN
transistor base region and resistance region, 106
...N-type NPN transistor emitter, collector region, 107...insulating oxide film, 108...aluminum electrode, FIG. 2 is a sectional view showing another conventional example. 201...P-type silicon substrate, 202...N ⁺
Type buried layer, 203...N type epitaxial layer, 2
04... P-type insulating separation layer, 205... Insulating oxide film, 206... P-type NPN transistor base region, 207... N-type NPN transistor emitter and collector region, 208... Polycrystalline silicon resistor, 209... Insulating oxide film, 210...aluminum electrode. FIGS. 3a to 3f are cross-sectional views showing an embodiment of the present invention in the order of its manufacturing steps. 301...P-type silicon substrate, 302...N ⁺
Mold buried layer, 303... Insulating oxide film, 304... Polycrystalline silicon, 305... Insulating oxide film, 306...
...Sided film, 307... Insulating oxide film, 308...
Opening, 309... Selective epitaxial layer, 31
0... Insulating oxide film, 311... P-type NPN transistor base region, 312... N-type NPN transistor emitter, collector region, 313... Aluminum electrode.

Claims (1)

[Claims] 1. A step of covering the surface of a silicon substrate with a first silicon oxide film, and a step of forming a polycrystalline silicon resistor whose bottom surface is in contact with the first silicon oxide film and whose side surfaces and surface are covered with a second silicon oxide film. selectively removing the first and second silicon oxide films to expose a part of the surface of the silicon substrate; and forming an epitaxial layer on the exposed part by selective epitaxial growth. The second
a step of growing the second silicon oxide film to almost the same height as the surface of the second silicon oxide film, a step of forming an element region in the grown epitaxial layer, and forming a selective contact hole in the second silicon oxide film to form the polycrystalline silicon oxide film. 1. A method of manufacturing a semiconductor device, comprising the step of forming an electrode on a silicon resistor.