JPH02285708A - Flip-flop ic - Google Patents

Abstract

PURPOSE:To easily and efficiently compensate a minimum delay time of other circuit and an 10 or the like by retarding an output of a function section having a function of a FF by a different time and outputting the result externally from an output terminal. CONSTITUTION:A delay time of a scan circuit such as an FF circuit is calculated in the stage of design. When a delay time for one period is less than a minimum delay time required for the design, the minimum delay time compensation is required. In this case, an output terminal 109 is used to add the delay by an internal delay circuit 2 and the minimum delay time is compensated. On the other hand, when the delay for one period satisfies the minimum delay time, an output terminal 109 is used to compensate the minimum delay time without adding the delay by the delay circuit. Thus, when the output terminal 108 or 109 is used alternatively, the minimum delay time required for the design is compensated.

Description

Detailed Description of the Invention Technical Field The present invention relates to a flip-flop IC, and particularly to a flip-flop IC that can compensate for delay time between ICs.
Regarding.

BACKGROUND ART In general, when a logic circuit is constructed by cascading a plurality of IC chips, clock skew may occur. In such a case, it is necessary to compensate for the setup time before or after the flip-flop IC. In addition, there are cases where it is necessary to provide a delay time between ICs due to circuit design considerations.

For example, in a well-known flip-flop circuit with a scan function, there is only one scan-out output terminal, and the scan-out signal from this output terminal is delayed by an external delay time compensation buffer gate, a well-known delay line, etc. By compensating for the minimum delay time, it was done.

However, such conventional methods have major drawbacks in mounting, such as an increase in the number of external components, an increase in the number and length of wires, etc. Furthermore, when external components are used, there is a drawback that the efficiency is poor from the viewpoint of delay performance, and the cost is also high.

OBJECTS OF THE INVENTION An object of the present invention is to provide a flip-flop IC that can easily and efficiently compensate for the minimum delay time with other circuits, ICs, etc.

Structure of the Invention A flip-flop IC according to the present invention includes a functional section having the original function of a flip-flop, a plurality of delay means for delaying and transmitting the outputs of the functional sections by mutually different times, and a plurality of delay means from the plurality of delay means. The device is characterized in that it has a plurality of output terminals, each of which sends out the output to the outside, and these are integrated into one chip.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a flip-flop IC according to the present invention. In the figure, a flip-flop IC according to an embodiment of the present invention is constructed by integrating a flip-flop circuit 1 and a delay circuit 2 into one chip. Note that 101 is a clock signal input terminal, and 102 is a clock signal input terminal.
103 is an input data signal input terminal, 103 is a data set signal input terminal, 104 is a hold signal input terminal, 105 is a scan-in signal input terminal, 10B is a shift mode signal input terminal, 107 is a mask reset signal input terminal, 108
and 109 are output terminals.

Flip-flop circuit 1 is set and reset.

This is a general flip-flop circuit with a scan function that has hold and shift functions.

The delay circuit 2 receives the positive logic output signal of the flip-flop circuit 1, delays it by a predetermined time, and sends it out. This delay circuit 2 has the same function as a conventional external delay circuit, and is realized by a plurality of gates or delay lines.

In other words, in this embodiment, a delay circuit is provided in the tC chip, and the output terminal for sending the output of the flip-flop circuit to the outside via this delay circuit and the output of the flip-flop circuit as they are (delay time (approximately 0)) has an additional output terminal for sending out to the outside. Therefore, if it is necessary to compensate for the minimum delay time, the output of the delay circuit 2, that is, the output from the output terminal 109 may be used.

A method of using the flip-flop IC of this embodiment having such a configuration will be explained using FIG. 2. FIG. 2 is a flowchart showing the determination procedure when applying the flip-flop tC of FIG. 1.

At the design stage, the delay time of the scan path between the flip-flop circuits and the like is calculated (step 20).

At this time, if the delay time of one section is less than the minimum delay time required in the design, minimum delay time compensation is required (Steps 21->22). In this case, by using the output terminal 109, the delay caused by the internal delay circuit 2 is added, and the minimum delay time can be compensated (steps 22→24).

On the other hand, if the delay in one section satisfies the minimum delay time, by using the output terminal 10B, it is possible to compensate for the minimum delay time without adding the delay caused by the delay circuit. 21 → 23 → 24).

In other words, by selectively using the output terminal 108 or 109 as necessary, it is possible to compensate for the minimum delay time required in the design. Therefore, there is no need to provide an external delay gate or delay line, and the conventional problems such as an increase in the number of parts, an increase in the number of wires, and an increase in the length of the wires do not occur.

In this embodiment, the output of the flip-flop circuit is sent to one of the two output terminals as is, and the output is sent to the other through a delay circuit.
It is clear that delay circuits having different delay times may be provided for each output terminal.

Further, in this embodiment, the delay circuit is provided only on the output side, but instead, it may be provided only on the input side, or on both the input side and the output side, and there are many more types of delay circuits and their number. Output terminals may be provided according to the requirements.

Furthermore, in this embodiment, a case has been described in which the flip-flop circuit has a scan function, but any type of circuit including other flip-flop circuits may be used, and the present invention is not limited to this type.

Effects of the Invention As explained above, the present invention provides a flip-flop circuit, a delay circuit that delays its output by different times, and separate output terminals for sending out the delayed outputs in one chip. By using the output from one of these output terminals as needed, design problems such as an increase in the number of parts, the number of wires, and the length of the wires can be eliminated, and other circuits can be easily and efficiently connected. This has the effect of being able to compensate for the minimum delay time between the two.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the internal structure of a flip-flop IC according to an embodiment of the present invention, and FIG. 2 is a flowchart showing a determination procedure when the flip-flop IC of FIG. 1 is applied. Explanation of symbols of main parts 1...Flip-flop circuit 2...Delay circuits 108, 109...Output terminal

Claims (1)

[Claims] (1) A functional section having the original flip-flop function, a plurality of delay means for delaying and transmitting the outputs of the functional sections by mutually different times, and outputs from the plurality of delay means, respectively, are sent to the outside. A flip-flop IC characterized in that it has a plurality of output terminals and is integrated into one chip.