JPH0228765A - Instruction processing sequence control system - Google Patents

Abstract

PURPOSE:To determine an instruction to be inputted without conforming to designated instruction inputting sequence by providing a means to hold an instruction group to be inputted, the means to hold the state of a vector register, etc., and the means to determine the instruction to be inputted. CONSTITUTION:A program holding part 1 stores a program, and an instruction storing part 2 stores plural instructions 1 and 2 from the holding part 1 in order to wait the time of inputting. A vector operator part 5 consists of plural vector registers and one or more operators, and a main storage referring processing part 6 controls access to a main storage device. A state holding part 3 holds the states of the above-mentioned vector register, the operator and the main storage device being used by the instruction in the course of execution. An instruction processing sequence determining part 4 determines the instruction to be inputted to the operator part 5 and the processing part 6 on the basis of the instruction from the storing part 2 and the states of various kinds of resources from the holding part 3 and without conforming to the instruction inputting sequence designated by the program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction processing order control system in a vector computer that issues and executes instructions irrespective of the instruction execution order specified in a program.

[Conventional technology]

In order to speed up instruction processing, a system is used in a computer for search processing that dynamically determines the instruction processing order and inputs the instructions to the arithmetic unit and main memory processing unit regardless of the order specified in the program. The details are available from IBM at 196
Publications published in January 2017 r I BM Journal
l of Re5earch & Devel.

Rement J Vol. 11, No. 1, pages 8-24.

By W. Anderson et al.
IBM System 1360 Model 91:
Machine Ph1losophy and In
Structure-Handling J and Publication F published by IEEE in 1984
ilth Annual International
Symposium on ComputerJ, pages 110-118, S., Weiss et al.
by rlNsTRUcTION l5SUELOG
ICFORPIPELINED SUPERCOMPU
You can refer to the paper titled TER3J.

Computers that control the order of instruction processing detect collisions between instruction input/output operands and memory addresses, and also determine the usage status of arithmetic units and main memory processing units. It also has means for deciding whether to input an instruction to the main memory processing section. This method of inputting instructions in a computer is applicable not only to scalar computers but also to vector computers. However, in a vector computer, it is difficult to determine whether it is acceptable to input a plurality of memory reference vector instructions to the main memory processing unit in the reverse order of the order specified in the program. That is, base is the store start address of the vector store instruction specified to be executed in the program, distl is the distance between elements of the vector stored by the vector store instruction, and 1enl is the length of the vector stored by the vector store instruction. (1e
i1), base2 is the load start address of the vector load instruction specified in the program to be executed after the vector store instruction, and c]1st is the distance between elements of the vector loaded by the vector load instruction.
2. The vector load command] The length of the vector to be loaded now is Jen2 (len2≧
1) is the set of addresses stored by the vector store instruction (basel.

basel+distlX1. basel+distl
X2. −, base e 1+d i s t LX
(l enl-1)) and the set of addresses to be loaded by the vector load instruction (base2.ba
se20dist2X1. base2+dist2X2
Only when the set of intersections with ゜base2+dist2X (1en2-1)) is empty, it is determined that the vector rot instruction may perform a main memory reference prior to the vector store instruction. But any basel
, distl, 1enl (lenl≧1), base
2. It is difficult to make a decision on the combination of dist2, 1en2 (len2≧1) in a short time.

Therefore, as a case where it can be determined simply, the store start start address bas specified in the preceding vector store instruction
The area from el to baselXdistlX (lenl-1), which is the final store address of the vector store instruction, is an address set element (addl:basel
≦addl≦(baselXdistlX (lenl
-1))) and the load start address base2 specified by the subsequent vector load instruction to base20 (1) which is the final store address of the vector store instruction.
en2-]) Xdist2 is the address set element (add2: base2≦add2≦(base
A method has been proposed for determining address range overlap, in which if the intersection set with 2Xdist2X(len2-1))) is empty, it may be overtaken in terms of main memory references.

[Problem to be solved by the invention]

Although this method is relatively easy to implement, it is possible to accurately determine whether overtaking is possible using basel, distl, etc.
, 1enl (lenl≧1), base2, dist
The combination of 2, 1en2 (len2≧1) is also limited. In other words, the store start address of the vector store instruction specified to be executed by the program is set as base.
L The distance between elements of the vector stored by the vector store instruction is distl, the length of the vector stored by the vector store instruction is 1enl (lenl≧1), the address of the final vector element stored by the vector store instruction is 1astl, Base2 is the load start address of the vector load instruction that is specified in the program to be executed after the vector store instruction, and d is the distance between elements of the vector loaded by the vector load instruction.
1st2, the length of the vector loaded by the vector load instruction is 1 en2 (len2≧1), and the address of the final vector element loaded by the vector load instruction is 1as
In the case of t2, in the method of determining address range and overlap described above, basel, 1astl, base2, 1
Among the 24 possible order relationships of ast2 addresses, there are at most 8 ways (basel≦1astl≦base2≦1ast2)
(basel≦1astl≦Ba5t2≦base2)
(lastl≦basel≦base2≦1ast2)
(lastl≦basel≦1ast2≦base2)
(base2≦1ast2≦basel≦1astl)
(last2≦bast2≦basel≦1astl)
(base2≦1ast2≦1astl≦basel)
(last2≦base2≦1astl≦basel)
It has the disadvantage that it can only be correctly determined in the following cases.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks, and to improve the judgment that it is okay to overtake the order of instructions with respect to main memory references.
se2. It is an object of the present invention to provide an instruction processing order control system that can perform instruction processing for a combination of dist2 and 1en2 in a short time.

[Means to solve the problem]

A system according to one aspect of the present invention includes a first means for holding a group of instructions to be input to a vector arithmetic unit and a main memory processing unit, a vector register used by an instruction being executed, an arithmetic unit, and a main memory. A second means for holding the state of the device 0, and inputting an instruction specified by the program based on the state of various resources held by the second means from a group of instructions held by the first means. A third means for determining instructions to be input to the vector arithmetic unit and the main memory processing unit without regard to order; the vector store instruction in the instruction group held by the first means; Regarding the vector load instruction in the instruction group held by the first means specified in the program to input the instruction later,
The distance between vector elements specified by the vector store instruction is equal to the distance between vector elements specified by the vector load instruction, and the store start address specified by the vector store instruction and the vector The load start start address specified in the load instruction specified in the load instruction is not equal, and the store start start address specified in the vector store instruction and the load specified in the load instruction specified in the vector load instruction are If the magnitude of the difference in starting point addresses is smaller than the magnitude of the distance between vector elements specified by the vector load instruction, the vector load instruction is preceded by the vector store instruction and the vector arithmetic unit and main memory processing unit It consists of a means for inputting into the system.

〔Example〕

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a program storage unit 1.1 that stores programs. An instruction storage section 2 that stores a plurality of instructions 1 and 2 from the program holding section 1 for waiting for input. Vector arithmetic unit section 5 consisting of a plurality of vector registers and one or more arithmetic units. Main memory reference processing unit 6 that controls access to the main memory. a state holding unit 3 that holds the states of the vector register, arithmetic unit, and main storage device used by the instruction being executed; Based on the instructions from the instruction storage section 2 and the status of various resources from the state holding section 3, the instructions are input to the vector arithmetic unit 5 and the main memory reference processing section 6 regardless of the instruction input order specified by the program. It includes an instruction processing order determining unit 4 that determines instructions.

The instruction storage unit 2 stores subsequent instructions in the order specified by the program whenever a space becomes available.

The instruction storage unit 2 holds, for example, two instructions, "instruction 1" and "instruction 2". 2"
It is kept in such a way as to keep it in place.

The instruction processing order determining unit 4 includes a main memory reference logic contention checking unit 9. It includes a register reference logic conflict check section 8 and an instruction input determination section 7.

Referring to FIG. 2, the main memory reference logic conflict check unit 9 checks the vector access start address (b) of instruction 1.
asel) and the address of the vector access start point of instruction 2 (ba se 2).
and a register 23 that stores the inter-element distance (distl) to be accessed by the vector of instruction 1.
and the distance between elements to be accessed by the vector of instruction 2 (d i
s t 2) and a subtraction circuit 2
5, an absolute value circuit 26, an absolute value circuit 27, an absolute value circuit 28, a comparator 29 that determines whether an inequality relationship holds true, and a comparator 29 that determines whether a greater-than relationship holds true. 30, a comparator 31 that determines whether an equivalence relationship holds, and an input logical product 32.

Referring to FIG. 7, the register reference logic conflict check unit 8 compares the write register number 71 of instruction 1, which is the preceding instruction, and the write register number 74 of instruction 2, which is the subsequent instruction, and when they do not match, a signal is sent. a comparison circuit 77 that outputs a signal, and a comparison circuit 78 that compares the write register number 71 of instruction 1, which is the preceding instruction, with the second read register number 76 of instruction 2, which is the subsequent instruction, and outputs a signal when they do not match. Write register number 71 of instruction l which is the preceding instruction and instruction 2 which is the succeeding instruction
and the first read register number 75, and outputs a signal when there is a mismatch. A comparison circuit 80 that compares the first read register number 72 of instruction 1, which is the preceding instruction, and the write register number 74 of instruction 2, which is the subsequent instruction. Comparison circuit 81 for comparing the second read register number 73 of instruction L'14X-1, which is the preceding instruction, and the write register number 74 of instruction 2, which is the subsequent instruction.
And these comparison circuits? ? -81 includes an AND gate 82 which ANDs the outputs from -81.

In order to be able to "overtake commands", there are basically the following three things.
All conditions must be met.

First, a subsequent instruction must not read the contents of a register that stores the execution result of a preceding instruction.

Second, the subsequent instruction must not perform a write operation on the register that is the read target of the preceding instruction.

Third, the write registers of the preceding and succeeding instructions must not be the same register.

The resistor reference logic conflict check unit 8 shown in FIG. 7 is an example of a circuit that shows these three conditions, and the AND gate 8
If the output of 2 is logic ``0'''', it indicates overtaking is prohibited, and ``1''
” indicates that overtaking is possible.

The configuration of the check section 8 makes it possible to eliminate the second condition by copying the contents of the read register of the preceding instruction in advance. That is, prior to overtaking execution of the subsequent instruction, the contents of the register read by the preceding instruction are buffer-linked. In this case, even if the succeeding instruction writes to the register that the preceding instruction was supposed to read, the value that has been buffered in advance can be used as the value of the reading register of the preceding instruction. can be executed correctly.

Next, the instruction input determining unit γ will be explained in detail.

Referring to FIG. 8, an instruction input permission signal generation circuit, which is one of the main parts of the instruction input determining section 7, is configured for each of the preceding instruction and the subsequent instruction.

Each circuit includes a decoder 83 for decoding the instruction code and a decoder 84 for decoding the write register number. Decoder 85 for decoding the first read register number. Decoder 86 for decoding the second read register number These decodes 83-86
A group of AND gates 87-101 and these AND gate groups 871 and 87-101 which take a logical product of the decoding result and a status signal indicating whether or not the status is busy via the line 14 from the status holding unit 3 in FIG.
01 (OR game) 102.

This instruction input permission signal generation circuit is a circuit that determines whether or not one instruction can be input (executed). A signal indicating whether or not the state is busy is transmitted from the state holding unit 3 via the line 14 to the main memory access path.

Only for adder 2 multiplier and registers (VRO to VR3). However, the type of this signal is not limited to this, and depends on the configurations of the vector arithmetic unit 5 and the main memory reference processing unit 6. Here, for convenience of explanation, the minimum required check signal is shown.

The decoder 83 generates output signals as shown in Table 1 below in accordance with the value of the instruction code.

Table 1 Also, decoders 84-86 generate output signals shown in Table 2 in accordance with the values of the register numbers.

Table 2 Next, the operation will be explained using the program example shown in FIG.

Referring to FIG. 4, rVLOADJ is a vector load instruction code, "■ADD" is a vector addition instruction code, rVsTOREJ is a vector store instruction code,
rVMULTj indicates a vector multiplication instruction code. Further, rVROJ to rVR3J indicate vector registers of instruction operands, and each vector register can store 256 vector elements. (a
, b.

The instruction operands shown in the triplet in C) indicate the main memory operand lands of the vector code/store instruction, and a is the starting point address for vector access ← (b a s
e, 5,256) J indicates an instruction to load a vector element with base as the starting address of the memory, distance between vector elements of 5, and vector length of 256 into the vector register VRO.

Next, the order in which the program shown in FIG. 4 refers to the main memory will be explained using FIG. 5. Figure 5A is 1 of Figure 4.
It shows the memory address referenced by the second instruction and the second main memory access instruction.

Both the first and second instructions are vector loads,
And since there is no vector register contention, in this case,
They are executed in the order given in the program. next,
When the first and second instructions start execution, the third vector addition instruction adds vector register vO and ■1
The execution result of the addition instruction is written to the main memory.
The th vector store instruction cannot be executed until the operation result of the addition instruction starts to be written to the VRO. On the other hand, as shown in Figure 5B, the fifth vector load instruction does not load the result stored by the fourth vector store instruction, so it starts execution before the fourth vector store instruction. is possible.

The present invention determines whether it is okay for the fifth vector load instruction to overtake this fourth vector store instruction in terms of main memory reference. The distances between the vector elements of the vector load instructions are the same (both are 151), and the store start point address (base) of the fourth vector store instruction and the load start point of the fifth vector load instruction are the same. Address (base)
(12) are not equal, and the size of the difference between the store start point address of the vector store instruction and the load start point address of the vector load instruction is (lbasel+2-b
Asel l, that is, 2) is smaller than the inter-element distance of the fourth vector store instruction (15, that is, 5), so it can be determined that overtaking is possible.

Based on this, the instruction input determining section 7 will be explained in detail.

The following will explain the actual instructions.

・VLOAD VRO←(base, dist, 1e
n) The instruction code is VLOAD, and if the main memory access path is currently BUSY, the instruction cannot be input. Also, the write register number is 9VRO, and the current VRO
If it is read and BUSY, this command cannot be input.

・VSTORE VRI-+ (base e, d
i st, 1 en) The instruction code is VSTORE, and if the main memory access path is currently BUSY, the instruction cannot be input. Also, the read register number is V
RI, and if VRI is currently write BUSY, this command cannot be input.

・VMULT VB2 ←VRO, VRI The instruction code is VMULT, and if the multiplier is currently BUSY, the instruction cannot be input.

Further, the write register number is VB2, and if VR2 is currently read BUSY, this instruction cannot be input. Furthermore, the read registers are VRO and VRI, and this command cannot be input even if which register is currently busy for writing.

In contrast to the above three examples, the generation circuit shown in Figure 8 is a circuit for checking whether an instruction currently being executed is already using the hardware resources that are to be used by the instruction that is about to be input. It is.

Referring to FIG. 1, the final judgment of the instruction input unit 7 is as follows.
Provided corresponding to the judgment result of the main memory reference logic conflict check unit 9 given via the line 16, the judgment result of the register reference logic conflict check unit 8 given via the line 15, and the preceding/successful instructions. This is done by integrating the determination results of the generation circuit shown in FIG.

These relationships are shown in Table 3.

Σ22- Next, before explaining the operation of an embodiment of the present invention, the relationship between the instruction execution state and various busy signals will be explained in detail with reference to FIGS. 9 and 10.

First, the execution state of an instruction will be explained.

Referring to FIG. 9, VLOAD, VADD.

The execution states of instructions such as VMU L T and VSTORE are shown by parallelograms. The meaning of this figure will be explained using FIG.

In vector operations, main memory references/operations are processed in a pipeline manner. Therefore, the first vector
Elements, second elements, third elements, etc. are processed simultaneously in a pipeline manner.

The oblique side of the parallelogram indicates the time course of processing for each element. The horizontal sides of the parallelogram indicate that new elements of the vector are processed in sequence.

Taking a vector load as an example, the processing for each vector element will be described as address generation, main memory access, and storage of read data in a vector register.

Processing for each vector element is performed by vector operation (VADD).
, VMULT) is an example of reading from a vector register, calculation, and storing the calculation result in the vector register.

Next, state changes of various busy signals will be explained.

Referring to FIG. 9, the busy signal indicated by a solid line indicates the on state of the busy signal. The number on the busy signal indicates which instruction among the instructions being executed is causing the busy state.

As an example, the first instruction ffLOAD VRO←(b
ase, 5,256)) will be explained.

When this instruction is taken out of the execution queue and actual execution begins, writing to the main memory access path and VRO becomes busy. The timing at which the busy state is released differs depending on whether the main memory access path is busy or when the VRO write is busy.

For the main memory access path, subsequent VLOAD/V
This is until immediately before the STORE instruction becomes able to use the main memory access path, and regarding the VRO register write busy, it is until immediately before the subsequent instruction that attempts to read the VRO becomes actually readable.

The type of this busy signal and the setting of the timing at which the busy signal is released differs depending on the configuration of the vector arithmetic unit section and main memory processing section, but in this embodiment, reading from each vector register is performed in response to a read request from multiple instructions. It is assumed that simultaneous processing is possible.

Next, the operation of one embodiment of the present invention will be explained in detail using the program example shown in FIG. 4 with reference to FIGS. 1, 2, 6, and 9.

Referring to FIG. 1, FIG. 2, FIG. 6, and FIG. 9, first, the state of the execution waiting queue 2 in the initial state (time t in FIG. A vector load instruction with two flavors of the program is set as the vector load instruction and instruction 2 (state in FIG. 6(a)).
. The register reference logic conflict check unit 8 checks whether the preceding instruction 1 in the program does not read or refer to the write register, and the following instruction 2 does not read or refer to the register, and instruction 1 does not read or refer to the register to which instruction 2 writes or refers. Therefore, the command input determining unit 7 is notified that overtaking is possible. The main memory reference logic conflict check unit 9 follows the circuit shown in FIG.
Main memory reference start address base2 of el and instruction 2
are not equal, and the magnitude of the distance between vector reference elements of instruction 1 is not equal to the magnitude of the distance between main memory reference elements of instruction 2, and the main memory reference start address basel of instruction 1 is Memory reference start address ba
Since the magnitude of the difference in se2 is smaller than the magnitude of the vector reference element distance of instruction 1, the instruction input determining unit 7 is notified that overtaking is possible.

The instruction input determining unit 7 determines, based on the signal from the state holding unit 3, that instruction 1 does not conflict with the registers, arithmetic units, and main memory processing unit used by the instruction being executed, and that instruction 2 also does not conflict. . Therefore, it is determined that both instruction 1 and instruction 2 can be input, and that there is no logical order relationship between instruction 1 and instruction 2, so the vector load instruction, which is the second instruction of instruction 1, is input. (Figure 9 time 1+).

Next, the state of execution queue 2 in the next state is the second vector load instruction of the program as instruction 1, instruction 2
The third vector addition instruction of the program is set as . (The state shown in FIG. 6(b)). The register reference logic conflict check unit 8 notifies the instruction input determining unit 7 that it is impossible to overtake the register because the subsequent instruction 2 in the program reads and references the register written by the preceding instruction 1 in the program. The main memory reference logic conflict check unit 9 does not make a determination because the instruction 3 does not refer to the main memory. The instruction input determining unit 7 determines that the overtaking between instructions 1 and 2 is not allowed due to the signal from the register logic conflict check unit 8, so the main memory reference processing unit 6 determines whether the next instruction will be executed according to the signal from the state holding unit 3. instruction 102 at the timing when it becomes possible to process
Inputs the vector load instruction, which is the 9th instruction.
Time t2 in the figure).

Next, the state of the execution queue 2 in the next state is such that the third vector addition instruction of the program is set as instruction 1, and the fourth vector store instruction of the program is set as instruction 2 (see FIG. 6(C)). situation). The register reference logic conflict check unit 8 notifies the instruction input determining unit 7 that it is impossible to overtake the register because the subsequent instruction 2 reads and references the register written by the preceding instruction 1 in the program. The main memory reference logic conflict check unit 9 does not make a determination because instruction 1 does not refer to the main memory. The instruction input determining unit 7 does not allow overtaking between instructions 1 and 2 due to the signal from the register logical conflict check unit 8, so the vector registers VRO and VRI can be read using the signal from the state holding unit 3. Input the vector addition instruction, which is the third instruction of instruction 1, in the timer that becomes (
Time t3 in FIG. 9).

Next, the state of execution queue 2 in the next state is the fourth vector store instruction of the program as instruction 1, instruction 2
The fifth vector load instruction of the program is set as (the state shown in FIG. 6(d)). The logic conflict check unit 8 for register references is a register written by the preceding instruction 1 in the program, but the subsequent instruction 2 in the program does not read and refer to it, and instruction 1 reads and does not refer to the register to which instruction 2 writes and refers to it. Therefore, the command input determining unit 7 is notified that overtaking is possible. The main memory reference logic conflict check unit 9 follows the circuit shown in FIG. The size of the distance between reference elements and the size of the distance between main memory reference elements of instruction 2 are not equal, and the main memory reference start point address basel of instruction 1 and the main memory reference start point address base2 of instruction 2 are different from each other. Since the magnitude of the difference is smaller than the magnitude of the distance between the vector reference elements □ of instruction 1, the command input determining unit 7 is notified that overtaking is possible. The vector store instruction 1 cannot be input until the processing result of the third vector addition instruction input in the previous state starts to be written to the vector register VRO, and instruction 2 can overtake instruction 1. Instruction 2-5
Input the th vector load instruction (time t in Figure 9).
4).

Next, the state of execution queue 2 in the next state is the fourth vector store instruction of the program as instruction 1, instruction 2
The sixth vector load instruction of the program is set as (the state shown in FIG. 6(e)). At this point, it is assumed that the operation result of the third vector addition instruction executed earlier has started to be written to the vector register VRO.

The register reference logic conflict check unit 8 checks that the register written by the preceding instruction 1 in the program is not read or referenced by the subsequent instruction 2 in the program, and the register that is written and referenced by instruction 2 is read by instruction 1 and not referenced. Therefore, the command input determining unit 7 is notified that overtaking is possible. The main memory reference logic conflict check unit 9 follows the circuit shown in FIG.
Main memory reference start address base of e 1 and instruction 2
2 are not equal, and the magnitude of the distance between vector reference elements of instruction 1 and the magnitude of the distance between vector reference elements of instruction 2 are not equal, and the main memory reference start address basel of instruction 1 and the distance between vector reference elements of instruction 2 are Main memory reference start address b
Since the difference and magnitude of ase2 are smaller than the magnitude of the vector reference element distance of instruction 1, the instruction input determining unit 7 is notified that overtaking is possible. The instruction input determining unit 7 uses a signal from the state holding unit 3 to determine that instruction 1 does not conflict with the registers, arithmetic units, and main memory processing unit used by the instruction being executed, and that instruction 2 also does not conflict. judge. Therefore, it is determined that both instruction 1 and instruction 2 can be input, and there is no logical order relationship between instruction 1 and instruction 2, so the vector store instruction, which is the fourth instruction of instruction 1, is input ( time t5 in FIG. 9).

After that, the status of execution standby queue 2 is changed to 6th through the same procedure.
The state changes from Figure (f) to Figure 6 (g).

As explained above, this embodiment determines the logical overtaking possibility of two vector main memory reference relationships that are in a diagonal relationship, but the number of entries in the instruction waiting queue 2 is set to 3 or more. It is also possible to do so. Furthermore, in this embodiment, an example of operation in which a vector load instruction overtakes a vector store instruction has been shown, but between vector store instructions, between vector load instructions, and when a vector load instruction is
It can also be applied when a store command overtakes.

In addition, in the main memory reference logic conflict check unit 9, from the store start starting point address basel specified in the preceding vector store instruction to the final store address baseIXdistlX (le
nl-1) as the address set element (add
l: base1≦addl≧(base IXd
i s t LX (1en 1-1))) and the load start point address base2 specified by the subsequent vector 4-F instruction to base2 1en2-1) Xdist, which is the final store address of the vector load instruction.
2 to 2 as address set elements (add2: ba
se2≦add2≧(base2Xdist2X(le
By installing a circuit that determines that if the set of intersections with n2-1))) is empty, it is OK to overtake the main memory reference, it is possible to determine both the fast relationship and the duplicate relationship of addresses. It is also possible to do this.

Another example of the logical conflict check section 9 for main memory reference when determining address duplication will be described in detail with reference to FIG.

Referring to FIG. 3, another example of the main memory reference logic conflict check unit 9 includes a register 33 that stores the starting point address (basel) for vector access of instruction 1, and a vector length (basel) for vector access of instruction 1. lenl), a register 35 that stores the inter-element distance (distl) to be accessed by the vector of instruction 1, and a register 35 to store the distance between elements (distl) to be accessed by the vector of instruction 2;
a s e 2) and a register 36 that stores the instruction 2).
A register 37 stores the vector length (len2) to be accessed by the vector of instruction 2, and a register 3 stores the inter-element distance (d i s t 2) to be accessed by the vector of instruction 2.
8, adder 39, multiplier 4°, adder 41, adder 42, multiplier 43, adder 44, 2×2 switching circuit 45, registers 46 to 49, A comparator 50 that determines whether the less-than relationship holds true, a comparator 51 that determines whether the less-than relationship holds true, and a comparator 52 that determines whether the greater-than relationship holds true.
A comparator 53 that determines whether a less-than relationship is established, an OR circuit 54, an AND circuit 55, and an OR circuit 5
6, a hashite relationship determination circuit 57, and an OR circuit 58
It consists of

The hashite relation determination circuit 57 is the same as the circuit shown in FIG. In addition, the 2×2 switching circuit 45 has the distance between elements to be accessed by the vector of instruction 1 (d i s t
When the sign part of the register 35 that stores instruction 1) indicates a negative number, it is connected to a cross state, and when the sign part of the register 35 that stores the distance (distl) between elements to be accessed by the vector of instruction 1 indicates a positive number, it crosses. Connect to no state.

In the present invention, addresses on main memory referenced by a vector store instruction and a vector load instruction that follows the vector store instruction and the vector load instruction that follow the vector load instruction in the program are far away from each other. and the start address accessed by the vector store instruction and the vector load instruction are not separated by more than the distance between vector elements of the vector store, whether overtaking is possible in terms of main memory reference. It has the effect of correctly determining the

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention; FIGS. 2 and 3 are diagrams showing an example of the main memory reference logic contention check section 9 of FIG. 1; FIG. 4 is a diagram showing a detailed example of the present invention. Figures showing example programs for explanation; Figures 5A and 5B are diagrams showing main memory references for vector load/store instructions; Figures 6A to 6G are instructions in the instruction storage section 2 of Figure 1; A diagram showing the storage state; FIG. 7 is a diagram showing the detailed configuration of the register reference logic conflict check unit 8; FIG. 8 is a diagram showing the detailed configuration of a part of the instruction input determining unit 7; FIG. 10 is a diagram showing the execution state of an instruction and the states of various busy signals that change as the instruction is executed; and FIG. 10 is a diagram showing the execution state of the instruction. In the figure, 1...program holding unit, 2...
...Instruction storage section, 3...State holding section, 4.
...Instruction processing order determining unit, 5...Vector arithmetic unit, 6...Main memory reference processing unit, 7...
. . . Instruction input determination section, 8 . . . Register reference logic conflict check section, 9 . . . Main memory reference logic conflict check section. Agent Patent Attorney Susumu Hara Uchihara 4 Protect your heart 25 every day

Claims (2)

[Claims] (1) A vector arithmetic unit composed of one or more pipelined arithmetic units, a plurality of vector registers, and a network connecting the arithmetic units and the vector registers;
In a vector processing device equipped with a main memory processing unit that performs load/store in units of vectors to and from the vector register of the main memory, and the vector registers used by the executing instruction,
a second means for holding the state of the arithmetic unit and the main memory; and a second means for holding the state of the arithmetic unit and the main memory; The third controller determines the instructions to be input to the vector arithmetic unit and the main memory processing unit regardless of the instruction input order.
The third means includes a vector store instruction in the instruction group held by the first means and a vector store instruction specified by the program to be input after the vector store instruction. Regarding the vector load instruction in the instruction group held by the first means, the magnitude of the distance between vector elements specified by the vector store instruction is equal to the magnitude of the distance between vector elements specified by the vector load instruction. ,
and the store start point address specified by the vector store instruction and the load start point address specified by the load instruction specified by the vector load instruction are not equal, and the store start point address specified by the vector store instruction If the difference between the address and the load start point address specified by the load instruction specified by the vector load instruction is smaller than the distance between vector elements specified by the vector load instruction, the vector load instruction An instruction processing order control system comprising means for inputting the vector store instruction to a vector arithmetic unit and a main memory processing unit in advance of the vector store instruction. (2) a vector arithmetic unit composed of one or more pipelined arithmetic units, a plurality of vector registers, and a network connecting the arithmetic units and the vector registers;
In a vector processing device equipped with a main memory processing unit that performs loads/stores in units of vectors between the main memory and the vector register, and the vector registers used by the executing instruction,
a second means for holding the state of the arithmetic unit and the main memory; The third controller determines the instructions to be input to the vector arithmetic unit and the main memory processing unit regardless of the order in which the instructions are input.
The third means includes a vector store instruction in the instruction group held by the first means and a vector store instruction specified by the program to be input after the vector store instruction. With respect to a vector load instruction in the instruction group held by the first means, a continuous address interval from a store start address stored by the vector store instruction to a final store address stored by the vector store instruction; Even if the continuous address range from the load start address loaded by the vector load instruction to the final load address loaded by the vector load instruction does not intersect, the vector load instruction is preceded by the vector store instruction. 2. The instruction processing order control system according to claim 1, further comprising means for inputting the data to the vector arithmetic unit and the main memory processing unit.