JPH02287855A - Bus size converting device - Google Patents

Abstract

PURPOSE:To attain the conversion between 16 bits and 8 bits by outputting the signals for control of the 1st and 2nd bidirectional buffers, a data latch, and an address buffer and at the same time outputting the lowest rank bit of an address to the address buffer. CONSTITUTION:The 16-bit data is divided into the higher rank 8-bit data and the lower rank 8-bit data in a writing operation state where the 16-bit data is sent to the outside from a CPU 1. Then the higher and lower rank data are sent to an 8-bit bus via the bidirectional buffers 3 and 4. While the lower rank byte data is latched by a data latch 5 in a reading operation state where the 16-bit data is sent to the CPU 1 from the outside. Then the higher rank byte data is outputted to a data bus of the CPU 1 in the timing coincident with the higher rank byte data. A control circuit 16 detects the access state of the CPU 1 and produces a control signal, and the bus size converting operation is controlled with the output signal of the circuit 16. Thus a 16-bit CPU can have accesses to a device, a memory, etc., corresponding to an external 8-bit CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus size conversion device installed between a 16-bit l-Ci)U and an external 8-bit lotus.

[Summary of the Invention] The present invention provides a bus size conversion device installed between a 16-channel data bus and an address bus and an external 8-channel bus and an address bus. 16 hiso[-(word) data is divided into upper and lower 8-bit (byte) data, and a first bidirectional buffer and a second bidirectional buffer are provided between these byte data and an external 8-bit data bus. A buffer is provided, and the lower byte data of the external data is latched into the data latch, and the timing is matched with the upper hide data and sent to C1) U, and these first and second bidirectional buffers, Outputs signals that control the data latch and address buffer, and also outputs signals to control the address buffer.
A control circuit is provided to output the least significant bit of the address, and this control circuit allows conversion between 16 bits and 8 bits, and also prevents byte addresses from becoming discontinuous.

[Conventional technology]

In electronic devices such as digital VTRs, 8-bit CPUs have usually been used as control CPUs. but,
Recently, 16-bit CPUs are being introduced in terms of processing power and processing of digital audio signals. As a result of this process, the peripheral devices of the CPU are 8hi, 1.
CI) Most of them have 11i=, for tJ,
When using J, a device is required to convert the bus 4 noise from a 16-bit bus to an 8-bit bus to which peripheral devices are connected.

[Problem to be Solved by the Invention] In order to cope with the difference in bus size, conventionally, the upper hide data of the 16-bit data was discarded and only the lower byte data was used.

This method has the problem that the addresses are discontinuous, the address space is reduced to 2, and the processing performance is also reduced. If the addresses are discontinuous, the number of software steps increases, the burden on the software increases, and as a result, processing performance decreases.

Therefore, an object of the present invention is to provide a bus size conversion device that can connect a 16-bit CPU and an 8-bit external high speed or memory high speed while maintaining address continuity.

[Means for Solving the Problems] In the present invention, in a bus size conversion device provided between a 16-bit CPU data bus and address bus and an external 8-bit data bus 6 and address bus 14, The first bidirectional buffer 3 is provided between the lower 8 bits of CPUI data bus 2 and an external 8-bit data bus 6, and the upper 8 bits of CPUI data bus 2 and an external 8-bit data bus 6 A second bidirectional buffer 4 is provided between the lower 8 bits of the CPUI and an external 8-bit data bus 6.
A data latch 5 that sends data to the data bus 2 of P U 1, an address buffer 13 provided between the address bus 12 of the CPUI and an external 8-bit address bus 14, and a data latch 5 that sends data to the data bus 2 of the P U 1; The signal BHE* indicating that the address is to be used, the least significant bit AO of the address, the read pulse R[], and the write pulse WR are input manually, and the first and second bidirectional buffers 34, data latch 5, and address buffer 13 are Control signals Jl, J2. ．． 13
．． ．． 14, and a plagiarism 1 circuit 16 that outputs the lowest address I-210 to the address buffer 13.

(Operation) During a write operation in which 16-bit data is sent from Cf'tJ1 to the outside, this 16-bit data is divided into 1st and lower 8-bit data (bye 1-).

These byte data are sent via bidirectional buffers 3 and 4 to an external 8-bit path. Also, during read operation to send 16-bit data from outside to CPLJI,
The lower hide data is latched into data latch 5, and the CPIJ l is synchronized with the upper byte data.
output to the data bus. Detection of the access state of the CPUI, generation of control signals, etc. are performed by the control circuit 16, and the above-described bus size conversion operation is controlled by the output signal of the control circuit 16.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of this embodiment, where ■ is 16
Bit l-CPU is shown. A bidirectional 16-bit bus 2 is connected to the CPUI. The bus 2 is a time-division bus, and a 16-bit address is output in the first half of a bus cycle (four clock cycles T1-14), and 16-bit data is output in the second half. A bidirectional buffer 3 for the lower 8 bits of 16-bit data, a bidirectional buffer 4 for the upper 8 bits, and a unidirectional data latch 5 are connected to the lotus 2. An external 8-bit data bus 6 is connected to these buffers 3, 4 and data latch 5.

Address latch 7 is connected to lotus 2, and C1) V
The lower 16-bit address is taken into the address latch 7 by the address strobe signal A S 'r B from No. 1. Further, the upper 4 bits of the address are outputted from CP tJ l to the address bus 8 , and this address is supplied to the address decoder 9 . 16 histo address bus 10 from address latch 7 is upper 8
It is divided into the address bus 12 and C for the lower 8 bits. The 7 bits excluding the lowest pitch hAo from the lower 8 bit address bus 12 or the external 8 bit address bus 1 via the address buffer 13
Connected to 4. Although not shown, other devices such as CP jl or memory are connected to the external data bus 5 and the address bus 14.

The upper 8 bits of the address via the address bus 11 are supplied to the address decoder 9. Address decoder 9
is the chip select signal C3* (
* means low actif. The same applies below. )
generate. The chip select signal C8* or L' is applied to the frame where the external lotus is selected. This chimbu select 1-
(r'+MC8*) is supplied to the control circuit 1 C3 provided for Hass-Rice conversion, and is inverted and manually inputted to the shift register 15.

The shift register 15 receives the clock C from the CPU 1.
1, , K* are supplied, and the output signal Q13 . Ql), QI-,,QF, Q)]
is supplied to the control 11 circuit 16. Timing chart G shown in FIG. 2; (, c l) Clock C of Ll 1
L K *, address strike l: I-f signal, A S
The relationship between i' B * and the chip select signal is shown. The output signal of this shift register 15 defines the timing of the operation of the control circuit 16.

Plagiarism 1 circuit 10 is P1. , A, and outputs a read pulse IgF) from CI'U1 to a control wholesale circuit 1fi, a write pulse W+<, and a signal Bt-]
1 * is input, and ○ is manually entered from -/l・Reshas 12 to the highest position of the address. CI) [
The read pulses 1-19 of Jl are also supplied to bidirectional bus buffers 3 and 4. The signal B HE * is one of the HASCON l-+:+-le signals (Bus lIig
h IEnable) belief υ. This signal BHE* converts the upper eight addresses 1 to 1 of the hash cycle.
This is an active low signal indicating that it is used in F2 to 'F4.

Control ■Ready signal R from circuit 16 to CPU 1
DY* is output. In addition, the plagiarism] circuit 16 sends the address buffer 13 the most significant bit Ao of the address.
Instead, it outputs a pseudo lowest level l-Z 10 (“H” at odd addresses, 1-7 at even addresses), and outputs read signals RIi A +, ) * and write signals WR do I to the outside. ' E *.Furthermore, the control circuit 16
a control signal J1 for controlling the bidirectional buffer 3 from the control signal J1, and a control signal J2 for controlling the bidirectional buffer 4;
Control signal J3 for controlling day clutch 5. J4 is output.

The accesses of the CPU 1 are basically word data even address access WORI), hide data odd address access OI:)D, and high[・data even address access lj V r! , N. Word access to odd addresses is achieved by sequentially performing byte accesses to odd addresses and byte accesses to even addresses.

When converting this 16-bit data into 8-bit data, first divide the 16-bit data into upper and lower 8-bit data, and convert these 8-bit data into control circuit 16.
The connection is switched to the 8-bit data bus 6 by a control signal from the 8-bit data bus 6.

In the control circuit 16, as described below, the access state and the like are detected from the above-mentioned input signal, and based on this detection, a read signal η, a write signal, and a control signal are generated.

Detection of access state (ACCESS) A O = O, B HE * = O, CS * = 0
At the time, WORD AO=1, BHE*-0, CS*=
When 0, 0DD AO=0. BHE*=1. When C3*=0, EV E N read or write (RD W R) detection RD=O, W
R=1. cs*=.

When , read (R1) 1) RD=1. WR=0. When C3*=0, write (WR+) Chip select even/odd detection (C3EO) C8*-0,
When QE=1, one (Ol) ■C3*=O, QE=O
(7) When l<, V EN 1 The output of the control circuit 16 is formed by the following logic based on the above detection. However, -1 means the case, and & is the logical product. , # means logical sum, * means negative logic, and : indicates the end of the logical expression.

READ*-((ACCESS=-WORf))&
(((RDWR=-RD1) &QF')
#'((RDWR==RD 1)&QD*)))#(
*(ACCESS=-WORI)) & (RDWR==
R1)1))i WRITE*= ((ACC TO) SS = =WOR
I))&(((R,DWR==WR1)&QF)#
((RDWR==WRlJ&QI)*)))# (*
(ACCESS--WORD) & (RDWR==
WR1)') ;J2*= (ACCESS-=OD
D) #((ACCESS-=WORD) & (C3EO
-=ODD1)) ; J 1 *= ((ACCESS--WORD) &(
C3EO==EVENl))#(ACCESS--EV
EN) J 4 *= ((ACCESS--WORD) &
(C8lmi0--ODD1))& (RDWR=
=RD1); J3*-((RDWR-=RD1)&QD*)
&(ACCESS==WORD); RDY*= (ACCESS==WORD)&QHI
&QB.

Z 10 *= ((ACCESS=-WORI))
& (C3EO=-EVENI) )# (ACC
ESS-=EVEN) Figures 3 to 6 are timing charts regarding byte access, and Figures 3 and 4 are timing charts when writing byte data, that is, from tJ 1 to an external memory or device. 7 shows a timing chart when transferring high data. Figures 5 and 6 show timing charts when reading byte data, that is, when transferring high 1 data from an external memory or device to CI) U 1. A timing chart is shown.

FIG. 3 shows the timing for writing hide data at even addresses, and FIG. 4 shows the timing for writing hide data at odd addresses. In these byte accesses, control signals J1. J2 switches the bidirectional buffers 3 and 4, and read pulse RI) switches the direction of data in the bidirectional buffers 3 and 4. In other words, with the read pulse RD, during a write operation, data is output from the internal lotus of the CPU to the external lotus 6, and during a read operation, data is output from the external lotus 6 to the CPU.
Data is output to I's internal bus.

FIG. 5 shows the timing for reading even addresses of hide data, and FIG. 6 shows the timing for reading odd addresses of hide data. These read operations are similar to the write operations described above except for the direction of bidirectional buffers 3 and 4.

Also, the write operation of odd address of word [data] is
The first operation is performed at the timing shown in FIG. 4, and the second operation is performed at the timing shown in FIG. Similarly, in the read operation of odd addresses of word data, the first operation is performed at the timing shown in FIG. 6, and the second operation is performed at the timing shown in FIG.

7 and 8 are timing charts showing word access, FIG. 7 is a timing chart regarding writing of word data at even addresses, and FIG.
The figure is a timing chart regarding reading of even-numbered addresses of word data. In the case of word access to these even addresses, the lowest address I-A
Since O is fixed at 'L, the above-mentioned control circuit 16
As is clear from the above description, the lowest position of the address H-Z 10 is formed in a virtual manner, and the upper and lower positions of the word are switched.

During a write operation (not shown in FIG. 7), a write pulse WR (indicated by a broken line) from CP tJ 1 is formed as a write signal W+'<]l'' with a wide pulse width.

In addition, the control signals j1 and J2 are sequentially set to ``I7'', and the lower 8 hides and the upper 8 hides are sequentially output from the outside.
Output. Further, the control circuit 16 outputs a ready signal RDY* to CI) IJ
] is held.

The read operation of the even number AI'' + NO of the word data shown in FIG. 8 is also performed in the same manner as the write operation described above.

In other words, the width of the read signal is made wider than the read pulse RD output from the CPU 1, and the control signal Jl,
J2 is sequentially set to "L", and the address Z10 is sequentially changed from "L" to "H". Also, the control from the control circuit 16 (K"4, M falling of s3, lower byte data is latched in the data latch 5. Then, when the upper Hyde is complete, it is output from the data latch 5 at the falling edge of the control signal J4.Therefore, it is read as word data [Effects of the Invention] According to the present invention, , while maintaining a continuous address space in Hide (16 bits).
It becomes possible to access devices, memories, etc. that are compatible with CP IJ. Therefore, it is possible to prevent the burden on the software from increasing due to differences in bus sizes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a timing chart used to explain the regulation of the timing of the control circuit; the third, FIG. 4, FIG. 5, and FIG. 6 are timing charts used to explain hide access;
FIGS. 7 and 8 are timing charts used to explain word access. 3.4: Bidirectional frequency converter, 5: Data latch, 6: External 8-bit data bus, 13: Address buffer, 14: External address bus, 16: Control sum circuit. Agent Patent Attorney Tadashi Sugiura Explanation of major symbols in the drawings 1:16 Hits l-CP tJ,

Claims (1)

[Scope of Claim] A bus size conversion device provided between a data bus and address bus of a 16-bit CPU and an external 8-bit data bus and address bus, wherein the lower 8 bits of the data bus of the CPU and the a first bidirectional buffer provided between the external 8-bit data bus; and a second bidirectional buffer provided between the upper 8 bits of the CPU data bus and the external 8-bit data bus. a bidirectional buffer; a data latch provided between the lower 8 bits of the CPU and the external 8-bit data bus, and transmitting data from the 8-bit data bus to the data bus of the CPU; An address buffer provided between the address bus of the CPU and the external 8-bit address bus, and a signal from the CPU indicating that the upper bits of the address bus are to be used, the least significant bit of the address, and a read pulse. A write pulse is input, and a signal for controlling the first and second bidirectional buffers, the data latch, and the address buffer is output, and the least significant bit of the address is output to the address buffer. A bus size conversion device characterized by comprising a circuit.