JPH0228899B2 - - Google Patents
Info
- Publication number
- JPH0228899B2 JPH0228899B2 JP58016939A JP1693983A JPH0228899B2 JP H0228899 B2 JPH0228899 B2 JP H0228899B2 JP 58016939 A JP58016939 A JP 58016939A JP 1693983 A JP1693983 A JP 1693983A JP H0228899 B2 JPH0228899 B2 JP H0228899B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon nitride
- nitride film
- silicon
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 本発明は容量素子の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a capacitive element.
たとえば１トランジスタ型ICメモリにおいて
は、容量素子の能率を高めるため絶縁部材として
シリコン窒化膜のように高誘電率の絶縁部材の介
在が好ましい。しかしながらシリコン窒化膜は基
体の熱酸化で得られるようなシリコン酸化膜に比
して欠陥密度が高く、高信頼の容量素子を得るこ
とが困難となる。一方、半導体基板のフイールド
領域すなわち不活性領域に厚いフイールド絶縁膜
を形成する際、素子を形成する活性領域にシリコ
ン窒化膜を設けこれをマスクとして上記フイール
ド絶縁膜を形成する。従来はこのフイールド絶縁
膜の形成後マスクとして用いたシリコン窒化膜を
除去し、しかる後に容量素子の誘電体膜となるシ
リコン窒化膜を新たに被着しなおしていた。した
がつて工程数が多くなつていた。 For example, in a one-transistor type IC memory, it is preferable to use an insulating material with a high dielectric constant, such as a silicon nitride film, as the insulating material in order to increase the efficiency of the capacitive element. However, a silicon nitride film has a higher defect density than a silicon oxide film obtained by thermal oxidation of a substrate, making it difficult to obtain a highly reliable capacitive element. On the other hand, when forming a thick field insulating film in a field region, that is, an inactive region of a semiconductor substrate, a silicon nitride film is provided in the active region where elements are to be formed, and this is used as a mask to form the field insulating film. Conventionally, after forming this field insulating film, the silicon nitride film used as a mask was removed, and then a new silicon nitride film, which would become the dielectric film of the capacitive element, was deposited again. Therefore, the number of steps has increased.
この発明の目的は、高能率高信頼の容量素子を
能率よく形成する製造方法を提供することであ
る。 An object of the present invention is to provide a manufacturing method for efficiently forming a highly efficient and highly reliable capacitive element.
この発明の特徴は、半導体基板の活性領域上に
選択的にシリコン窒化膜を形成する工程と、該シ
リコン窒化膜をマスクとして、熱酸化処理によ
り、該半導体基板の不活性領域上に厚い酸化膜を
形成する工程と、しかる後に該シリコン窒化膜の
一部上に容量電極を形成する工程とを有する容量
素子の製造方法にある。 The features of this invention include a step of selectively forming a silicon nitride film on an active region of a semiconductor substrate, and a thermal oxidation process using the silicon nitride film as a mask to form a thick oxide film on an inactive region of the semiconductor substrate. The present invention provides a method for manufacturing a capacitive element, comprising a step of forming a silicon nitride film, and a step of subsequently forming a capacitor electrode on a portion of the silicon nitride film.
このように本発明では、不活性領域に厚い酸化
膜、すなわちフイールド酸化膜を形成するシリコ
ン窒化膜をそのまま容量素子の誘電体膜として用
いることができるから容量素子が能率よく形成で
きる。又、シリコン窒化膜の成長時に発生する欠
陥が、フリールド酸化膜形成の熱酸化工程におい
て、必然的に酸化膜成長で埋まり、誘電体として
の電気的特性も改善されて、高信頼・高能率の容
量素子となる。 As described above, in the present invention, the thick oxide film in the inactive region, that is, the silicon nitride film forming the field oxide film, can be used as it is as the dielectric film of the capacitive element, so that the capacitive element can be formed efficiently. In addition, the defects that occur during the growth of the silicon nitride film are inevitably filled with oxide film growth during the thermal oxidation process for forming the Frield oxide film, and the electrical properties of the dielectric are improved, resulting in a highly reliable and highly efficient product. It becomes a capacitive element.
次に、この発明の特徴をより良く理解するた
め、この発明の実施例につき図を用いて説明す
る。 Next, in order to better understand the characteristics of the present invention, embodiments of the present invention will be described using figures.
第１図〜第３図はこの発明の一実施例を実現す
る主たる製造工程での断面図である。 FIGS. 1 to 3 are cross-sectional views showing the main manufacturing process for realizing an embodiment of the present invention.
この実施例のMOSICは容量素子の一方の電極
となる比抵抗10Ω−cmのＰ型シリコン単結晶基体
１の一表面に200Å〜1000Åのシリコン酸化膜２
を熱酸化成長し、シリコン酸化膜２の表面にシリ
コン窒化膜３を気相成長する。このシリコン窒化
膜３は後に活性領域を成す部分を残して選択的に
食刻され、活性領域周辺の基体表面に表面濃度が
２×1016cm-3の高濃度ボロン導入領域４が設けら
れる。また、シリコン窒化膜３をマスクとして基
体を熱酸化処理することにより活性領域の周囲の
基体表面、即ち不活性領域の表面には1.0〜1.5μ
の厚いシリコン酸化膜５が熱酸化成長する。この
熱酸化処理でシリコン窒化膜５は若干の熱酸化を
受けて表面に200〜300Åのシリコン酸化膜６を形
成する。 The MOSIC of this embodiment has a silicon oxide film 2 of 200 Å to 1000 Å on one surface of a P-type silicon single crystal substrate 1 with a specific resistance of 10 Ω-cm, which serves as one electrode of a capacitive element.
A silicon nitride film 3 is grown on the surface of the silicon oxide film 2 by vapor phase growth. This silicon nitride film 3 is selectively etched leaving a portion that will later form an active region, and a high concentration boron doped region 4 with a surface concentration of 2×10 16 cm -3 is provided on the substrate surface around the active region. In addition, by thermally oxidizing the substrate using the silicon nitride film 3 as a mask, the surface of the substrate around the active region, that is, the surface of the inactive region, is 1.0 to 1.5 μm thick.
A thick silicon oxide film 5 is grown by thermal oxidation. In this thermal oxidation treatment, the silicon nitride film 5 is slightly oxidized to form a silicon oxide film 6 with a thickness of 200 to 300 Å on the surface.
次に、活性領域上のシリコン窒化膜３の上面に
容量素子の他方の電極となる。燐添加の多結晶シ
リコン膜７を成長し、写真食刻により活性領域の
一部の上面に選択的に残し、このシリコン膜７を
熱酸化して5000Å程度のシリコン酸化膜８で被覆
する。しかるのちシリコン酸化膜８をマスクとし
てシリコン窒化膜３を食刻する。この食刻工程で
シリコン膜７と基体１との間に介在するシリコン
酸化膜２，６およびシリコン窒化膜３は容量素子
の絶縁部材として残留する（第２図）。 Next, the upper surface of the silicon nitride film 3 on the active region becomes the other electrode of the capacitive element. A phosphorous-doped polycrystalline silicon film 7 is grown and left selectively on the upper surface of a part of the active region by photolithography, and this silicon film 7 is thermally oxidized to cover it with a silicon oxide film 8 of about 5000 Å. Thereafter, silicon nitride film 3 is etched using silicon oxide film 8 as a mask. In this etching process, the silicon oxide films 2, 6 and silicon nitride film 3 interposed between the silicon film 7 and the substrate 1 remain as insulating members of the capacitive element (FIG. 2).
シリコン窒化膜３が除去された活性領域の表面
に500Åのシリコン酸化膜９をゲート絶縁膜とし
て熱酸化成長させ、このシリコン酸化膜９の上面
に選択的にトランジスタのゲート電極としての多
結晶シリコン膜１０を形成する。このゲート電極
をシリコンゲート型MOS技術の不純物導入マス
クとして用い、イオン注入法により活性領域の基
体中に表面濃度1019〜1020cm-2のＮ型領域１１，
１２を形成する。これらのＮ型領域は所定の開孔
（図示しない）を通して配線電極に導出され、同
時にゲート電極として用いられるシリコン膜１０
の上面にゲート配線電極１３が導電結合して通過
する（第３図）。 A 500 Å silicon oxide film 9 is thermally oxidized and grown on the surface of the active region from which the silicon nitride film 3 has been removed as a gate insulating film, and a polycrystalline silicon film is selectively grown on the upper surface of this silicon oxide film 9 as a gate electrode of a transistor. form 10. Using this gate electrode as an impurity introduction mask for silicon gate MOS technology, an N-type region 11 with a surface concentration of 10 19 to 10 20 cm -2 is formed into the base of the active region by ion implantation.
form 12. These N-type regions are led out to wiring electrodes through predetermined openings (not shown), and at the same time are connected to a silicon film 10 used as a gate electrode.
A gate wiring electrode 13 is conductively coupled to and passes through the upper surface (FIG. 3).
上述の第１図〜第３図の実施例は１トランジス
タ型のMOS−ICメモリを示す。すなわち、Ｎ型
領域１１，１２がドレインおよびソース領域とし
て動作し、シリコン膜１０がゲート電極として動
作するMOSトランジスタと、主としてシリコン
窒化膜３を誘電体としてシリコン膜７の下面に有
する本発明の容量素子とを含むメモリセルを示し
ている。シリコン窒化膜３の上下200Å程度の薄
いシリコン酸化膜２，６は容量素子の安定動作を
保障する。又、シリコン窒化膜３は厚いシリコン
酸化膜５の形成時の熱酸化処理で絶縁性が改善さ
れ、かつピンホールのような欠陥が基体からの酸
化膜の侵入で無欠陥状態となる。 The embodiments shown in FIGS. 1 to 3 described above show a one-transistor type MOS-IC memory. That is, a MOS transistor in which N-type regions 11 and 12 act as drain and source regions and silicon film 10 acts as a gate electrode, and a capacitor of the present invention which mainly has silicon nitride film 3 as a dielectric on the lower surface of silicon film 7 A memory cell including an element is shown. Thin silicon oxide films 2 and 6 of about 200 Å above and below the silicon nitride film 3 ensure stable operation of the capacitive element. Furthermore, the insulation properties of the silicon nitride film 3 are improved by thermal oxidation treatment during the formation of the thick silicon oxide film 5, and defects such as pinholes are made defect-free due to the penetration of the oxide film from the base.
従つてこの発明は高信頼の容量素子を実現する
ことができる。 Therefore, the present invention can realize a highly reliable capacitive element.
第１図〜第３図はこの発明の一実施例を用いた
MOS−ICの主たる製造工程を示す断面図である。
１……一導電型半導体基体、２……シリコン酸
化膜、３……シリコン窒化膜、４……一導電型高
不純物濃度導入領域、５，６……シリコン酸化
膜、７……多結晶シリコン膜、８，９……シリコ
ン酸化膜、１０……多結晶シリコン膜、１１，１
２……ドレイン及びソース領域、１３……ゲート
電極。
Figures 1 to 3 use an embodiment of this invention.
FIG. 3 is a cross-sectional view showing the main manufacturing process of MOS-IC. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate of one conductivity type, 2...Silicon oxide film, 3...Silicon nitride film, 4...High impurity concentration introduction region of one conductivity type, 5, 6...Silicon oxide film, 7...Polycrystalline silicon Film, 8, 9... Silicon oxide film, 10... Polycrystalline silicon film, 11, 1
2...Drain and source region, 13...Gate electrode.
Claims (1)
窒化膜を形成する工程と、該シリコン窒化膜をマ
スクとして、熱酸化処理により、該半導体基板の
不活性領域上に厚い酸化膜を形成する工程と、し
かる後に該シリコン窒化膜の一部上に容量電極を
形成する工程とを有することを特徴とする容量素
子の製造方法。1. A step of selectively forming a silicon nitride film on the active region of the semiconductor substrate, and a step of forming a thick oxide film on the inactive region of the semiconductor substrate by thermal oxidation treatment using the silicon nitride film as a mask. , and then forming a capacitor electrode on a portion of the silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58016939A JPS58151056A (en) | 1983-02-04 | 1983-02-04 | Capacitance element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58016939A JPS58151056A (en) | 1983-02-04 | 1983-02-04 | Capacitance element |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1199176A Division JPS59977B2 (en) | 1976-02-05 | 1976-02-05 | Insulated gate integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58151056A JPS58151056A (en) | 1983-09-08 |
| JPH0228899B2 true JPH0228899B2 (en) | 1990-06-27 |
Family
ID=11930088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58016939A Granted JPS58151056A (en) | 1983-02-04 | 1983-02-04 | Capacitance element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58151056A (en) |
-
1983
- 1983-02-04 JP JP58016939A patent/JPS58151056A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58151056A (en) | 1983-09-08 |
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