JPH02290027A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02290027A
JPH02290027A JP11024389A JP11024389A JPH02290027A JP H02290027 A JPH02290027 A JP H02290027A JP 11024389 A JP11024389 A JP 11024389A JP 11024389 A JP11024389 A JP 11024389A JP H02290027 A JPH02290027 A JP H02290027A
Authority
JP
Japan
Prior art keywords
wiring
signal wiring
width
semiconductor device
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11024389A
Other languages
Japanese (ja)
Inventor
Takayuki Suzu
貴幸 鈴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP11024389A priority Critical patent/JPH02290027A/en
Publication of JPH02290027A publication Critical patent/JPH02290027A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain semiconductor devices having identical characteristics by arranging a dummy wiring in the vicinity of a specified signal wiring and in parallel therewith. CONSTITUTION:In the vicinity of a signal wiring 2 of an Al film having designed specification minimum width, a dummy wiring 3 (which is not connected with a decoding circuit 5 and an I/O pad 4) of an Al film of the same width is arranged. The interval between them is set nearly equal to the minimum width capable of etching. By this constitution, in the adjacency of an arbitrary signal wiring, any one of the other signal wiring 2, a power supply wiring 1, and the dummy wiring 3 always exists, so that the width of the signal wiring is uniformized, and semiconductor devices having identical characteristics can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に長距離にわたる設計規
格最小幅の配線を配置した半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which wiring having a design standard minimum width over a long distance is arranged.

〔従来の技術〕[Conventional technology]

第2図に半導体装置の平面模式図を示す。 FIG. 2 shows a schematic plan view of the semiconductor device.

従来半導体装置のレイアウトを行う際、各機能ブロック
間をアルミニウム膜等の金属配線で接続していた。その
際、広いフィールド領域を設計規格最小幅の信号用配線
2で長距離にわたり配置される事があった。1はデコー
ド回路部5に接続された電源用配線で、信号用配線2よ
り幅が広い金属膜で構成されている。
Conventionally, when laying out a semiconductor device, each functional block was connected with metal wiring such as an aluminum film. At that time, the signal wiring 2 having the minimum width of the design standard was sometimes arranged over a long distance over a wide field area. Reference numeral 1 denotes a power supply wiring connected to the decoding circuit section 5, which is made of a metal film having a wider width than the signal wiring 2.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置は、広いフィールド領域で長
距離にわたり設計規格最小幅の信号用配線を配置してい
た為、パターン形成の製造工程のエッチング時に、この
信号用配線の幅が細く仕上がったりはなはだしい場合に
は溶解してなくなることがある。あるいはエッチングの
種類や条件によっては逆に太くなることもある。いずれ
にせよ、近傍に他の配線が存在しないものは工程上の再
現性が悪くなる欠点がある。
In the conventional semiconductor device described above, signal wiring with the minimum width of the design standard is arranged over a long distance in a wide field area, so it is extremely difficult for the width of the signal wiring to become narrow during etching in the manufacturing process for pattern formation. In some cases, it may dissolve and disappear. Alternatively, depending on the type and conditions of etching, it may become thicker. In any case, if there is no other wiring nearby, there is a drawback that the reproducibility of the process will be poor.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、所定の信号用配線の近傍に平行
して同一物質からなるダミー配線が配置されているとい
うものである。
In the semiconductor device of the present invention, dummy wires made of the same material are arranged in parallel to and near predetermined signal wires.

〔実施例〕〔Example〕

次に、本発明について図面を参照してその構成を説明ず
る。
Next, the configuration of the present invention will be explained with reference to the drawings.

第1図(a>及び(b)はそれぞれ本発明の一実施例を
示す平面模式図、及び部分拡大平面図である。
FIGS. 1A and 1B are a schematic plan view and a partially enlarged plan view showing an embodiment of the present invention, respectively.

設計規格最小幅のアルミニウム膜からなる信号用配線2
の近傍に平行して設計上同じ幅のアルミニウム膜からな
るタミー配線3(テコード回路5、入出力パッド4のい
ずれにも接続されていない。)が配置されている。両者
の間隔はエッチング可能な最小幅の程度にしておく。信
号用配線2の片側近傍にタミー配線のない従来例に比較
して、エツチンク時に幅が細く(あるいは太く)仕上が
る危険性が少なくなる。このようなダミー配線を近傍に
配置する必要のある信号用配線は、その近傍に他の信号
用配線や電源用配線のないものに限る。
Signal wiring 2 made of aluminum film with the minimum width of the design standard
A tummy wiring 3 (not connected to either the code circuit 5 or the input/output pad 4) made of an aluminum film and having the same width in design is arranged in parallel near the . The distance between the two is set to the minimum width that can be etched. Compared to the conventional example in which there is no tummy wiring near one side of the signal wiring 2, there is less risk of the finished width being thin (or thick) during etching. The signal wiring for which it is necessary to arrange such a dummy wiring in the vicinity is limited to one in which there is no other signal wiring or power supply wiring in the vicinity.

なお、タミー配線は電位的には浮遊状態でもよいが、電
源用配線等に接続し、ある電位に固定してもよい。
Note that the tummy wiring may be in a floating state in terms of potential, but it may also be connected to a power supply wiring or the like and fixed at a certain potential.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は所定の信号用配線の近傍に
平行してダミー配線を配置することにより、任意の信号
用配線に隣接して必らす他の信号用配線,電源用配線又
はタミー配線のいずれかが存在することになるので、信
号用配線の幅が均一になり特性の揃った半導体装置が得
られる効果かある。
As explained above, the present invention is capable of arranging dummy wiring in parallel near a predetermined signal wiring, thereby making it possible to connect other signal wiring, power supply wiring, or tummy wiring adjacent to any signal wiring. Since some of the wirings are present, the width of the signal wirings becomes uniform, which has the effect of providing a semiconductor device with uniform characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)及び(b)はそれぞれ本発明の一実施例を
示す平面模式図及び部分拡大平面図、第2図は従来例を
示す平面模式図である。 1・・・電源用配線、2・・信号用配線、3・・・ダミ
ー配線、4・・・入出力パッド、5・・・デコード回路
部。
1A and 1B are a schematic plan view and a partially enlarged plan view showing an embodiment of the present invention, respectively, and FIG. 2 is a schematic plan view showing a conventional example. 1... Power wiring, 2... Signal wiring, 3... Dummy wiring, 4... Input/output pad, 5... Decode circuit section.

Claims (1)

【特許請求の範囲】[Claims] 所定の信号用配線の近傍に平行して同一物質からなるダ
ミー配線が配置されていることを特徴とする半導体装置
A semiconductor device characterized in that a dummy wiring made of the same material is arranged in parallel near a predetermined signal wiring.
JP11024389A 1989-04-27 1989-04-27 Semiconductor device Pending JPH02290027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11024389A JPH02290027A (en) 1989-04-27 1989-04-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11024389A JPH02290027A (en) 1989-04-27 1989-04-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02290027A true JPH02290027A (en) 1990-11-29

Family

ID=14530737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11024389A Pending JPH02290027A (en) 1989-04-27 1989-04-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02290027A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7353481B2 (en) * 2005-01-04 2008-04-01 Kabushiki Kaisha Toshiba Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7353481B2 (en) * 2005-01-04 2008-04-01 Kabushiki Kaisha Toshiba Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit

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