JPH02291173A - Manufacture of mos transistor - Google Patents
Manufacture of mos transistorInfo
- Publication number
- JPH02291173A JPH02291173A JP11146089A JP11146089A JPH02291173A JP H02291173 A JPH02291173 A JP H02291173A JP 11146089 A JP11146089 A JP 11146089A JP 11146089 A JP11146089 A JP 11146089A JP H02291173 A JPH02291173 A JP H02291173A
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- channel
- implanted
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- 229910052796 boron Inorganic materials 0.000 abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 3
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- 238000010884 ion-beam technique Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 101710116852 Molybdenum cofactor sulfurase 1 Proteins 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 210000003371 toe Anatomy 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業」二の利用分野〕
本発明はＭＯＳ ｌ−ランジスタの製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a MOS l-transistor.
ホッＩ〜キャリア劣化耐性が要求されるＭＯＳ ＋一ラ
ンジスタにおいては、デバイスＯＮ状態のときの１へレ
イン近傍チャンネル部に高濃度のキャリアを発生させ、
抵抗を小さく抑えて電界集中を抑制するため、ドレイン
近傍チャンネル部の不純物濃度をソース近傍チャンネル
部の不純物濃度に比較して小さくしていた（参考文献：
Ｙ．Ｔａｒｕｊ ， Ｙ．ｌｌａｙａｓｈｉ ，Ｔ．
Ｓｅｋ．Ｌｇａｗａ， ：“Ｄｉｆｆｕｓｉｏｎ ｓｅ
ｌｆ ａｌｊ．ｇｎｅｄ ＭＯＳＴ ： Ａｎｅｗ
ａｐｐｒｏａｃｈ ｆｏｒ ｈｊ４ｈ ｓｐｅｅ
ｄ ｄｃｖｊｃｅ，′’Ｐｒｏｃ．２ｎｄＣｏｎｆ．
Ｓｏ］．ｉｄ Ｓｔａｔｅ Ｄｅｖｊｃｅｓ， Ｔｏ
ｋｙｏ， １９７０（Ｊ． ｏｆＪａｐａｎ Ｓｏｃ．
Ａｐｐｌ． Ｐｈｙｓ．，４０， Ｓｕｐｐｌ．．，
ｐｐｌ９３−１９８（１９７１））。In a MOS+1 transistor that requires carrier deterioration resistance, a high concentration of carriers is generated in the channel near the 1 line when the device is ON.
In order to keep the resistance low and suppress electric field concentration, the impurity concentration in the channel region near the drain was lower than that in the channel region near the source (References:
Y. Taruj, Y. llayashi, T.
Sek. Lgawa, : “Diffusion se
lf alj. gned MOST: Anew
approach for hj4h spee
d dcvjce,''Proc. 2ndConf.
So]. id State Devjces, To
kyo, 1970 (J. of Japan Soc.
Appl. Phys. , 40, Suppl. ．． ，
ppl93-198 (1971)).
以下、第３図（ａ）〜（．１）の一連の工程図を用いて
、上記構造のｎチャンネルＭＯＳ １−ランジスタの従
来の製造方法の典型的な−実施例について説明する。Hereinafter, a typical embodiment of a conventional method for manufacturing an n-channel MOS transistor having the above structure will be described using a series of process diagrams shown in FIGS.
第３図（ａ）において、不純物濃度Ｉ Ｘ １０” ａ
ｎ−３のｐ形シリコン基板４上に、Ｌ Ｏ Ｃ Ｏ Ｓ
法によって素子分離領域３を形成し、次いで、該基板４
の表面に膜厚］．Ｏｎｍのゲート酸化膜８を熱酸化法に
よって形成し、加速電圧３０ｋ ｅ Ｖ ， ドース量
２Ｘ１０１′ａｎ−”の条件でボロンをイオン注入する
。さらに、ＣＶＤ法によって、膜厚５ ５ ０ ０ ｎ
ｍの多結晶シリコン膜７′を形成する。次に、膜厚１
μｍのフォ１−レジスト１０を塗布した後、露光及びパ
ターニングを行う。さらに、多結晶シリコン膜をフォト
レジスト１０をマスクにしてＲＩＥ法によりパターニン
グし、これをゲート電極７とする。第３図（ｂ）におい
て、フォトレジスト１０を除去した後に、再び、フォト
レジスト２０を塗布し、ソース領域を露出させるように
パターニンクを行う。次に、ボロンを加速電圧５０ｋ
ｅ Ｖ ，ドーズ量Ｉ Ｘ １．０” ａｎ−２をイオ
ン注入した後、フォトレジスト２０を除去し、ソース領
域からソース近傍チャンネル領域にボロンを拡散させ、
ソース近傍チャンネル部高濃度領域を形成するため、窒
素雰囲気中で９５０゜Ｃのアニールを２０分間行う。続
いて、加速電圧］．ＯＯｋｅＶ， トーズ量５ Ｘ １
０”’ ａｎ−２の条件でヒ素をイオン注入し、前記チ
ャンネル部高濃度領域６のポリシリコン部へのドーピン
グ並びにソース９・ドレイン５領域の形成を行う。次に
、第３図（ａにおいて、ＣＶＤ法によってシリコン酸化
膜２を５５０ｎ ｍ形成した後、窒素雰囲気中で１００
０″Ｃのアールを１０分間行う。以下は、通常のポリシ
リコンゲーｈＭＯｓ ｌ〜ランジスタのプロセスと同様
にコンタク１〜ホールを形成し、ソース・ドレイン部及
びゲート部に電極配線１を施してデバイスの最終構造を
得る。In FIG. 3(a), the impurity concentration I
On the n-3 p-type silicon substrate 4, L O C O S
The element isolation region 3 is formed by a method, and then the substrate 4 is
film thickness on the surface]. Onm gate oxide film 8 is formed by thermal oxidation, and boron ions are implanted under the conditions of an acceleration voltage of 30 keV and a dose of 2 x 101'an-''.Furthermore, a film thickness of 5500 n is formed by CVD.
A polycrystalline silicon film 7' having a thickness of m is formed. Next, the film thickness is 1
After coating a photoresist 10 of μm, exposure and patterning are performed. Further, the polycrystalline silicon film is patterned by RIE using the photoresist 10 as a mask, and this is used as the gate electrode 7. In FIG. 3(b), after the photoresist 10 is removed, a photoresist 20 is applied again and patterned to expose the source region. Next, boron is accelerated at a voltage of 50k
After ion implantation with e V and a dose of I
In order to form a high concentration region in the channel near the source, annealing is performed at 950° C. for 20 minutes in a nitrogen atmosphere. Next, the accelerating voltage]. OOkeV, toes amount 5 x 1
Arsenic is ion-implanted under the condition of 0"'an-2 to dope the polysilicon part of the channel part high concentration region 6 and form the source 9 and drain 5 regions. Next, in FIG. After forming a silicon oxide film 2 with a thickness of 550 nm by the CVD method, a silicon oxide film 2 with a thickness of 100 nm is
0''C radius is carried out for 10 minutes.Then, contacts 1 to holes are formed in the same way as the process for normal polysilicon gate hMOS transistors, electrode wiring 1 is applied to the source/drain part and gate part, and the device is completed. obtain the final structure of .
以上のような第３図（ａ）〜（．｛）の製造工程によっ
て、ソース近傍チャンネル領域より低不純物濃度の１・
レイン近傍チャンネル領域を有し、そのためにデバイス
ＯＮ状態のときの１〜レイン近傍のアバランシェホット
エレクトロン発生を低減化し得る構造を得ることが可能
となる。By the manufacturing process shown in FIGS. 3(a) to (.{) as described above, the impurity concentration of 1.
It is possible to obtain a structure that has a channel region near the rain, thereby reducing the generation of avalanche hot electrons near the first to rain when the device is in the ON state.
しかしながらこの製造方法においては、ソース近傍チャ
ンネル部高濃度領域を形成するため、ソース部のみを露
出させるリソグラフィ工程と不純物拡散のためのアニー
ルとが余計に必要である。However, in this manufacturing method, in order to form a high concentration region in the channel region near the source, a lithography step for exposing only the source region and an annealing for impurity diffusion are additionally required.
さらに、リソグラフィ工程は、テバイスの微細化に伴っ
てゲー１へ長が小さくなり、目合わせが困難になりつつ
ある。また、高濃度領域が１〜ランジスタのしきい値電
圧を決定しており、ソース領域からの拡散によってソー
ス近傍チャンネル部高濃度領域の不純物濃度、ひいては
、しきい値電圧を制御することになり、その制御性に問
題があった。Furthermore, in the lithography process, as devices become finer, the length of the gate 1 becomes smaller, making alignment difficult. In addition, the high concentration region determines the threshold voltage of the transistor, and diffusion from the source region controls the impurity concentration in the high concentration region of the channel near the source, and thus the threshold voltage. There was a problem with its controllability.
本発明の目的は半導体装置のかかる欠点を克服し、高い
アパランシェホットキャリア発生耐性及び高いしきい値
電圧制御性を有するデバイスを実現する製造方法を提供
することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method that overcomes these drawbacks of semiconductor devices and realizes a device having high resistance to aparanche hot carrier generation and high threshold voltage controllability.
上記目的を達成するため、本発明によるＭＯＳトランジ
スタの製造方法においては、半導体基板上にゲー１−酸
化膜とその上にゲート電極膜をパターニングした後、ビ
ームをソース側からチャンネル側に入射するように傾け
てチャンネル部と同し型の不純物をななめイオン注入に
よって注入し、ソス近傍チャンネル部にドレイン近傍チ
ャンネル部より高濃度に１くープされた領域を形成する
ものである。In order to achieve the above object, in the method of manufacturing a MOS transistor according to the present invention, after patterning a gate electrode film on a semiconductor substrate and a gate electrode film thereon, a beam is incident on the channel side from the source side. Impurities of the same type as the channel part are implanted by diagonal ion implantation to form a convex region in the channel part near the soss with a higher concentration than the channel part near the drain.
第２図はソース近傍チャンネル部高濃度領域６を形成す
るため、半導体基板４上にゲート酸化膜８及びその上に
ゲー１−電極膜７をパターニングした製造工程途上にお
いて、ビームをソース側からチャンネル側に入射するよ
うに傾け、チャンネル部と同し型の不純物任ななめイオ
ン注入を行った状況を示している。従来と異なる点は、
ソース近傍チャンネル部高濃度領域６の形成にソースか
らの不純物拡散によらず、ななめイオン注入法によって
、直接にソース近傍チャンネル部高濃度領域６にイオン
注入しているという点である。FIG. 2 shows that during the manufacturing process in which a gate oxide film 8 and a gate 1-electrode film 7 are patterned on a semiconductor substrate 4 in order to form a high concentration region 6 in a channel region near the source, a beam is irradiated from the source side into a channel. This figure shows a situation in which impurity ions of the same type as the channel portion were implanted obliquely so that the impurity ions were incident on the side. The difference from the conventional one is that
The point is that ions are directly implanted into the source near channel high concentration region 6 by the diagonal ion implantation method, without relying on impurity diffusion from the source to form the source near channel high concentration region 6.
本発明ではこの処理によって、ソース近傍チャンネル部
高濃度領域６を形成するため、ソース部のみを露出させ
るリングラフィ工程が不用となるまた、チャンネル部高
濃度領域６がトランジスタのしきい値電圧を決定するの
であるが、ソース領域からの拡散によってソース近傍チ
ャンネル部高濃度領域６の不純物濃度を制御しているわ
けではなく、イオン注入によって直接にソース近傍チャ
ンネル部高濃度領域６を形成しているので、しきい値電
圧の制御が容易となる。In the present invention, the high concentration region 6 in the channel region near the source is formed by this process, so the phosphorography process that exposes only the source region is not necessary, and the high concentration region 6 in the channel region determines the threshold voltage of the transistor. However, the impurity concentration in the high concentration region 6 near the source channel is not controlled by diffusion from the source region, but the high concentration region 6 near the source channel is directly formed by ion implantation. , the threshold voltage can be easily controlled.
以下、第１図（ａ）〜（ｄ）の一連の工程図を用いて，
本発明によるｎチャンネルＭ０８１〜ランジスタの典型
的な一実旅例について説明する。Below, using a series of process diagrams in Figures 1 (a) to (d),
A typical example of a journey of the n-channel transistor M081 to transistor according to the present invention will be described.
第」図（ａ）において、不純物濃度１×１０１５ｃＩＴ
＋−３のｐ形シリコン基板４を用い、ＬＯＣＯＳ法によ
って素子分離領域３を形成したのち、該基板４の表面に
膜厚１０ｎｍのゲート酸化膜８を熱酸化法によって形成
し、加速電圧３０ｋｃＶ， ｌ’−ズ量２ Ｘ １．０
１２ｃ＋ｎ−”の条件でボロンをイオン注入し、さらに
、ＣＶＤ法によって、膜厚５５００ｎｍの多結晶シリコ
ン膜７′を形成する。次に、膜厚１μｍのフォｌ−レジ
スト１０を塗布した後、露光及びパターニングを行う。In Figure (a), the impurity concentration is 1 x 1015 cIT.
After forming an element isolation region 3 by the LOCOS method using a +-3 p-type silicon substrate 4, a gate oxide film 8 with a thickness of 10 nm is formed on the surface of the substrate 4 by a thermal oxidation method, and an accelerating voltage of 30 kcV, L'-Z amount 2 x 1.0
Boron is ion-implanted under the conditions of 12c+n-'', and a polycrystalline silicon film 7' with a thickness of 5500 nm is formed by the CVD method.Next, after coating a Fol-resist 10 with a thickness of 1 μm, exposure is performed. and patterning.
さらに、第１図（ｂ）のように多結晶シリコン膜７′を
フォトレジス１〜１０をマスクにしてＲＩＥ法によりパ
ターニンクし、これをゲー１へ電極７とする。引き続き
、ビーｌ１がソース側からチャンネル側に入射するよう
に傾けてチャンネル部と同じ型の不純物であるボロンを
、注入エネルギー］００ｋｅＶ， トーズ量２×１０
′４ｃｍ−、鉛直となす角度６０゜のななめイオン注入
法によって注入し、ソース近傍チャンネル部高濃度領域
６を形成する。Furthermore, as shown in FIG. 1(b), the polycrystalline silicon film 7' is patterned by RIE using the photoresists 1 to 10 as masks, and this is used as the electrode 7 for the gate 1. Subsequently, boron, which is the same type of impurity as the channel part, is implanted by tilting the beam l1 so that it is incident from the source side to the channel side at an energy of 00 keV and a torsion amount of 2×10.
The high concentration region 6 in the channel region near the source is formed by diagonal ion implantation at an angle of 60° with respect to the vertical.
続いて、加速電圧１００ｋｃＶ， ｌ＜ーズ量５Ｘ１０
”ｒｍ２の条件でヒ素をイオン注入し、前記ｉｔ−ｆ＋
ａ度領域６のポリシリコン部への１一一ピング並びに
ソース９・ドレイン５領域の形成を行う。次に、フオ１
〜レジス１ヘ１０を除去した後、第１図（（１）のよう
にＣＶＤ法によってシリコン酸化膜２を５５０ｎｍ形成
し、窒素雰囲気中で１０００゜Ｃのアニールを１０分間
行う。以下は、通常のポリシリコンゲートＭＯＳ ｌ−
ランジスタのプロセスと同様にコンタク１〜ホールを形
成し、ソース・ドレイン部及びゲート部に電極配線１を
施してデバイスの最終構造を得る。Next, the acceleration voltage is 100kcV, l<the amount of noise is 5X10
Arsenic is ion-implanted under the condition of "rm2, and the it-f+
The polysilicon portion of the a-degree region 6 is subjected to 1-1 ping and the source 9 and drain 5 regions are formed. Next, Huo1
After removing the resist 10 from the resist 1, a silicon oxide film 2 of 550 nm is formed by the CVD method as shown in FIG. polysilicon gate MOS l-
Contacts 1 to holes are formed in the same manner as in the transistor process, and electrode wiring 1 is applied to the source/drain portions and gate portions to obtain the final structure of the device.
なお、以上実施例ではｒｌチャンネルＭＯＳ ＋〜ラン
ジスタを示したが、本発明の製造方法は明らかにｎチャ
ンネルＭＯＳ ｈランシスタ特有のものではなく、一般
のＭＯＳ １〜ランジスタに応用でき、従って、本発明
製造方法の原理を用いるこれら一般のＭＯ５１〜ランジ
スタの製造方法は当然すべて本発明に含まれる。Although the above embodiments have shown rl channel MOS + to transistors, the manufacturing method of the present invention is obviously not specific to n-channel MOS h transistors, but can be applied to general MOS 1 to transistors. Naturally, all methods of manufacturing these general MO51 transistors using the principle of the manufacturing method are included in the present invention.
以上のように、本発明のＭＯＳ ＋−ランシスタ製造方
法によれば、半導体基板上にケー１〜酸化膜及びその」
一にゲート電極膜をパターニングしたＭＯＳ トランジ
スタ製造工程途上において、ビームがソース側からチャ
ンネル側に入射するように傾けてチャンネル部と同じ型
の不純物をななめイオン注入により注入し、ソース近傍
チャンネル部にドレイン近傍チャンネル部より高濃度に
ドープされた領域を形成することによって、ソース近傍
チャンネル部高濃度領域を容易、且つ、確実に形成する
ことができる効果を有するものである。As described above, according to the method for manufacturing a MOS +-Lancisister of the present invention, the oxide film and the oxide film are formed on the semiconductor substrate.
During the manufacturing process of a MOS transistor in which the gate electrode film is first patterned, impurities of the same type as the channel part are implanted diagonally so that the beam is incident from the source side to the channel side, and the drain is implanted into the channel part near the source. By forming a region more highly doped than the adjacent channel portion, the highly doped region near the source channel portion can be easily and reliably formed.
第１図（ａ）〜（ｄ）は本発明のｎチャンネルＭＯＳ
トランジスタ製造方法の一実施例を示す一連の工程図、
第２図は本発明のＭＯＳ Ｉ−ランジスタ製造方法の特
長であるななめイオン注入法を用いてソース近傍チャン
ネル部高濃度領域を形成した概略図、第３図（ａ）〜（
ｄ）はＭＯＳトランジスタの従来の製造方法の典型的な
一実旅例の概略断面図である。
１・・電極配線膜 ２・ＣＶＤシリコン酸化膜３
素子分離領域 ４ ｐ形シリコン基板５・・ドレ
インFigures 1(a) to 1(d) show n-channel MOS of the present invention.
A series of process diagrams showing an example of a transistor manufacturing method,
FIG. 2 is a schematic diagram of forming a high concentration region near the source channel using the diagonal ion implantation method, which is a feature of the MOS I-transistor manufacturing method of the present invention, and FIGS.
d) is a schematic cross-sectional view of a typical example of a conventional manufacturing method of a MOS transistor. 1. Electrode wiring film 2. CVD silicon oxide film 3
Element isolation region 4 P-type silicon substrate 5...Drain
Claims (1)
極膜をパターニングした後、ビームをソース側からチャ
ンネル側に入射するように傾けてチャンネル部と同じ型
の不純物をななめイオン注入によって注入し、ソース近
傍チャンネル部にドレイン近傍チャンネル部より高濃度
にドープされた領域を形成することを特徴とするＭＯＳ
トランジスタの製造方法。(1) After patterning a gate oxide film and a gate electrode film on the semiconductor substrate, the beam is tilted so that it is incident from the source side to the channel side, and impurities of the same type as the channel part are implanted by diagonal ion implantation. , a MOS characterized in that a channel region near the source is doped with a higher concentration than a channel region near the drain.
Method of manufacturing transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11146089A JPH02291173A (en) | 1989-04-28 | 1989-04-28 | Manufacture of mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11146089A JPH02291173A (en) | 1989-04-28 | 1989-04-28 | Manufacture of mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02291173A true JPH02291173A (en) | 1990-11-30 |
Family
ID=14561798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11146089A Pending JPH02291173A (en) | 1989-04-28 | 1989-04-28 | Manufacture of mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02291173A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0789401A3 (en) * | 1995-08-25 | 1998-09-16 | Matsushita Electric Industrial Co., Ltd. | LD MOSFET or MOSFET with an integrated circuit containing thereof and manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5368079A (en) * | 1976-11-30 | 1978-06-17 | Cho Lsi Gijutsu Kenkyu Kumiai | Short channel mos transistor and method of producing same |
| JPS53119686A (en) * | 1977-03-29 | 1978-10-19 | Agency Of Ind Science & Technol | Production of semiconductor device |
| JPS56126970A (en) * | 1980-03-11 | 1981-10-05 | Nippon Telegr & Teleph Corp <Ntt> | Mos field effect transistor and manufacture thereof |
| JPS5961185A (en) * | 1982-09-30 | 1984-04-07 | Fujitsu Ltd | Manufacture of metal insulator semiconductor field-effect semiconductor device |
-
1989
- 1989-04-28 JP JP11146089A patent/JPH02291173A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5368079A (en) * | 1976-11-30 | 1978-06-17 | Cho Lsi Gijutsu Kenkyu Kumiai | Short channel mos transistor and method of producing same |
| JPS53119686A (en) * | 1977-03-29 | 1978-10-19 | Agency Of Ind Science & Technol | Production of semiconductor device |
| JPS56126970A (en) * | 1980-03-11 | 1981-10-05 | Nippon Telegr & Teleph Corp <Ntt> | Mos field effect transistor and manufacture thereof |
| JPS5961185A (en) * | 1982-09-30 | 1984-04-07 | Fujitsu Ltd | Manufacture of metal insulator semiconductor field-effect semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0789401A3 (en) * | 1995-08-25 | 1998-09-16 | Matsushita Electric Industrial Co., Ltd. | LD MOSFET or MOSFET with an integrated circuit containing thereof and manufacturing method |
| US5905284A (en) * | 1995-08-25 | 1999-05-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device with a particular DMISFET structure |
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