JPH022930A - Automatic ultrasonic wave flaw detecting apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an ultrasonic flaw detection device that inspects materials using a water immersion method, and in particular, it can automatically inspect materials even when the sound velocity or dimensions of the material change. The present invention relates to an ultrasonic flaw detection device suitable for flaw detection inside.

[Conventional technology]

The conventional ultrasonic flaw detector is (“Ultrasonic flaw detection method” edited by the 19th Steelmaking Committee of the Japan Society for the Promotion of Science [revised new edition]-P677-)
As shown in Figure 2, it was a semi-fixed flaw detection gate setting method in which the gate start point and gate width (range) were adjusted manually.

However, no consideration was given to setting the flaw detection gate when the surface echo (Sl echo) reflected from the surface of the test material and the bottom echo (Bl echo) reflected from the bottom surface of the test material fluctuate during flaw detection.

[Problem to be solved by the invention]

The above conventional technology does not take into account the setting of the flaw detection gate in a state where the SL echo detection time changes and the B1 echo detection time changes at the same time, and when the sound velocity in the test material 5 changes. (Fig. 3(a)), and when the distance from the probe 1 to the test material surface 2 or the distance from the test material surface 2 to the bottom surface 3 changes (Fig. 3(b)),
As shown in FIG. 3(c), the SL echo 11 and the B1 echo 12 either entered the flaw detection gate 20 or were scattered far away, creating a dead zone, so normal flaw detection could not be performed.

The purpose of the present invention is to provide a device for flaw detection using the water immersion method.
An object of the present invention is to provide an automatic ultrasonic flaw detection device that has a function of reliably setting a flaw detection gate in the test range from the surface to the bottom of the test material when testing materials with different sound velocities and material dimensions. .

Another object of the present invention is to use defect echoes (F
An object of the present invention is to provide a B1 echo discriminating device that can reliably discriminate between B1 echoes and 81 echoes.

[Means to solve the problem]

The purpose of the above automatic ultrasonic flaw detection system is to control the flaw detection gate start point using the S1 echo, and to control the flaw detection gate end point by the ultrasonic wave that the probe is excited and transmitted by the previous pulse generated by the pulser. By controlling the time interval between the S1 echo and the B1 echo obtained from the sound waves, the flaw detection gate range can always be set from immediately after the S1 echo to immediately before the 81st echo.

The purpose of the B1 echo discriminator is to create a pulse corresponding to the maximum time at which the B1 echo fluctuates due to changes in the dimensions and sound speed of the test material, and to detect the echoes detected from the S1 echo detection time to the pulse generation time. Incorporate all
A B1 echo can always be detected by detecting an echo that appears at a time immediately before the pulse generation time.

[Effect]

In the automatic flaw detection gate setting method according to the present invention, the detection times of S1 echo and Bl echo and the time interval between the two are measured based on a synchronization signal of a constant period, and the start point and end point of the flaw detection gate are determined. While controlling, flaw detection is performed by sequentially setting flaw detection gates using synchronization signals. This makes it possible to perform ultrasonic flaw detection on test materials with different material dimensions and test materials with uneven sound velocities in the material.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows the basic configuration of the conventional ultrasonic flaw detection apparatus shown in FIG. 4, with the addition of an automatic flaw detection gate setting device and an automatic probe scanning device according to the present invention. Therefore, the basic configuration shown in FIG. 4 will be explained first. FIG. 4 shows a test material 5 and a probe 1 immersed in water 4. The probe 1 is excited by a pulser 31 and sends ultrasonic waves to the test material 5 through the water 4.

The ultrasonic waves reflected from the interface between the water 4 and the test material surface 2 and the bottom surface of the test material 5, that is, the S1 echo and the B1 echo, are
The signal is converted into an electrical signal by the probe 1, amplified by the amplifier 32, detected by the detector 33, and sent to the video amplifier 69 and gate circuit 67. In addition, the gate circuit 67 is supplied with flaw detection gate signals set in advance by a gate marker generator 66, that is, S1 echo and B
A signal is sent to monitor whether or not an echo is detected in the range between one echo. When an echo is detected within the flaw detection gate range, the gate circuit 67 outputs the data to the recorder 68. On the other hand, the video amplifier 71 amplifies the signal detected by the detector 33 and outputs it to the display 70.

At this time, if the distance between the probe 1 and the test material surface 2 or the distance between the test material surface 2 and the bottom surface 3 changes, or if the sound speed in the test material 5 changes, the flaw detection gate should be changed each time. As mentioned in Figure 3, automatic flaw detection cannot be applied with this semi-fixed gate setting, which requires resetting and flaw detection.

In order to solve these problems, in FIG. 1, the basic configuration of FIG. 4 is combined with an automatic flaw detection gate setting device and a coupler 71 according to the present invention. Scanner 72. A scanner controller 73 is added.

Regarding the automatic flaw detection gate setting device according to the present invention.

Constructed using the attached figures, mainly Figures 1 and 2.

And the operation will be explained.

The synchronization circuit 30 is a rectangular wave pulse train (abbreviated as (1) below (1) in Fig. 2) for synchronizing the operation of each part of the main casing.
is generated, and the pulser 31. Delay circuit 34, bistable flip-flop circuit 37. Bll echo monitoring gate entrance circuit 4
The synchronizing signal (1) is output to the 5 counter circuit 62.

The pulser 31 receives pulses from the synchronous circuit 30 and generates a pulse voltage (2) for exciting the probe 1. contact 1
The ultrasonic echo received by
3, it is detected as an ultrasonic echo signal (3).

The ultrasonic echo signal (3) is sent to the gate circuit 35°67
is output to. The delay circuit 34 is a circuit that delays the opening time of the gate circuit 35 from the synchronization signal (1), and sends the gate opening signal to the gate circuit 35. The gate circuit 35 is opened immediately after the transmission wave 10 of the ultrasonic echo signal (3) inputted from the detector 33, and is opened immediately after the transmission wave 10 of the ultrasonic echo signal (3) inputted from the detector 33.
Echo 11.81 Echo 12. The F echo 13) is detected, and the signal is transmitted to the waveform shaper 36 to be converted into a waveform shaped signal (4) and transmitted to the AND circuit 40°41.61.

On the other hand, the stable flip-flop circuit 37 receives the synchronization signal (1
), which becomes a high level at the nth rising time and becomes a low level at the n+1st rising time, that is, the flip-flop signal (5), is applied to AND circuits 39, 40 .
41, counter circuits 38, 42, and register circuit 44.
It is output to the voltage comparison circuit 57 and NOT circuit 60.

The AND circuit 41 sends the waveform shaping signal (6) to the counter circuit 42 when the flip-flop signal (5) is at a high level (n-th synchronization). The counter circuit 42 has a fifth
As shown in figures (,) and (e), when the flip-flop signal (5) is input, it is cleared and the AND circuit 41
This circuit outputs only the first pulse (SL pulse 14) of the pulse train when the output signal (22) is input. The output signal (6) of the counter circuit 42 is transmitted to the integrator circuit 4
Sent on 7, 49.50, 51.52. Integrating circuit 47
, 49.50, 51.52, when the output signal (6) of the counter circuit 42 is input, the pulse generator 43 starts integral calculation with the sent pulse.

That is, the calculation is started from the rise time of the n-th 81st pulse 14.

Next, like the AND circuit 41, the AND circuit 40 transmits the waveform shaping signal (4) to the counter circuit 38 when the flip-flop signal (5) is at a high level. The counter circuit 38 is shown in FIG. 6(a).

As shown in (b), the pulse (F pulse 15) of the second pulse of the pulse train of the AND circuit 40 output signal (23)
．． This circuit sequentially outputs Bl pulses 16) up to the n-th pulse at most, and outputs the counter circuit 38 output signal (7) to the register circuit 44. Also.

The B1 echo monitoring gate circuit 45 is a B1 echo monitoring gate 4 that is set slightly larger than the variation range of the B1 echo.
5 signal (8) is transmitted to the NOT circuit 46, and the signal is inverted and sent to the differentiating circuit 46'.

The differentiating circuit 46' generates a signal that generates a pulse at the closing time of the B1 echo monitoring gate, that is, a GE pulse signal (9), and sends it to the AND circuit 39.

The A N D circuit 39 outputs the GE pulse signal (9) to the register circuit 44 and the integration circuit 47 when the flip-flop signal (5) is at a high level.

Next, regarding the operation of the register circuit 44, 1 and 2 in FIG.
Explain using. When the output signal (7) (F pulse 15, Bl pulse 16) of the counter circuit 38 is input, the register circuit 44 inputs the output signal from the first terminal of this pulse train to the terminal 1.
, 2...n, the pulses are sequentially output to the integrating circuits 49 to 5o. Furthermore, when the GE pulse signal (9) is input, the circuit forcibly outputs a pulse to the non-output terminal at that time, that is, at the closing time of the B1 echo monitoring gate.

An example of a circuit that obtains the function of this register circuit is shown in FIG.

The pulse signals outputted from the output terminals 1, 2, . . .
is input, and the integral calculation ends at the rise time of each pulse. Integrating circuit 49°50.51.52 is S
Measures the voltage proportional to the interval between one pulse and the input pulse,
Integrating circuit 49°50.51.52 output signal ((j), (
k).

(Q), (m)) respectively to peak hold circuits 53.
54, 55, and 56. The peak hold circuit holds the peak voltages and sends these voltage values (Vl, Vx +...Vn) to the voltage comparison circuit 57.

Further, the integrating circuit 47 performs G from the rising time of the S1 pulse.
Perform integral calculations up to the rise time of the E pulse signal (9), and calculate the S
The voltage value (Vaε
) and send the signal (n) to the peak hold circuit 4.
Tell 8. The peak hold circuit 48 maintains its voltage value (
VGE) and sends it to the voltage comparator circuit 57.

The voltage comparison circuit 57 is a circuit that compares the voltage value (Vl, . . . vTh) output from the integration circuits (51 to 54) and the voltage value (VGE) output from the integration circuit 47, and compares the voltage value (VGE) output from the integration circuit 47.
VGE) and voltage value (v, ), -, fTl, positive value (V
l), and when VGE>V, the voltage value (V)
Output. 8(a), (b) In the case of this embodiment, when the voltage value (v2) is input from the f1 dividing circuit 50, that is, at the voltage value proportional to the interval between the S1 pulse and the B1 pulse, VGE is >V2, so the voltage comparator circuit 5
7 output signal (15) is output to the comparator 58.

On the other hand, the NOT circuit 60 receives the flip-flop signal (5)
When the low level signal of A is input, that is, when the n+1th synchronization is performed, a high level signal is generated
Output to ND circuit 61.

When the AND circuit 61 receives a high level signal,
Waveform shaping signal (4) sent from the waveform shaping circuit 36
is output to the counter circuit 62. The counter circuit 62 is
The first pulse of the input pulse train (S1 pulse 17)
The counter circuit 62 output signal (16) is outputted to the delay circuit 63 (FIG. 5(b), (c)). The delay circuit 63 is a circuit that generates a pulse that specifies the gate start time, and generates a gate start signal (17) at a time delayed by a time equal to or longer than the pulse width of the 81 echo 11 from the rising time of the S1 pulse 17. It is output to the gate marker generator 66 and the integrating circuit 64. The integration circuit 64 uses a pulse sent from the pulse generator 43 to calculate the timing from the pulse rise time of the gate start signal (17) inputted from the delay circuit 63 based on the integration constant set slightly larger by the integration constant setting device 65. Integral calculation is performed and the output signal (18) of the integration circuit 64 is sent to the comparator 58.
Output to.

The comparator 58 receives the output signal (1
5) and the output signal (18) of the integrating circuit 64, it detects the time when the voltage of the output signal (18) of the integrating circuit 64 reaches V2 and outputs it to the waveform shaping circuit 59. The waveform shaping circuit 59 outputs a pulse of the gate end signal (19) to the gate marker generator 66 at the detected time, that is, at the time when the flaw detection gate is closed.

The gate marker generator 66 creates a flaw detection gate signal (2o) from the gate start signal (17) input from the delay circuit 63 and the gate end signal (19) input from the waveform shaper 59, and outputs it to the gate circuit 67. do. The gate circuit 67 is a circuit that opens and closes the gate in response to a flaw detection gate signal (20) and allows the ultrasonic echo signal (3) from the detector 33 to pass only during a specific time period. In this embodiment, the defect echo signal 18 passes through this flaw detection gate 1-. Also,
The gate circuit 67 is connected to a recorder 68, and if there is a signal that has passed through the gate, it can be recorded on the recorder.

In the automatic flaw detection setting method according to the present invention, the probe sends ultrasonic waves into the test material at regular intervals based on a constant synchronization signal, and the S1 echo reflected from the test surface and the bottom surface.
And, the B1 echo is received. In this case, information for determining the gate closing time is collected from the ultrasonic echo received by the probe by the nth synchronization signal, and information for determining the gate start time is obtained from the (n+1)th synchronization signal. A flaw detection gate is created from both of these pieces of information, and flaw detection is performed using the (n+1)th synchronization signal.

Next, the probe 1 is connected to a scanner 72 by a coupler 71, and the scanner 72 is connected to a scanner controller 73. When the scanner 65 receives X and Y control signals from the scanner controller, it operates based on the signals and can scan the probe 1 on the test material 5.

According to this embodiment, the probe gate can be set between the surface 2 and the bottom surface 3 of the test material while automatically scanning the probe.
Defects in the test material 5 can be detected.

This time, we conducted an ultrasonic flaw detection test on carbon graphite (graphite material). It was found that this material has the characteristic that the sound speed varies depending on the material of the test material and the direction of ultrasonic propagation. Longitudinal direction of carbon graphite block specimen,
Lateral direction, thickness direction.

Attachment 2 shows the results of measuring the anisotropy of sound velocity in the thickness direction. The speed of sound differs depending on the material, especially the density, and even within the same material there is a difference depending on the direction. Among the three types of materials measured this time, there was a maximum difference of 970 m/see. Furthermore, it was observed that the sound speed changed depending on the position of the test material even in the same ultrasonic propagation direction.

When performing water immersion automatic ultrasonic flaw detection, a gate circuit is used to distinguish and detect the bottom echo of the test material and the defect echo, but the position of the gate is affected by the speed of sound. It is necessary to reset the settings depending on the flaw detection of the uniform area, the material, and the flaw detection direction. In addition, the position of the surface echo of the material changes because the test material is in the form of a block of material, the cut surface of the material is rough due to rough cutting, and the dimensional accuracy is poor. Therefore, it is difficult to perform flaw detection on a number of such materials at once.

〔Effect of the invention〕

According to the invention, a material in which the speed of sound changes inside the test material, a material in which the dimensions of the test material change, or.

Even when testing materials with many different dimensions, the flaw detection gate can be set automatically and reliably, preventing defects from being overlooked and erroneous evaluations.

[Brief explanation of the drawing]

Figure 1 is a system diagram of an apparatus according to an embodiment of the present invention, Figure 2 is a diagram of the main signal characteristics of the apparatus, and Figure 3 (a) is an explanation of the case where the sound speed of a conventional test material changes. Fig. 3(b) is an explanatory diagram of the case where the dimensions of the conventional test material change, Fig. 3(c) is an explanatory diagram of the case where the conventional flaw detection gate cannot be applied, and Fig. 4.
The figure is a system diagram of a conventional ultrasonic flaw detection device, FIG. 5(a) is a circuit diagram of the counter circuit 42, FIG. 5(b) is a circuit diagram of the counter circuit 62, and FIG. 5(C) is a circuit diagram of the counter circuit 42. Circuit 42.
62, FIG. 6(a) is an explanatory diagram of the counter circuit 38, FIG. 6(b) is an explanatory diagram of the signals of the counter circuit 38, FIG. 7(a) is a circuit explanatory diagram of the register circuit 44, 7th
FIG. 8(b) is a flowchart of the register circuit 44, FIG. 8(a) is a circuit explanatory diagram of the voltage comparison circuit 57, and FIG. 8(b)
is a flowchart 1 of the voltage comparison circuit 57, and FIG. 9 is a system diagram of the register circuit 44. 1... Probe, 2... Test material surface, 3... Bottom surface, 4
...Water, (21) Vol. -, Pu 4 No. 4 (5) CA) Engineering No. 43 (A) (j

Claims (1)

[Claims] 1. A probe equipped with a transducer that transmits and receives ultrasonic waves, a pulser that excites the transducer, a receiver that amplifies the received signal of the transducer, and the received signal. In an ultrasonic flaw detection device equipped with a gate circuit that allows signals to pass only during a specific time period, the ultrasonic flaw detection device includes a device that constantly detects the ultrasonic propagation time between the probe and the surface of the test material; A bottom echo discriminator is installed to detect bottom echoes reflected from the bottom surface, and the gate position and gate setting range can be continuously adjusted by constantly detecting the ultrasonic propagation time between the surface of the test material and the bottom surface. Features of automatic ultrasonic flaw detection equipment. 2. In the automatic ultrasonic flaw detection device according to claim 1, in the circuit that generates the gate closing signal of the B1 echo discrimination device, by comparing the number of reference pulses and the number of input pulses. An automatic ultrasonic flaw detection device that features adjustable gate width. 3. In the automatic ultrasonic flaw detection device according to claim 1, a signal for setting a gate width is created using one pulse of a series of generated ultrasonic pulse trains as a trigger; Detect flaws by creating a signal that sets the gate open with a pulse. That is, the automatic ultrasonic flaw detection apparatus is characterized in that it alternately executes a gate width setting cycle and a flaw detection cycle. 4. In the automatic ultrasonic flaw detection device according to claim 1, generating a rectangular wave with a period twice that of the synchronization clock pulse, and using its high level for the gate width setting cycle, An automatic ultrasonic flaw detection device characterized in that the low level is used as a switching signal for a flaw detection cycle. 5. In the bottom echo discriminator, a gate is set in advance to monitor the bottom surface of the changing test material, and the echoes generated from the time when the surface echo of the test material is generated to the time when the closing signal of this monitoring gate is generated. A patent characterized in that a bottom echo discrimination device is provided for detecting all of the echoes, detecting the echo detected one time before the monitoring gate closing signal generation time, and extracting the bottom echo. An automatic ultrasonic flaw detection device according to claim 1. 6. A circuit that generates a gate closing signal by comparing the output voltage of an integrator circuit that generates a voltage proportional to the number of input pulses with a preset reference voltage, and in the circuit, the integrator circuit 2. The automatic ultrasonic flaw detection apparatus according to claim 1, further comprising means for adjusting the gate width by changing the integral constant of.