JPH02295346A - Image processing device - Google Patents

Abstract

PURPOSE:To enable the picture working processing of high quality by converting a specified color, which is detected based on the output of a detecting means and a non-rectangular picture area signal, to the other color. CONSTITUTION:A digital color picture reader (called color reader) 1 and a digital color picture printer (color printer) 2 in a lower part are provided. This color reader 1 reads the color picture information of an original by colors by using a color separating means and a photoelectric converting element such as a CCD and converts the information to electric digital picture signals. The color printer 2 reproduces color pictures by colors in correspondence to the digital picture signal. Then the color pictures are transferred by plural times and recorded in a digital dot form at on paper to be recorded. Namely, the specified color in the color picture is detected and based on the detection output and non-rectangular picture area signal, the detected specified color is converted to the other color. Thus, the picture working processing of the high quality can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that digitally processes an input image and performs various image processing on the input image.

[Conventional technology]

In recent years, digital color copying machines that obtain digital color hard copies by color-separating a color original, reading each pixel, digitally processing the read image data, and outputting it to a color printer have become widespread. This type of device has the advantage of being able to process image data digitally, so it is possible to move the image output position (
Fig. 72(a)), extracting a desired image area (Fig. 72(b)), converting only a certain color within the desired area (Fig. 72(C)), and storing data in memory. It has become possible to perform various image processing such as inserting written characters and images into a reflective original (FIG. 72(d)), and its application in the field of so-called color copying is expanding.

Therefore, by combining various functions, it has become possible to easily apply it to color proposals, advertising posters, promotional materials, design drawings, etc.

On the other hand, for color reflective originals, the letters look more like letters.
There is a growing demand for images to look more like real images, and in response to this, image area separation is used to separate text and image areas.
High-resolution processing is applied to the text portion, particularly black characters are printed in a single black color, while high-gradation processing is applied to the image portion.

[Problem that the invention is trying to solve]

However, the conventional example described above has the following drawbacks because it operates to perform color conversion processing on a rectangular area.

(1) When a plurality of areas having converted colors are so adjacent that they cannot be separated by rectangular areas, and it is desired to perform color conversion processing on only one of them (Figure 1θ), the desired image cannot be obtained.

(2) When performing color conversion to an area consisting of colors with wide gradations, detection errors were noticeable because the detection width had to be widened considerably. Conversely, when the detection width was narrowed in an attempt to suppress errors, the desired portion was not converted.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing apparatus capable of eliminating such drawbacks and performing high-quality image processing.

[Means and operations for solving the problems] In order to solve the above problems, the image processing device of the present invention includes means for detecting a specific color in a color image based on input image data, and a non-rectangular image area signal. The image forming apparatus is characterized in that it has a generating means for generating a color, and a converting means for converting a detected specific color into another color based on the output of the detecting means and a non-rectangular image area signal.

(Margin below) 〔Example〕 Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an example of a schematic internal configuration of a digital color image processing system according to the present invention. As shown in the figure, this system includes a digital color image reading device (hereinafter referred to as a color reader) 1 at the top and a digital color image printing device (hereinafter referred to as a color printer) 2 at the bottom. This color reader 1 includes color separation means and C
A photoelectric conversion element such as a CD reads the color image information of the original for each color and converts it into an electrical digital image signal. Further, the color printer 2 is an electrophotographic laser beam color printer that reproduces a color image in each color according to the digital image signal, and records the image by transferring it to recording paper multiple times in the form of digital dots.

First, an overview of the color reader I will be explained.

3 is a document, 4 is a platen glass on which the document is placed, and 5 is a lens for condensing the reflected light image from the document exposed and scanned by the halogen exposure lamp 10 and inputting the image to the 1-magnification full-power color sensor 6. It is a door array lens, 5, 6,
7. 10 as a document scanning unit 11, which performs exposure scanning in the direction of arrow AI.

The color separation image signals read every line without exposure scanning are amplified to a predetermined voltage by the sensor output signal amplification circuit 7, and then inputted to a video processing unit to be described later via a signal line 501, where they are processed. . Details will be described later. 501 is a coaxial cable for ensuring faithful transmission of signals. A signal 502 is a signal line that supplies drive pulses for the same-magnification full-strength color sensor 6, and all necessary drive pulses are generated within the video processing unit l2. 8
．． Reference numeral 9 denotes a white plate and a black plate for correcting the white level and black level of the image signal, which will be described later.By irradiating with a halogen exposure lamp 1O, a signal level of a predetermined density can be obtained, and the white plate of the video signal can be Used for level correction and black level correction. 13 is a control unit having a microcomputer, which is connected to the bus 508
Display on the operation panel 20, key manual control, control of the video processing unit 12, position sensor S
l, S2 to set the position of the original scanning unit }11 to the signal line 5.
09, 510, and a stepping motor l4 for moving the scanning body 11 via the signal line 503.
Stepping motor drive circuit control to pulse drive,
The halogen exposure lamp IO is turned on via the signal line 504 by the exposure lamp driver. ．． /OFF control, light intensity control, digitizer l via signal line 505
6 and internal keys, display control, etc. Color reader part 1
All controls are in place. The color image signal read by the above-mentioned exposure scanning unit 11 during original exposure scanning is inputted to the video processing unit l2 via the amplifier circuit 7 and the signal line 501, and is subjected to various processes described later in this unit l2. , are sent to the printer part 2 via the interface circuit 56.

Next, an outline of the color printer 2 will be explained. 711 is a scanner, a laser output unit that converts the image signal from the color reader 1 into an optical signal, and a polyhedron (for example, an octahedron).
polygon mirror 712, a motor (not shown) for rotating this mirror 712, and a [/θ lens (imaging lens)]
713 etc. 714 is a reflecting mirror that changes the optical path of the laser beam, and 715 is a photosensitive drum. The laser beam emitted from the laser output section is reflected by a polygon mirror 712, passes through a lens 713 and a mirror 714, and linearly scans (raster scan) the surface of a photosensitive drum 715, forming a latent image corresponding to the original image. do.

In addition, 711 is a primary charger, 718 is a full exposure lamp,
723 is a cleaner section that collects residual toner that has not been transferred; 724 is a pre-transfer charger; these members are arranged around the photosensitive drum 715.

726 is a developer unit that develops the electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure, and 731Y, 731M, 731C, and 7318k are developing sleeves that directly develop the photosensitive drum 715 and 730Y. , 730M, 730C, and 7308k are toner hoppers for holding spare toner; 732 is a screw for transporting the developer; and these sleeves 73
1Y~7318k, Toner hopper-730Y~730
8k and screw 732 to connect the developer unit 72.
6, and these members are arranged around the rotation axis P of the developing unit. For example, when forming a yellow toner image, yellow toner development is performed at the position shown in this figure, and when forming a magenta toner image, the developing unit 726 is rotated around the axis P in the figure and exposed to light. body 715
The developing sleeve 731 in the magenta developing device is in contact with the
Place M. Cyan and black development work in the same way.

Further, 716 is a transfer drum that transfers the toner image formed on the photosensitive drum 715 onto paper, 7l9 is an actuator plate for detecting the moving position of the transfer drum 716, and 720 is adjacent to this actuator plate 719. 725 is a transfer drum cleaner, 727 is a paper press roller, 728 is a static eliminator, and 729 is a transfer charger. These members 71
9, 720, 725, 727, 729 are transfer rollers 7
It is arranged around 16.

On the other hand, 735 and 736 are paper feed cassettes that store paper (paper sheets), and 737 and 738 are cassettes 735 and 738, respectively.
Paper feed rollers that feed paper from 736, 739, 740
, 741 are timing rollers that take the timing of paper feeding and conveyance, and the paper fed and conveyed via these is guided by a paper guide 749 and wound around the transfer drum 716 while its leading edge is carried by a gripper (to be described later). Shift to image formation process.

Further, 550 is a drum rotation motor, and the photosensitive drum 7
15 and a transfer drum 716 are rotated in synchronization. 750 is a peeling claw that removes the paper from the transfer drum 716 after the image forming process is completed, 742 is a conveyor belt that conveys the removed paper, and 743 is a conveyor belt that is conveyed by the conveyor belt 742. The image fixing section 743 has a pair of heat and pressure rollers 744 and 745.

The image processing circuit according to the present invention will be described in detail with reference to FIG. 2 and subsequent figures. This circuit exposes a full-color original to an illumination source such as a halogen lamp or fluorescent lamp (not shown), captures a reflected color image with a color image sensor such as a COD, and sends the obtained analog image signal to an A/D converter. A color image copying device that processes and processes the digitized full-color image signal and outputs it to a thermal transfer type color printer, inkjet color printer, laser beam color printer, etc. (not shown) to obtain a color image, or digitizes it in advance. Applicable to color image output devices, etc. that input color image signals from computers, other color image reading devices, color image transmitting devices, etc., perform processing such as compositing, and output them to the color printer mentioned above. It is.

The original is first irradiated by an exposure lamp (not shown), and the reflected light is separated into colors for each image by a color reading sensor 500a and read, and amplified to a predetermined level by an amplifier circuit 50a. 533a is a CCD driver that supplies pulse signals for driving the color reading sensor, and the necessary pulse source is generated by a system control pulse generator 534a.

FIG. 3 shows the color reading sensor and drive pulses. Figure 3(a) shows the color reading sensor used in this example, which reads by dividing the main scanning direction into five (63
．． Assuming 5μm as one pixel (4aot/inch (hereinafter referred to as dpi)), 1024 pixels, that is, 1 pixel as shown in the figure, are divided into 3 by G, B, and R in the main scanning direction, so a total of 1024X3 = 3072 effective pixels. The number of pixels is sufficient. On the other hand, each of the chips 58 to 62 is formed on the same ceramic substrate, and the chips 58 to 62 are formed on the same ceramic substrate. 3. 5th (58a
, 60a, 62a) are on the same line LA, 2, 4
The distance from LA is 4 lines (63.5, czmX4=2
54 μm) on the line LB, and scans in the direction of the arrow AL when reading the document.

1 out of each 5 CCDs, 3. The fifth one is for the drive pulse group ODRV118a, and the second and fourth are for the EDRV119a.
are driven independently and synchronously.

OOIA, 002A, OR included in ODRVI18a
EOIA, EO2A included in S and EDRV119a,
ERS are a charge transfer clock and a charge reset pulse within each sensor, respectively; l, 3. 5th and 2.
Due to mutual interference with the fourth and noise limitations, all are generated synchronously so that there is no jitter between them. Therefore, these pulses are generated by one reference oscillation source OSC558a (second
Figure).

FIG. 4(a) shows a circuit block that generates the ODRV 118a, EDRV]]9a, and FIG. 4(b) shows a timing chart, which are included in the system control pulse generator 534a shown in FIG. Clock KO obtained by dividing the original clock CLKO generated from a single OSC558a
135a is a clock that generates reference signals SYNC2 and SYNC3 that determine the timing of generation of ODRV and EDRV, and SYNC2 and SYNC3 correspond to the set values of resettable counters 64a and 65a set by the signal line 22 connected to the CPU bus. The output timing is determined accordingly, and SYNC2 and SYNC3 are connected to the frequency divider 66a,
67a and drive pulse generators 68a and 69a are initialized. That is, the HSYN input to this block
Based on C118, all with one oscillation source OSC558a
Since it is generated by CLKO output from
Each pulse group of 18a and EDRV119a is
A synchronized signal without jitter is obtained, and signal disturbances due to interference between sensors can be prevented.

Here, the sensor drive pulses O obtained in synchronization with each other are
DRV118a is 1, 3. fifth sensor 58a,
60a, 62a, EDRVll9a is supplied to the second and fourth sensors 59a, 61a, and each sensor 58a,
59a, 60a, 61a. Video signals Vl-V5 are independently output from 62a in synchronization with the drive pulse, and are amplified to a predetermined voltage value by independent amplifier circuits 501-1 to 501-5 for each channel shown in FIG. ,
OOSl in FIG. 3(b) is passed through the coaxial cable 101a.
At the timing of 29a, V1, V3, and V5 are EOS134
At timing a(7), signals V2 and V4 are sent out and input to the video image processing circuit.

The color image signals obtained by dividing the original input into the video image processing circuit into 5 parts and reading them are processed into G (green) by the sample hold circuit S/H502a. It is separated into three colors: B (blue) and R (red).

Therefore, after S/H, 3×5=15 signals are processed.

The analog color image signals sampled and held for each color R, G, and B by the S/H circuit 502a are as follows:
The next stage A/D conversion circuit 503a digitizes each channel from 1 to 5, and each channel from 1 to 5 is independently connected in parallel.
Output to the next stage.

Now, in this embodiment, as described above, 4 lines (63.
5 μm x 4 = 254 μm) in the sub-scanning direction,
In addition, since the document is read using five staggered sensors divided into five areas in the main scanning direction, the reading positions of channels 2 and 4, which are being scanned in advance, and the remaining channels 1, 3, and 5 are shifted. Therefore, in order to connect this correctly, a shift correction circuit 504a equipped with memory for multiple lines is used to
We are correcting that discrepancy.

Next, using FIG. 5(a), the black correction/white correction circuit 506
The black correction operation in a will be explained. As shown in FIG. 5(b), when the amount of light input to the sensor is small, the black level outputs of channels 1 to 5 vary greatly between chips and between pixels. If this is output as is and an image is output, streaks and unevenness will occur in the data portion of the image. Therefore, it is necessary to correct the output variation in the black portion, and this correction is performed using a circuit as shown in FIG. 5(a). Prior to the original reading operation, the original scanning unit is moved to the position of a black plate having uniform density that is placed in a non-image area at the tip of the original table, the halogen is turned on, and a black level image signal is input to this circuit.

Regarding the blue signal BIN, selector 8 is used to store one line of this image data in black level RAM 78a.
Select A at 2a (■), close gate 80a (■), 8
Open 1a. That is, the data line is 151a-+152
a-+153a, and on the other hand, the address 155a of RAM78a is initialized with HSYNC, and VCLK
Output 154a of address counter 84a that counts
is outputted to the selector 83a so that the black level signal for l lines is inputted to R A M 7 8 a
(hereinafter referred to as black reference value import mode)
.

When reading an image, the RAM 78a is in a data read mode, and each line and each pixel are read out and input to the B input of the subtracter 79a via the data line 153a→157a path. That is, at this time, the gate 81a is closed (■
), 80a is open《(■). Further, the selector 86a has eight outputs. Therefore, the black correction circuit output! 56a is the black level data Df ((i), for example, in the case of a blue signal, BIN (i) DK (i)"B Ol.IT (
i) (referred to as black correction mode). Similarly, Green GI N + Red RIN is also 77aG, 7
Similar control is performed by 7aR.

In addition, the control lines of each selector gate for this control
, ■, ■, ■ are performed under CPU control by latch 85a assigned as I/O of CPU 22 (FIG. 2). Note that the selectors 82a, 83a, 86a are
RAM 7 by the CPU 22 by selecting
8a becomes accessible.

Next, white level correction (shading correction) in the black correction/white correction circuit 506a will be explained with reference to FIG. White level correction corrects sensitivity variations in the illumination system, optical system, and sensor based on white data obtained when the document scanning unit is moved to the position of a uniform white plate and irradiated. The basic circuit configuration is shown in FIG. 6(a). The basic circuit configuration is shown in Figure 5 (
This is the same as a), but the only difference is that the subtracter 79a performs the correction in the black correction, whereas the multiplier 79'a is used in the white correction, so a description of the same parts will be omitted.

CCD (500a
) is at the reading position (home position) of a uniform white plate, that is, before a copying operation or a reading operation, an exposure lamp (not shown) is turned on and image data of a uniform white level is stored in the correction RAM 78'a for one line. Store. For example, if it has an A4 longitudinal width in the main scanning direction, it is 16peI! /mm 16×297 m
m = 4 7 5 2 pixels, that is, at least RA
The capacity of M is 4752 bytes, and as shown in FIG. 6(b), the i-th pixel white board data Wi (i=1 to 4752)
Then, data for the white plate for each pixel is stored in the RAM 78'a as shown in FIG. 6(c).

On the other hand, for Wi, the read value Di of the normal image of the i-th pixel is corrected data DO=DiXFFH/Wi
It should be. Therefore, from the CPU 22, the latch 85
Gate 80'a for 'a■',■',■',■'
, 81' a, and selector 82' a,
83'a and 86'a are output so that B is selected, and RAM7B'a is made accessible to the CPU.

Next, in the procedure shown in FIG. 6(d), the CPU 22 performs FFH/Wo for the first pixel Wo, FF/W for W, .
The data is replaced by sequential calculations. After completing the blue component of the color component image (Step B in Fig. 6(d)), similarly, the green component (Step G) and the red component (Step
pR), and then input original image data Di
Gate 80'a is open (■') and gate 81'a is closed (■') so that Do=DiXFF H/Wi is output for
), selectors 83'a and 86'a select A, and coefficient data FFH read from RAM 78'a.
/Wi passes through signal lines 153a to 157a, is multiplied by the original image data 151a input from one side, and is output.

As described above, the black level and white level are corrected based on various factors such as the black level sensitivity of the image input system, the dark current variation of the CCD, the sensitivity variation between each sensor, the optical system light amount variation, and the white level sensitivity. Image data B O that has been uniformly corrected for each color, both white and black, in the scanning direction.
LJT 101, G OIJT 102+Rouy
103 is obtained. The white and black level-corrected color separation image data obtained here are processed by detecting pixels on the image having a specific color density or a specific color ratio according to instructions from an operation unit (not shown). The data is sent to a color conversion circuit B which converts the data into another color density or color ratio specified by the unit.

Color Conversion> FIG. 7 is a block diagram of color conversion (gradation color conversion and density color conversion). The circuit in FIG. 7 uses an 8-bit color separation signal R IN
A color detection unit 5b. determines an arbitrary color set in the register 6b by the CPU 20 for IG INI B IN (lb to 3b). Area signal Ar4b, ? for performing color detection and color conversion for multiple locations. A line memory 10b that performs a process of spreading a signal indicating "a specific color" (hereinafter referred to as a hit signal) outputted by the color detection section in the main scanning and sub-scanning directions (in the example of FIG. 7, only the sub-scanning direction).
~llb, OR game}12b, expanded hit signal 3
4b and non-rectangular signals (including rectangular) Color conversion enable signal 33b1 generated from BHi 27b Enable signal 33b and input color separation data (R IN + G IN.B
IN lb~3b), line memory 13b~16b1 delay circuit 1 for synchronizing area signal Ar4
7b to 20b1 Enable signal 33b1 Synchronized color separation data (R+N, GIN, BIN' 2
lb~23b), area signal Ar' 24b and CP
The color conversion unit 25b performs color conversion based on the color data after color conversion set in the register 26b by U20.
OLIT I B OIJT 28b-30b),
Hit signal H output in synchronization with ROUT + GOUT + BOLJT. Consists of lJ■3lb.

Next, we will outline the algorithms for gradation color determination and gradation color conversion. Here, gradation color judgment and gradation color conversion mean that when performing color judgment and color conversion, color conversion is performed by saving density values for colors of the same hue. The purpose is to perform color conversion.

It is known that for the same color (a certain hue), for example, a red signal R, a green signal G, and a blue signal B have the same ratio l,X.

Then, data M1 of one of the colors to be converted (here, l;! maximum value color, hereinafter referred to as principal color) is selected, and the ratio between it and the data of the other two colors is determined. For example, for input data R+, G+, B+, M, X γ
,≦R+≦M, X γ2 However, αh β,, γ1
≦1 α2・β2, γ2≧1 A pixel that is satisfied is determined to be a pixel to be color-converted.

Furthermore, data after color conversion (R,,,G2,B2) is also data M2 of the main color (maximum value color here).
Find the ratio between this and the data of the other two colors.

For example, when G2 is the main color, it is M2-62, and for the main color M of input data, if the data is a color conversion pixel, if it is not a color conversion pixel, then (R+, G+, B+) is output.

As a result, all parts of the same hue with gradation are detected,
It becomes possible to output color conversion data according to gradation.

FIG. 8 is a block diagram showing an example of a color determination circuit. This part is a part that detects pixels to be color-converted.

In this figure, 50b is R, N bl, G, N b2
, BIN b3 is a smoothing section that smooths the input data, and 5lb is a selector 52bR, 52b, 52b that selects one of the outputs (primary color) of the smoothing section.
B is the output of selector 5lb and the fixed value R. ＋GORB
Selector for selecting one of o, 54bR, 54bo, 5
4b8 is an OR gate, 63b, 64bR, 64bo, 6
4b8 are selectors 5lb, 52bR, 52b based on area signals ArlO, Ar20, respectively. ,52bB
Selector for setting the select signal to 56bR
, 56bo, 56b8 and 57bRl57bG, 57
b8 is a multiplier that calculates the upper and lower limits of each.

Further, the upper limit ratio registers 58b R, 58b o, 58b 8 and the lower limit ratio registers 59b R, 59b , 59 set by the CPU 20
b 8 can each set data for color detection for a plurality of areas based on the area signal Ar 30.

Here, ArlO, Ar20, and Ar30 are signals created based on Ar4b in Fig. 7, and each has the required number of stages of D.
Contains F/F. Also, 6lb is an AND gate, 62
b is an OR gate, and 67b is a register.

Next, we will explain the actual movement. R, Nbl, G, N
One of the data R', G', B' obtained by smoothing b2, B, N b3, respectively, is sent to the CPU2.
The selector 5lb is set by the select signal S1 set to 0.
Select to select the main color data. Here, C.P.
U20 sets different data A and B in registers 65b and 66b, and selector 63b selects either A or B according to the ArlO signal and inputs it to selector 5lb as an SI signal.

In this way, prepare two registers, 65b and 66b,
Input different data to A and B of selector 63b,
With the configuration in which the area signal ArlO selects one of them, separate color detection can be performed for a plurality of areas. This area signal ArlO may be a signal for not only a rectangular area but also a non-rectangular area.

In the next selectors 52bR, 52b, 52b8,
R set by the CPU 20. Either +GO+BO or the main color data selected by the selector 5lb is selected by a selection signal generated by the outputs 53ba to 53bc of the decoder 53b and the fixed color mode signal S2. In addition, selectors 64bR, 64bG,
By selecting either A or H according to the area signal A r20, the sensor 64b8 can detect different colors for a plurality of areas, as in the case of the selector 63b. Here, RO + Go
+Bo is selected when the main color is in conventional color conversion (fixed color mode) and gradation color determination, and is selected when the main color data is a color other than the main color in gradation color conversion.

Note that the operator can freely select between fixed color determination and gradation color determination from the operation section. Alternatively, it is also possible to change it by software using color data (color data before color conversion) input from an input device such as a digitizer.

These selectors 52bR, 52bo, 52b
From the output of B and the upper limit ratio registers 58bR, 58b, 58b and lower limit ratio registers 59bR, 59bo, 59b8 set by the CPU 20, the upper limit value and lower limit value of R'G' and B' are calculated by the multiplier. 56bR, 56b,, 56b8 and 57b
R, 57b, 57b8 and set as upper and lower limit values in window comparators 60bR, 60b, 60b8.

Window comparator 60bR, 60b,, 60b8
The AND gate 6lb determines whether the data of the main color falls within a certain range and the two colors other than the main color fall within a certain range. The register 67b can set "1" regardless of the determination signal by the enable signal 68b of the determination section. In that case, the color to be converted exists in the portion marked with "l".

The above configuration enables fixed color determination or gradation color determination for a plurality of areas.

FIG. 9 is a block diagram of an example of a color conversion circuit.

? If the signal is color-converted by the circuit based on the output 7b of the color determining section 5b, then the original signal is selected.

In FIG. 9, the color conversion unit 25b includes a selector lllb, registers 1t2bR, . 112bR2,
112bo,, 112bG2, ll2b8
,, l12b8■, multiplier 113bR, 113b,
, 113b8, selector l14bR, l14bo,
114b8, selector 115bR, l15bo, 115
b8, AND gate 32b1 Figure 7 area signal Ar'
Ar50, Ar60, generated based on 24
The data set by the CPU 20 by Ar70 is transferred to the selector lllb, multipliers 113bR, 113ba, l.
13bB, selector ll4bR, l14b, 114b
Selector 117b, ll2bR, 1 set to B
12b,, 112bB, 116bR, l16b,
, l16b8, and a delay circuit 118b.

Next, we will explain the actual movement.

The selector lllb receives the input signal RI N 2lb,G
, N' 22b, B, N' 23h (principal color)? The selection is made according to the selection signal S5. Here, the signal S5 indicates that the area signal Ar40 selects the selector 117b as A,
This occurs by selecting either H. In this way, color conversion processing for multiple areas becomes possible.

The signal selected by selector Illb is sent to multiplier +13
Multiplication with the register value set by the CPU 20 is performed in bR, 113bo, and ll3b8.

Here again, the area signal Ar50 has two register values 112
bR, -1!2bR,, l12b,, - 11
By selecting 2b, 2, 112b8, ·ll2b8■ by selectors l12bR, 112bo, l12b8, respectively, different color conversion processing can be performed for a plurality of areas.

Next selectors l14bR, 1145o, ll4
In b8, the result of multiplication and the two fixed values Ro' set by the CPU 20 ・Ro Go - Go'Bo'
-Bo, one of the fixed values selected by the selectors ll6bR, 116b0, 116b8 by the area signal Ar 70 is selected by the mode signal S6. Is this also a mode? The signal S6 is selected by the area signal Ar60 in the same manner as S5.

Finally, selector 115bR, ll5b, 115b8 uses select signal S8 to select RINGIN r.
BIN (RIN + GIN + BIN delayed and timing adjusted) and selector 114bR, l1
Either the output of 4b6 or 114bB is selected, and R
Output as OLIT+GOUT+BOUT. Also hit signal H. U. Also R. U T +COU■+
Output in synchronization with BOLIT.

Here, the selector signal S8 is a delay product obtained by ANDing the color determination result 34b and the color conversion enable signal BHi34b. If a non-rectangular enable signal such as the dotted line in FIG. 10 is input as the BHi signal, color conversion processing can be performed on a non-rectangular area. In this case, the area signal is an area like the one-dot chain line, that is, the top left (Figure 10a), the top right (Figure 10 b), the bottom left (C), and the bottom left determined from the dotted lines. (Fig. 10d). Also, non-rectangular area belief? BHi is input from an input device such as a digitizer.

When performing color conversion using this non-rectangular enable signal,
Since the enabled area can be specified along the boundary of the area to be converted, the threshold for color detection can be expanded compared to conventional color conversion using rectangles. Therefore, the detection ability is further improved, and an output image subjected to gradation color conversion with high accuracy can be obtained.

From the above, color conversion with brightness according to the main color of the color judgment unit 5b (for example, when converting red to blue, light red is converted to light blue and dark red is converted to dark blue) or fixed value color conversion You can freely perform any of the following for multiple areas.

Furthermore, as will be described later, the hit signal H. Mosaic processing only on specific color areas (non-rectangle or rectangle) based on U■,
Texturing processing, trimming processing, masking processing, etc. can be performed.

Then, as shown in FIG. 2, the output 103 of the color conversion circuit B,
104 and 105 are a logarithmic conversion circuit for converting image data proportional to reflectance into density data; System and cables 135
, 136, 137 to an external device interface M for communicating data with external devices.

Next, the color image data proportional to the input light amount is
The signal is input to a logarithmic conversion circuit C (FIG. 2) which performs processing to match the luminosity characteristics of the human eye.

Here, the image source is converted as much as possible to white = 00H and black = FFH, and is further input to the image reading sensor,
For example, a normal reflective original, a transparent original such as a film projector, and even the same transparent original have different gamma characteristics depending on the sensitivity and exposure state of the negative film, positive film, or film.
As shown in b), there are multiple LUTs (look-up tables) for logarithmic conversion, which are used depending on the purpose. Switching is done using signal line 1 go, l gl, l g
2, and is performed by inputting an instruction from an operation unit or the like as an I/O board of the CPU 22 (FIG. 2). Here, the data output for each B, G, and R corresponds to the density value of the output image, and the data output for each B (blue), G (green), and R (red) signal is Y (yellow). Since this corresponds to the toner amounts of M (magenta) and C (cyan), subsequent image data will be associated with yellow, magenta, and cyan.

Next, each color component image data from the original image obtained by logarithmic conversion, that is, yellow component and magenta component. The color correction circuit D performs color correction on the cyan component as described below. As shown in Fig. 13, the spectral characteristics of the color separation filters arranged for each pixel in the color reading sensor have unnecessary transmission areas such as the shaded areas, and on the other hand, for example, the color transferred to the transfer paper Toner (Y, M, C)
It is also well known that the fluorophore also has unnecessary absorption components as shown in Figure 14. Therefore, each color component image data Yi, Mi,
Masking correction is well known in which color correction is performed by calculating a linear equation for each color with respect to Ci. Furthermore, by Yi, Mi, and Ci, M
in (Yi, Mi, Ci) (Yi, Mi,
The minimum value of Ci) is calculated, and this is used as a smear (black), and then black toner is added (smear removal), and undercolor removal (U
CR) operations are also commonly performed. FIG. 12(a) shows the circuit configuration of a color correction circuit D that performs masking, smearing, and UCR. The characteristics of this configuration are: ■ It has two masking matrices and can be switched at high speed with one signal line "I/O". ■ One signal line "I/O" with and without UCR /0", it can be switched at high speed. (2) It has two circuits that determine the amount of smear, and it can be switched at high speed with "I/O".

First, prior to image reading, a desired first matrix coefficient MI and second matrix coefficient M2 are set via a bus connected to the CPU 22. In this example, M, is stored in the registers 87d to 95d, and M2 is stored in the registers 96d to 104.
It is set to d.

Also, llld~122d, 135d, 131d, 13
6d is a selector, which selects A when the S terminal is "1" and selects B when the S terminal is "0". Therefore, when selecting matrix M, switching signal MAREA364 "1"
”, if matrix M2 is selected, it is set to “0”.

Further, l23d is a selector, and selection signals C0, C
, (366d), 367d), Figure 12(b)
) outputs a, b, and c are obtained based on the truth table of ).

Selection signal C. , C1 and C2 correspond to color signals to be output, for example Y. In the order of M, C, Bk (C2,
C,, C(+) = (0, 0. 0), (0
, 0, l), (o, l, 0), (1,
0. 0), and further as a monochrome signal (0, l,
1) Desired color correction by? Obtain the color signal. Now (Co, CIn C2) = (0, 0.
0), and MAREA="B", selector l 2
The outputs (a, b, c) of 3d have registers 87d
, 88d, 89d, therefore (aye, -b
Me, -Cc+) is output. On the other hand, the input signal Yi,
Min (Yi, Mi, C
i) The black component signal 374d calculated as =k is 1
At step 37d, the signal undergoes a linear transformation such that Y=ax-b (a and b are constants), and is input to the B inputs of subtracters 124d, 125d, and 126d. In each subtractor 124d-126d, Y=Yi-(ak-b), M=M
i − (ak-b), C=Ci − (ak-b)
is calculated, and multipliers 127d and 1 for masking calculation are connected via signal lines 377d, 378d, and 379d.
It is input to 28d and 129d.

Multipliers 127d, 128d, and 129d each have (a Yl, - b Ml
, −C c+ ), and the B input has the above-mentioned (Yi−
(ak-b), Mi- (ak-b), Ci one (a
k-b)) = (Yi, Mi, Ci) is input, so as is clear from the figure, the output is D. For U■, Y under the condition of C2=0 (Y or M or C). U1=? iX (aye)+MiX (-bM+)
10Cix (-Cc.) is obtained, and yellow image data that has been subjected to masking color correction and undercolor removal processing is obtained. Similarly, M■Uy = Yix (-ay2) + MiX (-bv2)
+CiX(-CC2)C■ Uy =YiX(-ay3
)+MiX(-bv3)+CiX(-CC3) is D.

U. is output to. Color selection is controlled by the CPU 22 according to the table in FIG. 12(b) using (Co, C+, C2) according to the order of output to the color printer. Registers 105d to 107d and 108d to 110d are registers for monochrome image formation, and based on the same principle as the masking color correction described above, MONO=J Yi+
It is obtained by weighted addition for each color using Il1 Mi + mICi.

Further, when outputting Bk, C2 (368) is input as a switching signal to the selector 131d, so that C2=11, so the signal undergoes a linear conversion such that Y=cx-d in the primary converter 133d, and is output from the selector 131d. Also, Bk
MJllO is a black component signal output to the outline of a black character based on the output of a character image area separation circuit (2) to be described later. Color switching signal C.

C, , C2' 366 to 368 are the CPU bus 22
MARE is set from the output boat 501 connected to
A364 is output from the area signal generation circuit 364.

The gate circuits 150d to 153d output a signal C when DHi-“L” is determined by a non-rectangular area signal DHil22 read from a binary memory circuit (bitmap memory) L537, which will be described later. , C1 1 C2 = “l, 1.
0'' and automatically outputs data for m o n o images.

Character image area separation circuit Next, the character image area separation circuit l uses the read image data to determine whether the image data is a character or an image, and whether it is chromatic or achromatic. This is a circuit that determines whether The flow of the process will be explained using FIG. 15.

Red (R) 103, green (G) 104, blue (B) input from color conversion B to character image area separation circuit ■
) 105 is a minimum value detection circuit M, N (R, G,
B) 1011 and maximum value detection circuit Max (R,
G, B) is input to 102■. In each block, the maximum value and minimum value are selected from the three types of input luminance signals R, G, and B. The difference between the selected signals is determined by a subtraction circuit 104. Unless the difference is large, that is, the input R, G, and B are not uniform, the signal should be close to an achromatic color indicating black and white.
Indicates that it is a chromatic color that is biased towards some color. Naturally, if this value is small, it means that the R, G, and B signals are at approximately the same level, and it can be seen that the signal is an achromatic signal and not a signal that is biased towards any color. This difference signal is output to the delay circuit Q as a gray signal GR124. In addition, this difference is stored in register 11 by the CPU.
11 arbitrarily set threshold and comparator 112I.
The comparison result is output to the delay circuit Q as a gray determination signal GRBil26. These GR125,G
After the signal of RBil26 is matched in phase with other signals in a delay circuit Q, it is input to a character image correction circuit E, which will be described later, and is used as a processing determination signal.

The minimum value signal obtained by M, N (R, G, B) IOII is also input to the edge emphasis circuit 1031. The edge emphasis circuit performs the following calculation using the front and rear pixel data in the main scanning direction. Edge enhancement is performed.

DOLIT: Image data Di after edge enhancement
: i-th pixel data Note that edge enhancement is not necessarily limited to the above method, and other known techniques may be used. The image signal edge-enhanced in the main scanning direction is then averaged within 5×5 and 3×3 windows by calculating the average value of 5×5 average of 109I and 3×3 average of 1
It will be held at 10I. Line memories 1051-108I are delay memories in the sub-scanning direction for performing averaging processing. The 5×5 average value calculated in 5×5 average 1091 is then applied to an offset value independently set in an offset section connected to CPUBUS (also not shown) and adders 1151, 1191 . It is added at 1241. The added 5×5 average value is Limiter 1 1131,
It is input to limiter 2 118I and limiter 3 1231. Each limiter is connected to a CPU bus (not shown), and is configured so that a limiter value can be set independently. If the 5×5 average value is larger than the set limiter value, the output is clipped at the limiter value. The output signal from each limiter is sent to a comparator l.
1161, comparator 2 1211, and comparator 3 1261. First, comparator 1
At 1161, the output signal of the limiter lll3I and the output from the 3x3 average 1101 are compared. The compared output of the comparator 1 116I is input to a delay circuit 1171 in order to match the phase with an output signal from a halftone area determination circuit 122I, which will be described later. This binarized signal is destroyed by MTF at a certain concentration or higher,
In addition, in order to prevent skipping, binarization is performed using the average value, and in order to prevent halftone dots in the halftone image from being detected by binarization,
In order to cut high frequency components of the halftone image, it is passed through a 3×3 low-pass filter. Next, converter 2 (
The output signal of 1211) is binarized with through image data in order to detect high frequency components of the image so that it can be discriminated by a halftone dot area discriminating circuit 1221 in the subsequent stage. Since a halftone image is composed of a collection of dots, the halftone dot area determination circuit 1221 detects dots by confirming dots from the direction of the edge and counting the number of dots around the edge. A detailed explanation of the halftone area determination circuit 1221 will be omitted since it is not the gist of this patent.

129
After taking the value 1, the false determination removal circuit 130I removes the false determination and outputs it to the AND gate 1321.

In this erroneous judgment removal circuit 130I, taking advantage of the characteristics that characters and the like are thin and images have a wide area, first, the image area of the binarized signal is narrowed, and an isolated image area is taken. Specifically, for the center pixel Xi', the peripheral 1 mm
When even one pixel other than the image exists within the corner area, the center pixel is determined to be outside the image. After removing the image area of the isolated point in this way, thickening processing is performed to restore the thin image area to its original size. Similarly, the output of the halftone dot discriminating circuit 1221 is directly input to the erroneous judgment removal circuit 1311, where thinning processing and thickening processing are performed. Here, the mask size for the thinning process is the same as the mask size for the fattening process. There is. Specifically, both the false judgment removal circuits 130I and 1311 are thinned with a 17x17 pixel mask, further thinned with a 5x5 mask, and then thickened with a 34x34 pixel mask. There is. Output signal SC from misjudgment removal circuit 1311
The RN signal 127 is a discrimination signal for smoothing only the halftone dot determination section in a character image correction circuit E, which will be described later, to prevent moiré in the read image.

Next, the output signal from the comparator 3 1261 is used to extract the outline of the input image signal in order to sharpen the characters at a later stage. The extraction method is to perform thinning processing and fattening processing on the binarized comparator 3 126 summer output in 5 x 5 blocks, and to obtain the difference area between the fattened signal and the thinned signal. Make it an outline. The contour signal extracted by such a method must match the phase with the mask signal output from the false determination removal circuit 1301. After passing through the delay circuit 128I, the contour signal is determined by the AND gate 1321 to be a mask signal and an image. The contour signal in the part where the characters are printed is masked, and only the contour signal in the original character part is output. The output from the AND game} 1321 is then output to the contour regeneration unit 1331.

Contour regeneration unit> The contour regeneration unit 1331 processes pixels that are not determined to be character contours to become character contours based on the information of surrounding pixels, and as a result, converts MjArl24 into character image correction circuit E. and perform the processing described below.

Specifically, as shown in Figure 16, bold letters ((a) in the same figure)
, the character determination unit determines the dotted line part in (b) as a character and performs the processing described below.
Regarding C)), the character part becomes as shown in the dotted line part in FIG. 10(d), and if the processing described below is performed, it may become unsightly due to misjudgment. In order to prevent this, processing is performed to treat parts that are not determined as characters based on surrounding information.

Specifically, by making the diagonal line part the text part, the text becomes as shown in the dotted line part (e) in the same figure, which reduces misjudgments even for characters that are so thin that they are difficult to detect, and improves image quality. Connect.

FIG. 17 is a diagram showing how surrounding information is used to regenerate a pixel of interest into a character portion.

(a) to (d) are 3 x 3 blocks, with the pixel of interest as the center, and both vertical, horizontal, and diagonal text portions (S, S2 are both "l")
When , the pixel of interest is set as a character portion regardless of the information of the pixel of interest. On the other hand, (e) to (h) are 5×5 blocks, with one pixel centered around the pixel of interest, and both vertically, horizontally, and diagonally are character parts (S, S2 are "l"), regardless of the information of the pixel of interest. is the character part. Like this 2
The structure of tiered blocks (multiple types of blocks) makes it possible to handle a wide range of errors.

FIGS. 18 and 19 are circuits for realizing the process shown in FIG. 17. The circuits shown in FIGS. 18 and 19 include line memories 1641 to 1677, and D F / F 104 i-1 26 i for obtaining information around the pixel of interest.
, 17(a) to 17(h) and an OR gate 154i.

Figure 17 (
The information of S, , S2 in a) to (h) is extracted. Furthermore, 146iN153i is a register corresponding to each process of (a) to (h) 5 5 i = 1
6 2 i can independently control enable and disable.

AND circuit 146i=153i and FIG. 17(a) ~(
The correspondence relationship in h) is as follows.

FIG. 20 shows W1(
This is a timing chart of RE (ENI) and RE (EN2). This is done so that ENI and EN2 are output at the same timing when the image is enlarged to the same size, or when the image is enlarged (for example, from 200% to 300%), the number W is written once in two thinned lines.

This expands the size of FIGS. 17(a) to (h).

This is because when enlarging, the information that enters here is an image enlarged only in the sub-scanning direction, so by increasing the size of (a) to (h), processing is performed using the same size image even when enlarging. I'm going to

Character Image Correction Circuit> The character image correction circuit E performs the following processing on black characters, color characters, halftone images, and halftone images, respectively, based on the determination signal generated by the character image area separation circuit I described above.

[Processing 1] Processing regarding black characters (1-1) Signal Bk obtained by black-mark extraction as video
Using MjL12 (1-2) Y, M, C data are multivalued achromatic chromaticity signals GR
125 If << performs subtraction according to the set value. On the other hand, Bk
The data is a multivalued achromatic chromaticity signal GRl25. If << is added according to the set value (1-3) Edge emphasis is performed (1-4) Black characters are printed out at 400 lines (400 dpi) (1-5 ) Perform color residual removal processing [Processing 2] Processing related to colored characters (2-1) Perform edge emphasis (2-2) Color characters are 400 lines (400 dpi) I
I: Print out [Process 3] Processing related to halftone images (3-13 Smoothing to prevent moiré (main scan
[Processing 4] Processing related to halftone images (4-13 Smoothing (2 pixels each in the raw scanning direction) or Through can be selected.

Next, a circuit that performs the above processing will be explained.

FIG. 21 is a block diagram of the character image correction section E.

The circuit of FIG. 21 uses the video input signal 111 or BkM
j 112, an AND gate 6e that generates a signal to control the selector, a block 16e that performs residual color removal processing (to be described later), an AND gate 16e that generates an enable signal for the same processing, a GR signal 125 and an I/ A multiplier 9e that multiplies the set value 10e of the O port.
, a selector Ile that selects the multiplication result lOe or the set value 7e of the I/O port, a multiplier 15e, X that multiplies the output 13e of the selector 6e and the output 14e of lle.
OR gate 20e, AND gate} 22e, adder/subtractor 24e, line memories 26e, 28e for delaying line data, edge emphasis block 30e, smoothing block 31e, selector 33e for selecting through data or smoothing data, control signal for the selector a delay circuit 32e for synchronization of the selector 42e for selecting the edge emphasis result or the smoothing result, a delay circuit 36e for synchronization of the control signal of the selector, and an OR game}39e, AND
Gate 41e, 400 lines (dpi) for character determination section
Inverter circuit 4 for outputting a signal (“L” output)
4e, an AND circuit 46e, an OR circuit 48e, and a delay circuit 43e for synchronizing the video output 113 and the LCHG 49e. Also, character image correction section E
is connected to the CPU bus 22 via the I/O port le.

Below [1] Color residual removal processing that removes the color signal remaining around the edges of the black text area, subtracting a certain proportion from the Y, M, and C data of the black text area determination section, and subtracting a certain proportion from the Bk data. [2] Edge enhancement for the text part, smoothing for the halftone judgment part, and part where through data is selected for other gradation images, [3] L for the text part.
The process will be divided into three parts, each of which will be explained: the part where the CHG signal is set to 'L' (printed at 400 dpi).

(1) Remaining color removal processing and addition/subtraction processing In this case, the processing is performed on the area where both the signal GRBil 26 indicating that it is an achromatic color and the signal MjAR 124 indicating that it is a text area are active, that is, the edge area of the black character and its surrounding area, The Y, M, and C components protruding from the edges of black characters are removed, and the edges are filled in.

Next, a detailed explanation of the operation will be given.

This process is subject to character part determination (MjARl24="l"
), this is performed only when the character is black (GRBil26-“1”) to the color mode (DHil22-“O”). Therefore, ND (black and white) mode (DHi-“
1”) and color characters (GRBi="O").

When scanning a document for recording color Y, M, or C, the video manual 111 selects it with the selector 6e (I/O-
6 (set to “O” in 5e)). l 5e, 20
e, 22a, and 17e generate data to be subtracted from video 8e.

For example, if '0'' is set in I/O-312e, selector output data 13e
Multiplying by the value set in I/O-17e is performed by multiplier 1.
It takes place in 5e. Here, data 18e that is 1 times larger than 13e is generated. By setting 1 to registers 9e and 25e, the two's complement data of 18e becomes 17e,
Generated at 20e and 22e. Finally, adder/subtractor 24
Since addition 23e of 8e and 23e in e is a two's complement number, 17e-8e is actually subtracted and output from 25e.

1/0-312 When "l" is set in e, B data is selected in selector lie.

At this time, the value set in I/O-210e is applied to the multi-valued achromatic color signal GR125 (a signal that takes a large value if it is close to an achromatic color) generated by the character image area separation circuit ■ at 9e. The multiplied value is used as the multiplier of 13e. When this mode is used, the coefficients can be changed independently for each of the colors Y, M, and C, and the amount of subtraction can be changed depending on the achromatic degree.

When scanning recording color Bk, selector 6e selects BkMj1.
12 selected (“1” for I/O-65e
set). 15e, 20e, 22e, and 17e generate data to be added to video 17e. Above Y,
The difference from M and C is that "O" is set in I/O-4 and 9e, so 23e=8e, Ci=0
Therefore, 17e+8e is output from 25e. coefficient 1
The method of generating 4e is the same as that for Y, M, and C. Also,
In the mode in which "1" is set in the I/O-312e, the coefficient changes depending on the degree of achromatic color. Specifically, when the achromaticity is large, the amount of addition is large, and when it is small, it is small.

This process is illustrated in Figure 22. The shaded area of the black letter N is enlarged in (a). (c).

For Y, M, and C data, subtraction from the video is performed where the character signal part is "l" (Figure (b)), and for Bk data, where the character signal part is "l". is added to the video ((d) in the same figure). In this figure, 13e=l
8e, that is, the Y, M, and C data of the character portion are 0, and the Bk data is twice that of the video.

Through this processing, the outline of black characters is printed in almost a single black color, but the Y, M, and C data outside the outline signal (see Figure 22 (b)
) The * mark shown in ) remains around the letters as residual color, making it unsightly.

The color removal process removes the remaining color.

This processing extends to the area of the text area,
In addition, processing to take the minimum value of 3 or 5 pixels before and after pixels where the video data 13e is smaller than the comparison value set by the CPU, that is, outside the character area, where there is a possibility of color remaining. It is.

Next, the explanation will be supplemented using a circuit.

Figure 23 shows a character area expansion circuit that works to expand the character area.
ND gate 69e, 71e, 73e, 75e,
It is composed of an OR gate 77e.

All I/O boats 70e, 72e, 74e, 76e
When MjArl24 is set to "l", when the signal expanded by two pixels in the front and back in the main scanning direction is I/O port 70e, 75e "0'", 71e, 73e"l1, main scanning The signal expanded by l pixels forward and backward in the direction is Sig2
It is output from 18e.

Next, the remaining color removal processing circuit 16e will be explained.

FIG. 24 is a circuit diagram of residual color removal processing.

In FIG. 24, 57e is a 3-pixel min select circuit that selects the minimum value of a total of 3 pixels, including the pixel of interest and 1 pixels before and after it, for the input signal 13e, and 58e is the input signal 13
For e, select the maximum value of a total of five pixels, including the pixel of interest and two pixels before and after it. A 5-pixel min select circuit 55e is a comparator that compares the magnitude of the input signal 13e and the I/O-18 (54e), and outputs l when 54e is greater. 61e, 62e are selectors, 53e, 53'
e is an OR gate, and 63e is a NAND gate.

In the above configuration, the selector 60e selects 3 pixels min or 5 pixels based on the value of I/O-19 from the CPU bus.
Select pixel min. The effect of color residual removal becomes thicker with 5 pixels min. This can be selected by manual setting by the operator or automatic setting by the CPU.

The selector 62e is configured so that the output of the NAND gate 63e is “0”.
”, that is, the comparator 55e determines that the video data 13e is smaller than the register value 54e, and it is within the range where the character part signal is expanded, and if 17'e is 1, the A side is selected, otherwise the video data 13e is The B side is selected. (However, at this time, the registers 52e and 64e are "l",
The register 52'e is 'o'. When the B side is selected, through data is output as 8e.

The EICON 50e can be used in place of the comparator 55e when, for example, a binary luminance signal is input.

FIG. 25 shows the area where the above two processes have been applied. FIG. 25(a) shows the black character N, and FIG. 25(b) shows the area determined as a character in the Y, M, and C data, which is the density data of the shaded area, that is, the character determination part (-jf2,
Ao 3, Ao 6, Ao 7) are reduced to 0 by subtraction processing, Ku1,
Screen 4 is +1←%0 due to color residue removal processing,
←65, resulting in 0, and <c> in Figure 25 is obtained.

On the other hand, for B and data as shown in Figure 25(d),
Only addition processing is performed in the character determination section (Ku 8, Tatami 9, Kumo 10, Ku 11), resulting in an output with a black ring as shown in FIG. 25.

Note that no changes are made to the colored characters, as shown in FIG. 25(f).

[2] Edge Emphasis or Smoothing Process Here, processing is performed to output edge emphasis for the character determination section, smoothing for the halftone dot section, and outputting through for the others.

Character part→MjARl24 is “1”, so 25e,
3× generated from 3 line signals of 27e and 29e
The output of the edge emphasis 30e of No. 3 is selected by the selector 42e and output from 43e. Note that the edge enhancement here is obtained from a matrix and calculation formula as shown in FIG.

Halftone part → SCRN35e is "1", M j A R 2
Since 1e is "0", the smoothing 31e applied to 27e is the selector 33e, 42
It is output at e. Note that smoothing is the 27th
As shown in the figure, when the pixel of interest is vN (V N 10V
This is a process of converting N+1)/2 into data of vN, that is, smoothing of two main scanning pixels. This prevents moiré that may occur in the halftone dot area.

Other→Other portions refers to processing for areas that are neither character portions (character outlines) nor halftone dot portions, specifically, midtone portions. At this time, MjAR124 and SCRN35e
Since both are "0", the data of 27e is output as is from the video output 43e.

When the characters are colored characters, the above two processes are not performed even in the character determination section.

In the embodiment, an example was shown in which color residual removal was performed only in the main scanning direction, but color residual removal processing may be performed in both the main scanning and sub-scanning directions.

[3] Text section 400 lines (dpi) output processing video output 1
LCHGI40 is output from 48e in synchronization with 13. Specifically, the inverted signal of MjARI24 is output in synchronization with 43e. In the case of a character part, LCHG=0, and in other parts, 200/400="l".

As a result, the character part determination part, specifically the character outline part, is 4
00 line (dpi), and the others are printed at 200 line (dpi).

Next, the character drawings. The image synthesis circuit F will be explained.

FIG. 28(a) is a block diagram of a circuit for processing and modifying images using binary signals in this apparatus. The color image data l38 inputted from the image data input section is inputted to the V input of the 3tol selector 45.

The other two A and H of the 3tol selector 45f contain the lower part (An) of the data read out from the memory 43f.
, B ll) Of 555f, A has An and B has B
n is latched by VCLK117 in latch 44f and input. Therefore, the output Y of the selector 45f
Select Jinriki X. , x l+ Jl,
Based on J2, either V, A, or H is output (
114).

In this embodiment, data xn is the top two data in memory.
This bit is a mode signal that determines processing and modification. 139 is a code signal output from the area signal generation circuit.
It is controlled to switch in synchronization with ll7, and the memory 43f
is entered as the address of

That is, for example, (x
to+ A10+ Boo) 1 (OL AIon B
29(b), the code signal 139 is written in synchronization with the scanning of the line l in the main scanning direction.
"10" from point P to point Q and "0" from point Q to point R.
is given, and between P and Q, data xIl = (0.
1) is read out, and at the same time (As+Bm) is (A,
. +81. ) is latched and output. 3
As shown in the truth table of the tol selector 45f in FIG. 28(c), (X,, Y, therefore Y has a constant A1. If Jl is "0", it means (1) that the input is Y, and therefore the input color image data is output as is to the output 114. In this way, for example, so-called tweezers character synthesis of a character portion having a value of (A+o) is realized for a color image of an apple as shown in FIG. 29(b). Similarly (X I+ Xo)
= (1.0), and use Jl in Figure 29 (C) for binary input.
When a signal like this is input, FIFO 47f ~ 49
f, and the circuit 46r (details in FIG. 28(b)),
A signal like J2 in the same figure is generated, and if the truth table in Figure 28(C) is followed, characters will be output with frames in the apple image as shown in the figure (outline or bag). letter).

Similarly, in FIG. 28(D), the rectangular area inside the apple is (
B. ), and the characters inside are output with a density of (A.). In the same figure (A), (X1, xo) = (
0, O), that is, any Jl, J2
Depending on the binary signal, there is a control that does nothing even with respect to changes in .

The signal with expanded width input to J2 is shown in Fig. 28(b).
According to , it is an expansion of 3×3 pixels, but it is easy to increase the size even further by adding a hardware circuit.

Also, CO and CI (366, 367) output from the I/O port 501 in FIG. 2 in association with the output colors (Y, M, C, Bk) to be printed are stored in the memory 4.
It is input to the lower 2 bits of the address of 3f, and therefore "0, O" 0 corresponds to the output of Y, M, C, Bk.
, l"l, 0", "l, l", so for example, when yellow (Y) is output, it changes as 0, 4, 8, 12, etc.
16...Address, magenta (M) is 1, 5, 9,
13, I7... address, cyan (C) is 2, 6,
10, 14. 18... Address, black (Bk)
) are 3, 7, 11, 15. 19...An address is selected. Therefore, according to an operation instruction on the operation panel, which will be described later, for example, x1 to x4 = "l, 1" (AI, A2, A3,
A4) = (α1, α2, α3, α4), (Bl, B2
, B3, B4) = (βl, β2, β3, β4)
For example, as shown in Figure 29 (D),
When the signal changes, the section where Jl is “LO” becomes (Y, M
, C, Bk) = (αl, α2, α3, α4), and when Jl is “Hi”, (Y, M,
C, Bk) = (βl, β2, β3.β4) The color is determined by the combination. In other words, the output color can be arbitrarily determined based on the memory contents. On the other hand, on the operation panel described later, Y. M
, C, and Bk are each adjusted or set in percent (%). That is, since each gradation has 8 bits, the numerical value is OO to 255, so a 1% fluctuation is a digital value of 2.55.

The setting value is (Y, M, C, Bk) = (y%, m%,
C%, k%), the numerical values to be set (that is, the numerical values written to memory) are (2.55Y.2.
55m, 2.55c, 2.55k), and in reality, an integer rounded off to the nearest whole number is written in a predetermined memory. Furthermore, if the adjustment mechanism is used to adjust in %, an addition of 2.55 Δ will be added to the change in Δ% (
It is sufficient to write the value obtained by a<<do> or subtraction (u<<do)> into the memory.

In the truth table in Fig. 28(c), the i column is an input/output table for characters, image gradation, and resolution switching signal LCHG149, and x,, XO+ Jl, J2 causes A or B to output Y. When it is output, it is "0", and when ■ is output to Y, the input is output as is. LCHG149 is a signal that switches the print density during printing, for example, when LCHG="O", for example, 400 dpi.
, LCHG-“l” prints at 200 dpi.

Therefore, when A or B is selected, LCHG=O means that the inner area of the synthesized characters is printed at 400 dpi, and the area other than the characters is printed at 200 dpi.
The text is controlled to maintain high resolution, sharp halftone areas, and high gradation, and is output smoothly. As mentioned above, this is why the LCHG 140 outputs the output from the character image correction circuit E based on MJAR, which is the output from the character/image separation circuit (2).

Image processing and editing circuit> Next: Image signal 1 after receiving color balance adjustment at P
15 and the gradation resolution switching signal LCHG141 are input to the image processing and editing circuit G. A rough schematic diagram of the image editing processing circuit G is shown in FIG.

Input image signal 115, gradation resolution switching signal LC
The HG 141 is first input to the texture processing section 101g. The texture processing section is roughly divided into a memory section 103g that stores texture patterns, memories RD and WR that control them, an address control section 104g, and an arithmetic circuit 105g that performs modulation processing on input image data according to the stored pattern. has been done. The image data processed by the texture processing section 101g is then subjected to scaling, mosaic, and taper processing section 1.
02g. The variable magnification, mosaic, and taper processing section 102g has double buffer memory 105g, 10
6g and a processing/control unit 107g, various processes are independently performed and output by the CPU.

Here, the texture processing section 101g and the scaling, mosaic, and taper processing section 102g receive G H i 1 (11
9) and GHi2 (+49) are configured so that texture processing and mosaic processing can be performed on independent areas.

Furthermore, the gradation resolution switching signal LCHG signal 141 input together with the image data 155 is processed in various processes while matching the phase with the image signal.

The image processing/editing circuit G will be explained in detail below.

<Texture processing section> Texture processing is a process of cyclically reading out a pattern written in memory and applying modulation to the video. For example, the image shown in FIG. It modulates the image in a pattern like this to generate an output image like that shown in FIG.

FIG. 32 is a diagram illustrating the texture processing circuit.

Below, modulation data 2 to texture memory 113g
18g writing section and 113g texture memory
216g of data and 215g of image data (
Texture processing) will be explained separately.

[Data writing unit to texture memory 113g] When writing data, masking, undercolor removal, and smudging are performed, and data is input from 201g. This data is selected by selector 202g. On the other hand, selector 20
8g, data 220g is selected and the memory 113
g and the enable signal of the driver 203g. The memory address is a vertical counter 212g that counts up in synchronization with the horizontal synchronization signal HSYNC, and a horizontal counter 21 that counts up in synchronization with the image clock, VCK! g, B is selected by the selector 210g, and inputted to the address of the memory 113g.

In this way, the density pattern of the input image is stored in the memory 11.
Written to 3g. Typically, this pattern is an input device,
For example, it is located and written using a digitizer.

[Writing data by CPU] CPU data is selected by the selector 202g.

On the other hand, A is selected by the selector 208g, and the memory 11
3g and the enable signal of the driver 203g. As the memory address, A is selected by the selector 210g and inputted to the address of the memory 113g. thus,
An arbitrary density pattern is written into memory.

[Calculation unit for texture memory 113g data 216g and image data 215g] This calculation is realized by a calculation unit 215g. This arithmetic unit here consists of a multiplier. Data 216g and 201 only where enable signal 128g is active
An operation with g is performed, and when the disable is enabled, the signal 201 becomes a through state.

Also, 300g and 301g are XOR and OR gates, respectively, and register 304 is a part that generates an enable signal using MJ signal 308g, that is, a character synthesis signal.
When g"1" 305g is set to "0" in the register, texture processing is applied to areas other than those containing composite character signals. On the other hand, register 304g"O"305g has "O"
When `` is set in the register, texture processing is applied only to the part that contains the composite character signal.

302g is a portion that generates an enable signal using a GHil signal 307g, that is, a non-rectangular signal. When the register 306g is "07", texture processing is applied only to the part where the GHil signal is enabled.At this time, the enable is 12.
If 8 is kept active, non-rectangular texture processing is performed that is not affected by non-rectangular signals, that is, synchronized with HSNC.If enable signal GHil and enable 128 are made the same, texture processing is performed that is synchronized with non-rectangular signals. Become.

For example, if a 3 lb bit signal is used for GHil, texture processing can be performed only on a certain color.

The LCHG and N signals 141g are gradation resolution switching signals, which are delayed by the amount of delay in the arithmetic unit 215g, and then the LCHG
ou. Output from 350g.

<Mosaic, scaling, and taper processing unit> Next, the general operation of the mosaic, scaling, and taper processing unit G12 of the image processing/editing circuit G will be described using FIG. 33.

The image data 126g and the LCHG signal 350g input to the mosaic, scaling, and Taber processing section 102g are first input to the mosaic processing section 401g. The mosaic processing unit 401g uses the Mj signal 145 output from the character synthesis circuit F and the area signal GHi 2149 from the switching circuit N.
, after the mosaic clock MCLK from the mosaic processing control unit 402g determines the presence or absence of mosaic processing, the size of the mosaic in the main scanning direction, and the composition of characters, 1t0
2 selector-403g. Here, the main scanning direction size for mosaic processing is the mosaic clock MCLK.
It is made variable by controlling. Control of the mosaic clock MCLK will be explained in detail later.

The lto2 selector 403g outputs the input image signal and LCHG signal to either Yl or Y2 using the line memory select signal LMSEL obtained by frequency-dividing HSYNC 118 by the D flipflop 406G.

The output from Yl of 1to2 selector-403g is line memory A404g and 2tol selector-407g.
is connected to A of Also, the output from Y2 is line memory 8405g and 2tol selector 407.
Connected to B of g. When an image is sent from selector 403g to line memory A, line memory A
404g is in write mode and line memory 8
405g is in read mode. Similarly, when an image is sent to the line memory 8405g from the selector 403g, the line memory B is in the write mode and the line memory A 404g is in the read mode. In this way, the image data read out alternately from line memory A 404g and line memory B 405g is 2tol.
Selector 407g''CD'7 Lip Float 406g
The image data is output as continuous image data while being switched by an inverted signal of the output LMSEL signal. The output image signal from the 2tol selector 407g is then sent to the enlargement processing section 4.
After predetermined enlargement processing is performed in step 14g, the image is output.

Next, write/read control of these memories will be described. First, when writing or reading, line memory A
404g, the address given to the line memory 8405g is synchronized with HSYNC, which is the reference for one scan, and is synchronized with the image C
Up/down counters 409g, 41 to increment and decrement in synchronization with LK.
It is composed of 0g. A counter enable signal output from the line memory address control unit 413g,
The operation of the address counters (409g, 410g) is controlled by a control signal WENB for controlling a write address and a control signal RENB for controlling a read address generated from the scaling control section 415g. These controlled address signals are input to 2tol selectors 407g and 408g, respectively.

The 2tol selectors 407g and 408g provide a read address to the line memory A 404g and a write address to the line memory 8405g when the line memory A 404g is in the read mode in response to the above-mentioned line memory select signal LMSEL. When the line memory A 404g is in write mode, the opposite operation is performed.

Next, line memory A. Memory write pulses WEA and WEB to line memory B are output from the variable magnification control section 415g. Memory write pulses WEA and WEB are used when reducing the input image and when the mosaic processing control unit 4
Mosaic processing is controlled by a mosaic length control signal MOZWE in the sub-scanning direction output from 02g.

Next, a detailed explanation of these operations will be given below.

<Mosaic Processing> Mosaic processing is basically realized by repeatedly outputting one image data.

This mosaic processing operation will be explained using FIG. 34.

First, a mosaic processing control unit 402g independently performs main scanning and sub-scanning mosaic processing control.

First, set the variable corresponding to the desired mosaic size to CPU
The CPU sets the latch 501g (for main scanning) and the latch 502g (for sub-scanning) connected to US.

First, for mosaic processing in the main scanning direction, the same data is written continuously to multiple addresses in the line memory, and for mosaic processing in the sub-scanning direction, writing to the line memory is performed at a specified line within the mosaic processing area. This is done by thinning out each time.

(Main scanning direction mosaic processing) Variables corresponding to the main scanning direction mosaic processing are set in the latch 501g by the CPU. The latch 501g is connected to the main scanning mosaic control counter 504g,
The setting value is loaded by the HSYNC signal and the ripple carry of the counter 504g.

A counter 504g loads the value set in the latch 501g for each HSYNC, counts a predetermined value, and outputs ripple carry to the NOR gate 502g and AND gate 509g.

Mosaic clock MCL from AND gate 509g
K is a signal obtained by multiplying the image clock CLK by the ripple carry from the counter 504g, and MCLK is output only when the ripple carry occurs.

MCLK output from the AND game 509g is then input to the mosaic processing section 401g.

The mosaic processing unit 401g operates the two D flip-flops 510g and the flip-flop 510 regardless of the Mj signal.
Output g. When the GHi2 signal 149 is 1 and the Mj signal is O, a signal from the flip-flop 511g controlled by the mosaic clock MCLK is output.

When the Mj signal is 1, the output is a flip-flop 510g
Output the signal from. With this control, it is possible to output a part of the mosaic-processed image in the main scanning direction without performing the mosaic process. In other words, it is possible to perform mosaic processing on only the image without performing mosaic processing on the characters that have been synthesized into an image by the preceding character synthesis circuit F as shown in FIG. The output from the selector 512g is input to the 2tol selector 403g shown in FIG. 33 mentioned above. As described above, mosaic processing in the main scanning direction is performed.

(Sub-scanning direction mosaic processing) Similarly to the main scanning direction, the sub-scanning direction is also controlled by a latch 502g connected to CPUBUS, a counter 505g, and a NOR gate 503g. The sub-scanning mosaic width control counter is ITOP signal 144, 51 1g, selector 512g, AND gate 514g, inverter 5
It is composed of 13g. Flip Flop 510g
, 511g, in addition to the image signal, a gradation resolution switching signal LCHG is connected to the flip-flop 510.
g is the image clock CLK, flipflop 51
1g holds the image data manually input by the mosaic processing clock MCLK and the LCHG signal. In other words, the gradation resolution switching signal LCHG corresponding to one pixel is
Flip flop 510g, 511 when the phase is matched
G is held during each cycle of CLK and MCLK. Each retained image signal and LCHG
The signal is input to 2tol selector-512g. The output is switched by the mosaic area signal GHi2 and the binary character signal Mj signal. Selector-512g
generates a ripple carry pulse by counting HSYNCll8. The ripple carry pulse is applied to the mosaic area signal GHi to the OR gate 508g.
The inverted signal GHi2 of 2149 and the character signal Mj are input. It is input to the sub-scanning mosaic control signal MOZWE415g, and the NAND gate 515g controls the write pulse generated by a line memory write pulse generation circuit (not shown). The line memory write pulse generation circuit is a circuit whose output clock rate is variable, such as a rate multi-briar which is generally used for variable magnification control. In this embodiment, detailed explanation will be omitted since it differs from the gist of the invention.

The WR pulse controlled by the above MOZWE signal then becomes H
The switching pulse changes from l to 2 selector to W by the switching signal LMSEL signal, which changes the switching pulse every SYNCl18.
WR pulses are alternately output to EA and WEB. With the above control, the mosaic area signal GHi2 signal 149 is “
Even in the case of "l", writing to the memory is performed when the Mj signal becomes "l", so it is possible to output a part of the mosaic processed image in the sub-scanning direction without mosaic processing. 35(a) is a diagram showing the distribution of density values for each pixel for recorded colors in which mosaic processing is actually performed.In the mosaic processing of FIG.
Each pixel in a 3×3 pixel block is set as a representative pixel value. In this process, the mosaic process is not performed on the character A1, that is, the pixels in the shaded area, based on the character signal Mj. In other words, when a composite character and a mosaic processing area overlap, priority can be given to the character.

Therefore, even when mosaic processing is performed, an image can be formed so that only the characters can be read. Note that the mosaic area is not limited to a rectangular shape, and mosaic processing can also be performed on a non-rectangular area.

(Italics, Taper Processing) Next, the italics processing will be described first with reference to FIGS. 33 and 36.

FIG. 36 shows the inside of the line memory address control section 413g in FIG. 33. This line memory address control unit 413g has write and read counters 409g, 4
10g enable signal is controlled, and movement, italics, etc. are possible by controlling an address counter to determine which part of the main scanning line is to be written into or read from the line memory. First, using Figure 36,
The enable control signal generation circuit will be explained.

Counter 701g has a counter output of 0 at HSYNC.
Then, the image clock 117, which is the clock of the counter 701g, is counted. Counter 7Ql
The output Q of g is the equisurface comparator 706g, 708g, 7
It is input in 09g and 710g. Converter 70
The eight input sides of each comparator other than 9g are connected to independent latches (not shown) connected to CPUBUS, and any set value and counter 701g
When the output matches the output, a pulse is output. The output of the equilateral comparator 706g is the J-K fritub flop 70.
8g and the comparator 707g is connected to the K input, and from when the comparator 706g outputs a pulse until the comparator 707g outputs a pulse, the J
-K flip-flop 708g is configured to output l. This output is used as a write address counter control signal, and the write address counter is activated only in the period where it is 1, and generates an address for the line memory. Similarly, the read address counter control signal controls the read address counter. Here, A of comparator 709g
A selector 703g is connected to the input signal to make the input value to the comparator different depending on whether italic processing is performed or not. Here, when the italic processing is not performed, the value set in the latch connected to CPUBUS (not shown) is input to the A input of selector 703g, and the A input is similarly output by the select signal output from the latch (not shown). It is output from the selector 703g. The subsequent operation is performed by the aforementioned comparators 706g and 707.
This is the same operation as g. Next, when performing italics, the value input to A of selector 703g is also input to selector 702g as a preset value. selector
When the select signals of 702g and 703g select the B input, the output of selector 702g is sent to adder 704g.
Then, this value is also added to a value set in a latch (not shown). Here, this value indicates the amount of change for each l line due to the oblique angle, and if the desired angle is θ, then tan
It is determined by θ. The addition result is input to a flip-flop 708g clocked by HSYNC 118, and the value is held for one main scan. The output of the flip-flop 705g is connected to the B input of the selector 702g and the selector
Connected to the B input of 703g. By repeating this addition operation, the output value from the selector to the comparator 709g changes at a constant rate for each scan, and the start of the read address counter is set to H.
It can be varied at a constant rate from SYNC. As a result, the reading from the line memories A404g and A8405g is shifted with respect to HSYNC, and italic processing becomes possible. Further, the amount of change described above may be either positive or negative; if it is positive, the readout will shift away from HSYNC, and if it is negative, it will shift toward HSYNC. In addition, selector 702g,
By changing the select signal of 703g in synchronization with HSYNC, partial italics can be made.

Regarding enlargement processing methods, generally 0th order, ■order, SINC
There are methods such as interpolation, but since they are different from the gist of the present invention,
Explanation will be omitted. Taper processing is made possible by changing the magnification in the main scanning direction in synchronization with HSYNC for each scanning line while performing diagonal processing.

In addition, in these processes, the input gradation resolution switching signal is processed while matching the phase with the image signal, and the output image data 114 and the output gradation resolution switching signal LCHG are processed.
l42 is output to the edge emphasis circuit.

The conceptual diagram of the italic processing and Taber processing explained above is shown in the 35th page.
Shown in Figure (b), CC).

FIG. 37(a) is a block diagram showing details of a mask bitmap memory 573L and its control for restricting an area of arbitrary shape. This memory has a shape as shown in FIG. 37(e), for example, and is used for the aforementioned color conversion, image cropping (non-rectangular trimming), and image filling (
It is used as an ON (process)/OFF (non-process) switching signal for various image processing/editing such as non-rectangular painting).

That is, in FIG. 2, BHil23, DHil22,
FHil21, GHi119, PHil45, A H
It is supplied via the i l 4 8 signal line.

As shown in Figure 38, the mask is constructed so that 4x4 pixels are one block and one bit of the bitmap memory corresponds to one block, so for example, 16pe
For an image with a pixel density of l/mm, 297mm x 420m
m (A3 size), (297X420X1
6X16)÷16#2Mbit, that is, for example I
It can be configured with M bit dynamic RAM and 2 chips.

The signal 132 input to the FIFO 559L in FIG. 37(a) is a data input line for mask generation as described above. When input as , first, 4×
Count the number of "1"s in the block of 4 (1 bit x 4 line buffers 559L, 560L, 561L
, 562L. FIFO559L~562L
As shown in the figure (output of 559L is input to 56OL,
The output of 560L is connected to the input of 561L, and so on, and the output of each FIFO is connected to a 4-bit parallel memory transistor 563L.
~565Ll;':, VCLKI: is latched (see the timing chart in FIG. 37(d)).

FIFO output 615L and latch 563L, 56
4L, 565L outputs 616L, 617L, 61
8L is added by adders 566L, 567L, and 568L (signal 602L), and the CPU 22 compares the value with the value (for example, "12") set via ■/0 port 25L in converter 569L. . That is, here, it is determined whether the number of 1's in the 4×4 block is greater than a predetermined number.

In FIG. 37(d), the number of "l"s in block N is "14" and the number of 1's in block (.N+1) is "4", so the comparator 569L in FIG. 37(a) When the signal 602L is "l4", the output 603L is larger than "12", so when the signal "l" is "4", it is smaller than "12", so it becomes "0". Therefore, the latch pulse 605L in FIG. , the latch 570L latches one 4×4 block once, and the Q output of the latch 570 is stored in the memory 57.
3L DIN input, that is, mask creation data. 580L is an H address counter that generates the address in the main scanning direction of the mask memory, and since one address is assigned to a 4×4 block, the pixel clock VCL
Counting up is performed using a clock obtained by dividing K608 into four by a frequency divider 577L. Similarly, 575L is an address counter that generates an address in the sub-scanning direction of the mask memory, and for the same reason, it is counted up by a clock obtained by dividing the synchronization signal HSYNC of each line by 4 by a frequency divider 574L, and the H address. ■Address operation is 4×4
It is controlled to be synchronized with the counting (addition) operation of "l" within the block.

In addition, ■ Output of the lower 2 bits of the address counter, 610
L, 611L is NORed by a NOR gate 572L, and a signal 606 gates a 4-frequency clock 607L.
L is created, and the AND gate 571L is used to divide 1 block into 4×4 blocks as shown in timing chart FIG. 37(C).
The latch signal 605L is applied so that latching is performed only once. Further, 616L is a data bus included in the CPU bus 22 (FIG. 2), 613L is an address bus, and a signal 615L is a write pulse WR from the CPU 22. Memory 57 from CPU 22
During WR (write) operation to 3L, the write pulse is “L”
o", the gates 578L, 576L, and 581L are opened, and the address bus and data path from the CPU 22 are connected to the memory 573L, and predetermined data is written at random, and WR is sequentially written by the H address counter and the ■address counter. (write), RD read, the gate 576 is connected to the I/O port 25 by the control lines of the gates 576'
' L, 582L is opened and sequential addresses are provided to memory 573L.

For example, the output 421 of the binarized output 532 or the CPU
22, if a mask as shown in FIG. 39 is formed, images can be cut out, synthesized, etc. based on the area within the bold line frame.

Further, the bitmap memory shown in FIG. 37(a) can be read by thinning out or interpolation in both the H direction and the ■ direction.

That is, as shown in FIG. 40, the details of the H or ■ address counter (580L, 575L) in FIG. 37 are shown.
For example, during reduction, the B input of the selector 634L should be selected.<MULSEL 636L is set to "0".

635L is a decimation circuit (rate multilayer) for the input clock 614L, and FIG. 41 (timing diagram)
As shown in <<, for example, CLK is thinned out so that it is output once every three times (setting is based on I/O port 641L)
(637L). On the other hand, 630L is set to, for example, "2", and only when the thinned out output 637L is output, the output 638L of address counter 632L and the value set in 63OL (for example, "2") are added, and the result is loaded into the counter. Therefore, as shown in FIG. 41, the clock advances by "+2" every three clocks in the order of l→2→3→5→6→7→9, etc., resulting in a reduction of 80%. On the other hand, when enlarging, MULSEL="B" and 8 inputs 614L are selected, so as shown in the timing chart of Fig. 41,
The address count progresses in the order of l→2+3→3→4→5→6→6saki...

Figure 40 shows the H address counter 580L of Figure 37, ■
This is the details of the address counter 575L, and since the hardware circuit is the same, the explanation will be limited to FIG. 37 only.

As a result, as shown in Fig. 42, enlargement 2 and reduction l are generated for the non-rectangular area l that is immediately input, so once the non-rectangular area is input, no new input work is required. Furthermore, with one mask brain, it is possible to change the magnification according to various magnifications.

Next, the binarization circuit (532 in FIG. 2) and the high-density binary memory circuit K will be explained. In FIG. 43(a), the binarization circuit 532 outputs the video signal 1 of the output of the character image correction circuit E.
13 with a threshold value 141k to obtain a binary signal, the threshold value is set by the CPU bus 22 in conjunction with the operation unit. In other words, the threshold value is the amplitude value of input data =
256, the memory of the operation unit in FIG. 43(C) is set to M(
When specified as the midpoint), it is '128', and as the scale moves in the ten directions, it changes by -30" from the midpoint, and as it moves in one direction, it changes by +30". Therefore, corresponding to "weak → -2 → -1-4M → +l → +2 → strong", the threshold value is "218 → 188 → 158 → 128 → 98 → 68 →
38”.

In addition, as shown in FIG. 43(a), CPUBUS
From 22, two threshold values are set, and selector 35
At k, it is switched by the switching signal 151 and set as a threshold value in the converter 32k. For the switching signal 151, a different threshold value is set only within a specific area set by the Digitiger 58. For example, the threshold value is relatively low for a monochromatic area of the original, and relatively high for a mixed color area. Settings can be made so that a uniform binary signal is always obtained regardless of the color of the original.

The memory circuit K is a memory that stores the signal in which the binarized signal 421 is output to 130 for one page of images, and since this device handles images at A3 and 400 (dpi), approximately 3 It has 2 Mbit.

Details of the memory circuit K will be explained in FIG. 43(b).

The input data l), N130 are gated by the enable signal HE528 when writing to the memory, and are further gated by the W/ of the 10-board 23k controlled by the CPU 20 when writing.
When the R I output is "Hi", it is input to the memory part 37k. At the same time, the image vertical synchronization signal ITOP144
synchronization signal HSYNCI1 in the main scanning (horizontal scanning) direction
Count 8 and generate a vertical address. ■
The address counter 35k1HSYNCI18 counts the image transfer clock VCLK117 to count the addresses in the horizontal direction. The H address counter generates an address corresponding to storage of image data. Memory WP input at this time (write timing signal)
A clock having the same phase as the clock VCLK117 is input as a strobe to the clock 551k, and the input data Di is sequentially stored in the memory part 37k (timing diagram, FIG. 44). When reading data from memory 37k,
By setting the control signal W/R 1 to "LO", output data D is generated in exactly the same manner. ．． JA is read out. However, data writing and reading are both HE52
8, so for example, as shown in Figure 44, < }{E
528 to "Hi" at the input timing of D2 and falls to "Lo" at the input timing of Dm, the data from D2 to D.528 is stored in the memory 37k. , l are only input, and the images after Do, D, and Dm++ are not written, and data "0" is written instead. The same goes for reading, and data "0" is read out except for the section where HE is "Hi". HE is output from an area signal generation circuit 17, which will be described later. That is, for example, when a character manuscript as shown in FIG. 45A is placed on the manuscript table, when writing the binary signal, HE is set as
Once generated, it is possible to import into memory a binary image with only the character part, such as A'. Similarly, unnecessary characters can also be erased and written into the memory.

Furthermore, since the address counters 35k and 36k that read data from the memory 37k have the same configuration as in FIG. 40 and operate at the same timing as in FIG. 41, the binary data read from the memory 37k is It becomes possible to change the magnification. Therefore, when synthesizing the binary character image shown in (B) of the same figure, which has been previously stored in this memory as shown in Fig. 46, with the image of (A), both of them are reduced as shown in (C). or create a sketch ((A) as shown in (D)).
It is possible to perform composition by enlarging only the character part to be composited without changing the size of the part ).

FIG. 47 shows the data stored in the loadpi format described above.
Each image processing block A, B, D of data from the binary bitmap memory L for non-rectangular masks (Fig. 2) and the 400 dpi binary memory K for characters and line images (Fig. 2).
This is a switching circuit for switching between distribution to F, P, and G and distribution of binarized video images to memories L and K. The mask data for limiting the non-rectangular area stored in the memory is sent to, for example, the aforementioned color conversion circuit B (BHi 123), and for example, only the inside of the shape as shown in FIG. Requires color conversion. In FIG. 47, 1n is an I/O connected to the CPU bus 22.
O port, 8n-13n is a 2tol selector,
It is configured to output the A input to Y when the switching power S='9' and the B input to Y when s='o'.Therefore, for example, as described above, the output of the LOODPI mask memory L is output to the color conversion circuit. In order to send to B, select A in the selector 90, that is, 28n="1", AND game}3
In n, 2In human power may be set as "l". Similarly, other signals can be arbitrarily controlled by 16n to 31n. The outputs of the I/O port}nl, 30n and 31n, are control signals for storing the output of the binarization circuit 532 (Fig. 2) in either the binary memory L or K. When 30n is "l" , binary human power 421 goes to loOdpi memory L, 31n
= "I", the data will be input to the 400 dpi memory K.

By the way, when AHil48-“l”, image data sent from external equipment is combined and BHil23-“l”
In this case, color conversion is performed as described above, and D H i122
="1", monochrome image data is calculated and output from the color correction circuit. Below FHi 121, PHi14
5, G}Iil 119, GHi2 149 are respectively character synthesis, color balance change, texture processing,
Used for mosaic processing.

In this way, it has two binary memories, 100 dpi memory L and 400 dpi memory K, and stores character information in high-density 4-bit memory.
By inputting region information (including rectangular and non-rectangular shapes) into the 100 dpi memory K, character synthesis can be performed in a predetermined region, especially in a non-rectangular region.

Furthermore, by having a plurality of bitmap memories, color mudding processing as shown in FIG. 62 is also possible.

FIG. 49 is a diagram for explaining the area signal generation circuit J. The area refers to, for example, the shaded area in FIG. 49(e), which refers to the timing chart AREA in FIG. 49(e) for each line in the sub-scanning direction A-H.
It is distinguished from other areas by signals such as . Each area is designated by digitizer 58 in FIG. Figure 49(a)-(d)
), the generation position, section length, and number of sections of this area signal are C
This shows a configuration that is programmable and can be obtained in large numbers by the PU 20. In this configuration, one area signal is generated by one bit of the RAM that can be accessed by the CPU, and for example, n area signals A R E A O - A
In order to obtain R E A n, an n-bit RAM is used.
(Fig. 49(d) 60j, 610
. Now, if we obtain the area signals AREAO and AREAn as shown in FIG. 49(b), the RAM address x1
* Set bit 0 of X3 to “1” and set all bits O of the remaining addresses to “0”. On the other hand, bits are set at RAM addresses 1, X11, X21, and For example,
As shown in FIG. 49(C), data "l" is read at addresses Xi and X3. This read data is input to both the J and K terminals of the JK flip-flops 62j-0 to 62j-n as shown in FIG. 49(d).
The output is a toggle operation, that is, when "1" is read from the RAM and CLK is input, the output changes from "0" to "1", "l".
” → changes to “0”, and a section signal such as AREAO,
A region signal is therefore generated. Furthermore, if data is set to "0" over all addresses, no area section is generated and no area is set. FIG. 47(d) shows this circuit configuration, and 60j and 61j are the aforementioned RAMs. For example, RAM
While reading data line by line from RAMB 60j, the CPU 20
Memory write operations for more different area settings are performed, and interval generation and memory write from the CPU are alternately switched. Therefore, when specifying the shaded area in Fig. 49(f), R
AMA and RAMB are switched, which is shown in Figure 49(d).
), (C3, C4, C5) = (0, 1
, O), the counter output counted by VCLK 117 is given as an address to RAM 60j through selector 63j (Aa), gate 66j is opened,
The gate 68j is closed and read out from the RAM 60j, and the total bit width, n bits, is transferred to the J-K flipflop 62.
j-0 to 62j-n, and interval signals AREAO to AREAn are generated according to the set values. During this time, writing from the CPU to B is performed on the address bus A-Bu.
ssy' bus D-Bus and access signal R/
Performed by W. Conversely, when generating section signals based on data set in RAMB61j (Cs, C4,
By setting C5)=(1.0, l), the same operation can be performed and data can be written from the CPU to the RAM 60j.

58 is a digitizer for specifying an area;
The coordinates of the specified position are input from U20 via the I/O port. For example, in FIG. 50, when two points A and B are specified, the coordinates of A (XI, Y2) and B (X2.Yl) are input.

FIG. 51 shows an interface circuit M for bidirectional communication of image data with an external device connected to this image processing system. lm is an I/O boat connected to the CPU bus 22, and each data path AO to CO, At
- Signals 5m to 9m for controlling the directions of CI and D are output. 2m and 3m are pass buffers having an output dry state control signal E, and 3m can change its direction by inputting D. For 2m and 3m, when E input = “l”,
When the signal is output and "O", the output is in a high impedance state. 10m is 3 systems of parallel human power A, B,
3t to select one from C by selection signals 6m and 7m
ol selector. In this circuit, basically 1. (
AO, BO, Co) → (AI, Bl, CI), 2,
There is a bus flow of (At, Bl, Cl)→D. Each is controlled by the CPU 20 as shown in the truth table of FIG. In this system, as shown in Fig. 53, images input from external devices through AI, A2, and A3 are rectangular, as shown in Fig. 53 (A),
Both non-rectangular and non-rectangular configurations as shown in (B) are possible. When inputting in a rectangle as shown in Figure 53 (A),
In order to set the switching input of the selector 503 in FIG. 2 to "1" so that A is selected, a control signal 147 is output from the I/O port 50l.

Corresponds to the area to be combined at the same time. Area signal generation circuit J
The rectangular area signal 129 is generated by writing predetermined data from the CPU to predetermined addresses in the RAMs 60j and 61j (FIG. 51), as described above. In the area where the image input 128 from the external device is selected by the selector 507, not only the image data 128 but also the gradation,
The resolution switching signal 140 is also switched at the same time. That is, in an area where an image from an external device is input, a character area signal is generated based on the MIAR 124 (FIG. 2), which is detected from the color separation signals of the image read from the document table. Stop the gradation and resolution switching signals and forcefully “
By setting it to "Hi", the image area from the inserted external device is outputted smoothly with high gradation.

Further, as explained in FIG. 51, bitmap mask signal AHi 148 from binary memory L
When selected by signal 147 at 03, Fig. 53 (B)
Image synthesis from external devices such as

<Overview of the operating section> FIG. 54 shows an overview of the main operating section 1000 of this embodiment. Key 1100 is a copy start key.

Key 1 101 is a reset key that returns all settings on the operation panel to the values when the power was turned on. A key 1102 is a clear stop key, which is used to reset input values such as specifying the number of copies and to cancel a copy operation.

A group of keys 1103 is a numeric keypad and is used to input numerical values such as the number of copies and magnification input. A key 1104 is a document size detection key. A key 1105 is a center movement designation key. A key 1106 is an ACS function (black original recognition) key. When ACS is ON, a monochrome black original will be copied in monochrome black. A key 1107 is a remote key, and is a key for passing control to a connected device. Key 1108 is a preheat key.

A liquid crystal screen 1109 displays various information.

The surface of the screen is a transparent touch panel, and when you press it with your finger, the coordinate values are captured.

In the standard state, the magnification, selected paper size, number of copies, and copy density are displayed. While setting various copy modes, the screens necessary for mode settings are displayed one after another. (Setting the cobby mode is done using the keys displayed on the screen.) Also displays the self-diagnosis display screen on the guide screen.

A key 1110 is a zoom key, and is an enter key for entering a mode for specifying the magnification of magnification. Key 1.111 is a zoom program key, and is an enter key to a mode in which a magnification ratio is calculated from the original size and copy size.

A key 1112 is an enlarged continuous shooting key, and is an enter key for entering enlarged continuous shooting mode.

A key 1113 is a key for setting inset composition.

A key 1114 is a key set for character composition. key 1
115 is a key for setting color balance. key 1
Reference numeral 116 is a key for setting a color mode such as single color, negative/positive inversion, etc. Key 1117 is a user's color key, and can set any color mode. key 111
8 is a paint key that allows you to set the paint mode. A key 1119 is a key for setting a color conversion mode.

Key 1120 is a key for setting the contour mode. Key 1121 is used to set the mirror image mode. Specify trimming and masking with keys 1124 and 1123.

It is possible to specify an area using the key 1122 and set the internal processing differently from other parts. key 1129
is the enter key to enter the mode that performs tasks such as loading texture images. Key 1128 is an enter key for entering a mosaic mode such as changing the mosaic size.

Key 1127 is an enter key to a mode that adjusts the edge sharpness of the output image. The key 1126 is a key for setting an image repeat mode in which a specified image is repeatedly output.

The key 1l25 is a key for applying italic/tapering, etc. to the image. Key 1135 is a key for changing the movement mode. A key 1134 is used to make settings such as continuous page copying and arbitrary division, and a key 1133 is used to make settings related to the projector. Key 1132 is an enter key to a mode for controlling optional connected equipment. The key 1131 is a recall key that allows you to recall the settings up to three times ago. Key 1130 is an asterisk key.

Keys 1136 to 1139 are mode memory recall keys.
Used when recalling a registered mode memory. Keys 1140 to 1143 are program memory call keys, which are used to call up registered operating programs.

<Color conversion operation procedure> The procedure of color conversion operation will be explained using FIG. 55.

First, when the color conversion key 1119 on the main body operation section is pressed, the display section 1109 is displayed as PO50.

Place the original on the digitizer and use the pen to specify the color before conversion. When the input is completed, the screen of PO51 appears. Here, use touch key 1050 and touch key 1051 to adjust the color width before conversion, and after completing the setting, touch key l052.
Press. The screen changes to P052, and the user selects whether or not to add shading to the converted color using touch keys 1053 and 1054.

If you select shading, the color after conversion will have gradation to match the shading of the color before conversion. That is, the above-mentioned gradation color conversion is performed. On the other hand, if you select no shading, the specified color will be converted to the same density. If you select whether or not to have shading, the screen of P053 will appear, allowing you to select the type of color after conversion. When 1055 is selected in P053, P
The operator can specify any color to O54. Also, if you press the color adjustment key, it will move to PO55 and Y, M, C, Bk
Color adjustments can be made in 1% increments for each.

Further, if 1056 is pressed in P053, the process moves to P056, and the user specifies the desired color of the document on the digitizer with the point pen. Next, the color shading can be adjusted using PO57.

Furthermore, if 1057 is pressed at P053, the screen moves to P058, where a predetermined registered color can be selected by number.

<Procedure for specifying the trimming area> Below, using Figures 56 and 57, trimming (
The same goes for masking, and how to specify areas.
The same procedure applies to partial processing, etc. ) Explain the procedure for specifying an area.

If you press the trimming key l124 on the main body operation unit 1000 and enter two diagonal points of the rectangle using the digitizer when the display unit 1l09 becomes Pool, the screen of P002 will appear, and you can continue to input the rectangular area. can. Also, if you have specified multiple areas, press the previous area key 1001 of PO0 1, then press the area key l002 to select the POO area.
As shown in 2, each designated area in the X-Y coordinates can be confirmed.

On the other hand, in this embodiment, it is possible to specify a non-rectangular area using the bitmap memory. POO 1
While displaying the screen, press touch key l003 to move to POO3. Select the shape here. For circles, ellipses, R rectangles, etc., when the necessary coordinate values are input, the shapes are expanded into the bitmap memory by calculation. In the case of a free shape, coordinate values are continuously input by tracing the desired shape with a point pen using a digitizer, and the values are processed and recorded on a bitmap.

Each non-rectangular area specification will be explained below.

(Circular Area Designation) When the key 1004 is pressed at P003, the display section 1109 moves to POO4, where a circular area can be specified.

The circular area designation will be explained below using the flowchart of FIG. 58. At SIO1, the center point is input from the digitizer 58 of FIG. 2 (POO4).

Next, the display unit 1109 moves to POO5 and inputs one point on the circumference of a circle having the radius to be specified from the digitizer 58 in S103. In S105, the CPU 20 calculates the coordinate values of the input coordinate values on the bitmap memory L (LOODPI binary memory) shown in FIG.

Further, in S107, coordinate values of another point on the circumference are calculated.

Next, a bank of the bitmap memory L is selected at 8109, and the above calculation result is input to the bitmap memory L via the CPU bus 22 at Sill. Figure 37(a)
The data is written from CPU DATA 616L to bitmap memory from 604L via driver 578L. Address control is the same as described above, so it will be omitted. This is repeated for all points on the circumference (S113) to complete the circular area designation.

In addition, instead of inputting information while calculating it in the CPU 20 as described above, template information for the two inputted information points is stored in the ROMII in advance, and by specifying these two points with a digitizer, the information can be input directly without calculation. It is also possible to write to the bitmap memory L.

(Oval area specification) P003. Then, when the key 1005 is pressed, the process moves to P007. The process will be explained below using the flowchart shown in FIG.

First, in S202, the diagonal 2 of the largest rectangular area inscribed in the ellipse
A point is designated by the digitizer 58. For the following circumferential part, do S206 in the same way as in the case of specifying the circular area above.
~S21 Write to bitmap memory L in steps 2.

Next, the straight line portion is written into the memory in steps 8214 to S220, and the area designation is completed. As in the case of a circular shape, it can also be stored in the ROM 21 in advance as template information.

(R rectangular area designation) The method of designation is the same as in the case of an ellipse for memory writing, so the explanation will be omitted.

Incidentally, although the cases of a circle, an ellipse, and an R rectangle have been explained above as examples, it goes without saying that other non-rectangular areas can also be specified based on the same template information.

In POO6, POO8, POIO, and P102, by pressing the clear key (1009 to 1012) after inputting each shape, it is possible to partially erase the bitmap memory.

Therefore, even if a mistake is made in the designation, only the two points can be quickly cleared and the two points can be designated again.

It is also possible to specify multiple areas in succession. When multiple areas are specified, priority is given to processing of the area specified later when processing each of the overlapping areas. However, the one specified first may be given priority.

FIG. 57 shows an output example obtained by trimming with an ellipse using the above settings.

Operation procedure for character composition> Figure 60 below. The operation setting procedure regarding character synthesis will be explained using FIG. 61 and FIG. 62. When you press the character synthesis key 1114 on the main body operation section, the liquid crystal display section 1109 displays P.
It will be displayed like O20. A character original 1201 to be synthesized is placed on the original table described above, and when the touch key 120 is pressed, the character original is read, binarized, and the image information is stored in the bit map memory shown in FIG. 2 described above. The specific means of processing has been described above, so duplication will be avoided. At this time, to specify the range of the image to be stored, press the touch key 1021 in P020 to go to the screen of PO21, place the text document 120l on the digitizer 58 mentioned above, and use the point ben of the digitizer to mark the range with two points. specify.

When the specification is completed, the display section changes to P022, and the user selects whether to read within the range specified by touch key 1023 and touch key 1024 (trimming) or to read outside the specified range (masking). Also,
Depending on the text document, it may be difficult to extract the character portion of the text document during the above-mentioned binarization process. In this case, the touch key 1022 in P020 moves to the screen of P023, and the slice level of the binarization process can be adjusted using the touch key l025 and the touch key 1026.

Since the slice level can be adjusted manually in this way, appropriate binarization processing can be performed depending on the color, thickness, etc. of the characters on the document.

Furthermore, press touch key l027, PO24'PO2
By specifying an area with 5', it is possible to partially change the slice level with PO26'.

In this way, by specifying an area and changing the slice level only for that part, even if there is, for example, yellow text in a part of the black text document, separate appropriate slice levels can be set for each of the black and yellow text. By doing so, it is possible to perform good binarization processing on the entire character.

When the reading of the character original is completed, the display section 1109 becomes as shown in FIG. 61, P024.

To select color blank processing, touch key 10 in PO24
Press 27 to move to the screen of P025, and select the color of the characters to be combined from among the displayed colors.

It is also possible to partially change the color of the characters, in which case the user presses the touch key 1029 to move to the screen P027, specifies the area, and then selects the color of the characters on the screen PO30. Furthermore, it is also possible to add color border processing to the edges of the characters to be synthesized, in which case PO30
Move to the PO32 screen using the touch key 1031 inside and select the color of the border. At this time, color adjustment can be performed in the same way as in the case of color conversion described above. Furthermore, touch key 1033
Press to adjust the border width on the PO41 screen.

Next, a case in which color number processing is added to a rectangular area containing characters to be synthesized (hereinafter referred to as square processing) will be described. P02
Press the touch key 1028 in 4 to move to the PO 34 screen and specify the area. The processing will be performed within the range specified here. When the area designation is completed, the character color is selected in P037, the touch key 1032 is pressed, the screen moves to PO39, and the color of the square is selected.

In the above color selection, for example, on the screen PO25, by pressing the color adjustment key of the touch keys 1030, the screen moves to P026, where it is possible to change the tone of the selected color.

Character synthesis is performed according to the procedure described above. FIG. 62 shows an example of the output when the settings are actually made.

In addition to specifying a rectangular area, the area specification can also specify a non-rectangular area as described above.

<<Texture processing setting procedure>> Next, texture processing will be explained using FIG. 63.

When the texture key 1129 on the main body operation section 1000 is pressed, the display section 1109 displays P060.

When applying texture processing, touch key 1060 is pressed to highlight this key. When reading an image pattern for texture processing into the above-mentioned texture image memory (Fig. 32, 113g), press the touch key 106.
Press 1. At this time, if the pattern is already in the image memory, as in PO62, if it is not displayed, P
O61 will be displayed. By placing the document with the image to be read on the document table and pressing the touch key 1062, the image data is stored in the texture image memory. At this time, in order to read any part of the manuscript,
The user presses the touch key 1063 and makes a designation using the digitizer 58 on the PO63 screen. The specification is the reading range, l 6 m
This can be done by inputting with a pen at one point at the center of m x 16 mm.

Reading of a texture pattern by specifying one point as described above can be performed as follows.

Without reading the pattern, press the touch key 1060, set the texture processing, and press the copy start key 1.
If an attempt is made to escape from the P064 screen using 100, other mode keys (1110 to 11.43), touch key 1064, etc., the display unit issues a warning as shown in PO65.

Further, the length and width of this range can be specified by the operator.

Mosaic Process Setting Procedure> FIG. 64 is a diagram illustrating a mosaic process setting procedure.

When the mosaic key 1l28 on the main body operation section is pressed, the display section will display something like PIOO. To apply mosaic processing to a document, touch key 1400 is pressed to highlight this key.

Furthermore, when performing mosaic processing, the mosaic size is changed by pressing the touch key 1401 on the PIOI screen. The mosaic size can be changed independently in both the vertical (Y) direction and the horizontal (X) direction.

(About -X-mode operating procedure) FIG. 65 is a diagram illustrating the operation procedure in the pot mode.

When the blue key 1130 on the main body operation section 1000 is pressed, the blue mode is entered, and the display section l109 is displayed as Pl10. The touch key 1500 enters a color registration mode for registering color information used in paint user colors, color conversion, color text, etc. A touch key 1501 turns on/off a function for correcting image defects caused by the printer.

Touch key 1502 is a key for entering mode memory registration mode. Touch key 1503 enters a mode for specifying the manual feed size. Touch key 1504 enters program memory registration mode. The touch key 1505 is
This key is used to enter the mode for setting default color balance values.

(About color registration mode) When the touch key 1500 is pressed when PIIO is displayed, the color registration mode is entered. The display section looks like Pill, and the type of color to be registered is selected. To change the palette color, press the touch key 1506, select the color you want to change on the Plm,6 screen, and change the values of each component of yellow, magenta, cyan, and black in 1% steps on the Pl17 screen. It can be adjusted with.

Also, if you want to register any color on the document, touch key 1.
Press 507, select the registration number on the Pll8 screen,
Specify using the digitizer 58, set the original on the original table when the screen of P120 is displayed, press the touch key 1510,
Register.

(About specifying the manual feed size) As shown in PI12, the manual feed size can be specified as either a regular size or a non-standard size.

For irregular shapes, both the horizontal (X) direction and the vertical (Y) direction can be specified in units of 1 mm.

(Regarding mode memory registration) The set mode can be registered in the mode memory as shown in Pl13.

(Regarding Program Memory Registration) As shown in PI 14, a series of programs for specifying areas and performing predetermined processing can be registered.

(Regarding color balance registration) As shown in PI15, color balance can be registered for each of Y, M, C, and Bk.

About the program memory operation procedure〉Figure 66 below. The registration operation to the program memory and its usage procedure will be explained using FIG. 67.

Program memory is a memory function that stores operating procedures related to settings and reproduces them. It is possible to connect the necessary modes and make settings that go beyond unnecessary screens. As an example, let's program memory the procedure for changing the magnification of a certain area of a document and repeating the image.

Press the old mode key 1130 on the main body operation section, display the screen P080 on the liquid crystal display section, and press the program memory key of the touch key 1200. In this embodiment, four programs can be registered. Select the number to register on the PO81 screen. After this, move to program registration mode. In the program registration mode, for example, the screen shown in FIG. 68 1300 in the normal mode becomes as shown in l301. The skip key of the touch keys 1302 is designated when the user wants to skip the current screen. The clear key of the touch keys 1303 is used to cancel the current registration in the middle of program memory registration and restart the registration from the beginning.

Touch key! The end key 304 exits the program memory registration mode and registers in the memory of the first determined number.

First, the main exercises. Press the trimming key 1124 in the editing section and specify the area with the digitizer. The display is PO84
is displayed, but if you do not want to set any more areas at this point, press touch key l202 to specify that you want to skip this screen. (The screen becomes P085) Next, when the zoom key 1110 on the main body operation section is pressed, the display section becomes PO86. Here, the magnification is set and when touch key 1 203 is pressed, the display changes to PO87. Finally, press the image repeat key 1126 on the main body operation section, make settings regarding image repeat on the screen P088, and then register to program memory No. 1 using the touch key 1204.

To call up the program registered in the above procedure, press the program memory l call key 1140 on the main body operation section. The display section displays PO91 and waits for area input. If you input the area using a digitizer,
The display section displays PO92, and then moves on to the next P093. After setting the magnification here, if the touch key 1210 is pressed, the display section changes to PO94 and image repeat can be set. When the touch key 1211 is pressed, the mode in which the program memory is used (referred to as trace mode) is exited.

Note that from the time the program memory is called until the program is terminated,
Each key (1110 to 1143) in the edit mode is disabled, and operations can be performed according to the registered program.

FIG. 69 shows the program memory registration algorithm. Screen turning in S301 means changing the display on the display unit using keys or touch keys.

If you press the touch key 1302 and specify to skip the currently displayed screen (S303), that information will be set on the recording table when the next screen is turned (S303).
305). Then, in S307, a new screen number is set in the recording table. If the clear key is pressed, the record table is completely cleared (S309, S311); otherwise, the process returns to S301 and moves to the next new screen. FIG. 71 shows the format of the recording table. FIG. 70 shows an algorithm representing the operation after calling the program memory.

If there is a screen turn in S401, it is determined whether the new screen is a standard screen (S403). If it is a standard screen, the process moves to S411 and sets the next screen number from the recording table; if it is not a standard image, the new screen number is compared with the scheduled screen number in the recording table (S405);
If they are equal, the process moves to S409, and if there is a skip flag, S411 is skipped and the process returns to S401. If they are not equal, a recovery process is performed (S407) and the screen is turned over.

This embodiment has a generating means for generating a signal that bounds a non-rectangular image area, a storage means for storing the output of the generating means, a means for specifying a specific color to be detected, and an output of the specific color detecting means. By providing storage means for signals demarcating a non-rectangular image area, it is possible to perform color conversion processing on the non-rectangular area.

As explained above, according to this embodiment, by performing color conversion processing on non-rectangular areas, (1) multiple areas having converted colors are so close that they cannot be separated by rectangular areas; It is now possible to perform color conversion processing on only one side.

(2) When color conversion processing is applied to an area consisting of colors with wide gradations, the detection width can be expanded, so color conversion processing can be applied to a desired area.

This has the effect of performing the above two points, that is, more advanced and accurate color conversion processing.

The present invention is particularly effective for gradation color conversion, but is also highly effective for general color conversion (colors after conversion have no gradation).

In this embodiment, based on input image data, means for detecting a specific color in a color image (FIG. 2B), generating means for generating a non-rectangular image area signal (FIG. 2J),
Conversion means (conversion means) for converting the detected specific color into another color based on the output of the detection means and the non-rectangular image area signal;
The above objective is achieved by having the structure shown in FIG. 2B).

〔Effect of the invention〕

As explained above, according to the present invention, high-quality images are obtained. FIG. 1 is an overall diagram of an image processing apparatus according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of an image processing apparatus according to an embodiment of the present invention. Figure 3 is a diagram showing the color reading sensor and drive pulses.
, Fig. 4 is a circuit diagram for generating ODRV118a and EDRV119a, Fig. 5 is a diagram explaining black correction operation, Fig. 6 is a circuit diagram for shading correction, Fig. 7 is a color conversion block diagram, and Fig. 8 is a color Detection unit block diagram, Figure 9 is a block diagram of the color conversion circuit, Figure 10 is a diagram showing a specific example of color conversion, Figure 11 is a diagram explaining logarithmic conversion, Figure 12 is a circuit diagram of the color correction circuit. , Figure 13 shows the unnecessary transmission area of the filter, Figure 14
The figure shows unnecessary absorption components of the filter, Figure 15 is a circuit diagram of a character image area separation circuit, Figure 16 is a diagram explaining the concept of contour regeneration, and Figure 17 explains the concept of contour regeneration. Figure 18 is a contour regeneration circuit diagram, Figure 19 is a contour regeneration circuit diagram, Figure 20 is a timing chart of ENI and EN2,
Figure 1 is a block diagram of the character image correction section, Figure 22 is an explanatory diagram of addition/subtraction processing, Figure 23 is a switching signal generation circuit diagram, Figure 24 is a circuit diagram of color residual removal processing, and Figure 25 is color residual removal processing. , Figure 26 is a diagram showing edge emphasis, Figure 27 is a diagram showing smoothing, Figure 28 is a diagram explaining processing and modification processing using binary signals, Figure 29 is a diagram explaining text, Figure 30 is a block diagram of the image editing circuit, Figure 31 is a diagram showing texture processing, Figure 32 is a circuit diagram of texture processing, Figure 33 is a diagram of mosaic, scaling, and tapering processing. A circuit diagram, FIG. 34 is a circuit diagram of mosaic processing, FIG. 35 is a diagram explaining mosaic processing, etc., FIG. 36 is a circuit diagram of the line memory address control section, FIG. 37 is an explanatory diagram of the mask bit memory, Fig. 38 is a diagram showing addresses, Fig. 39 is a diagram showing a specific example of a mask, Fig. 40 is a circuit diagram of an address counter, Fig. 41 is a timing chart for enlargement and reduction, and Fig. 42 is a diagram for enlargement and reduction. Figure 43 is an explanatory diagram of the binarization circuit, Figure 44 is a timing chart of the address counter, Figure 45 is a diagram showing a concrete example of bitmap memory writing, Figure 46 is a diagram showing characters and images. Figure 47 is a diagram showing a specific example of synthesis, Figure 47 is a circuit diagram of distribution switching, Figure 48 is a diagram showing a specific example of a nonlinear mask, Figure 49 is a circuit diagram of a region signal generation circuit, and Figure 50 is a diagram of a region generated by a digitizer. Figure 51 is an interface circuit diagram with external equipment, Figure 52 is a selector truth table, Figure 53 is a diagram showing examples of rectangular areas and non-rectangular areas, Figure 54 is a diagram showing designation.
55 is a diagram explaining the procedure of color conversion operation, FIG. 56 is a diagram explaining the procedure of specifying the trimming area, FIG. 57 is a diagram explaining the procedure of specifying the trimming area, Figure 58 is a diagram showing the algorithm for specifying a circular area.
Figure 9 is a diagram showing the algorithm for specifying areas of ellipses and R rectangles, Figure 60 is an explanatory diagram of the operating procedure for character composition, Figure 61 is an explanatory diagram of the operating procedure for character composition, and Figure 62 is an illustration of the operation procedure for character composition. 63 is a diagram explaining the procedure of texture processing; FIG. 64 is a diagram explaining the procedure of mosaic processing; FIG. 65 is a diagram explaining the procedure of cloud mode operation;
Figure 67 is a diagram explaining the program memory operation procedure. Figure 68 is a diagram explaining the program memory operation procedure. Figure 69 is a diagram explaining the program memory registration algorithm. Figure 70 is a diagram showing the algorithm of the operation after calling the program memory; Figure 71 is a diagram showing the format of the recording table;
FIG. 2 is a diagram showing image processing and editing.

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Claims (5)

[Claims] (1) A means for detecting a specific color in a color image based on input image data, a generating means for generating a non-rectangular image area signal, based on the output of the detection means and the non-rectangular image area signal, An image processing device comprising a conversion means for converting a detected specific color into another color. (2) The image processing apparatus according to claim 1, wherein the specific color is a color having a specific color component ratio. (3) The image processing apparatus according to claim 1, wherein the specific color is a color having a specific color component value. (4) The specific color component ratios are R (red), G (
3. The image processing apparatus according to claim 2, wherein the image processing apparatus has a ratio of green) to B (blue). (5) The image processing apparatus according to claim 3, wherein the specific color component values are values of R (red), G (green), and B (blue).