JPH02295772A - Raster scan type perfecting printer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a raster scan type double-sided printing device such as a laser printer.

[Prior Art] When performing double-sided printing in a printing device such as a laser printer, it may be necessary to print images such as characters, figures, etc. horizontally or vertically inverted on one sheet of paper. For this reason, it is known to create an image on a page memory using software or dedicated hardware, develop the image in bits into an image buffer, and output it to the printing mechanism. However, this method has problems such as being burdensome on the software, requiring time to operate, resulting in slow printing speed, and the cost of dedicated hardware being high.

[Problems to be Solved by the Invention] The present invention solves the above-mentioned problems, and makes it possible to reverse horizontally, vertically, etc. of data in memory using simple configuration and low-cost hardware. The purpose is to provide a double-sided printing device that can reduce the burden on software and increase printing speed. [Means for Solving the Problems] In order to achieve the above object, the present invention provides a page memory in which code data such as characters, figures, etc. It is equipped with an image buffer, a printing mechanism section that sequentially inputs data output for one scan of the bit data developed in the image buffer and performs printing operations, and a CPU that controls all of these, and prints images such as characters and figures on the left and right side. In a raster scan type double-sided printing device having a back side printing mode in which printing is performed by flipping the image upside down, there is provided means for vertically inverting a row address indicating an address in the fir direction in a predetermined unit of data when setting the back side printing mode; means for horizontally inverting a column address indicating a horizontal address in data units, and means for horizontally inverting a 1-bit unit of the predetermined unit data that has been horizontally inverted as described above; An address conversion circuit interposed in the address bus between the CPU and the image buffer is used as a means for horizontally inverting unit data.

[Operations] According to Susunari, when printing on the back side, data is vertically reversed and horizontally reversed in predetermined data units, and the data that has been horizontally reversed is horizontally reversed in a 1-bit position. Here, by appropriately controlling the address conversion circuit for horizontal inversion of data in a predetermined data unit, it is possible to convert the address of the data expanded to the image buffer at will, without putting a burden on the software. You can flip the data in memory vertically and horizontally.

[Embodiment] FIG. 1 shows a block configuration of a double-sided printing apparatus according to an embodiment of the present invention.

This device includes an interface 2 into which print (code) data such as characters and graphics is input from a host computer 1 as an external device, a CPU 3 into which data is input via the interface 2 and which controls the entire device. A reception buffer 4 in which input code data is temporarily stored, a page memory (RAM > 5) in which the same data is stored in page units, a ROM 6 in which a system control program is stored, and characters corresponding to the code. a character generator (CG) 7 storing bit data such as;
A DPRAM (image buffer) 8 in which image information is expanded and stored as bit data based on the data stored in the page memory 5, and a parallel-to-serial conversion circuit 9 that converts parallel output from the DPRAM 8 into serial output. It is comprised of a printing mechanism section (engine) 10 such as a laser scanner that receives one scan worth of bit data from a conversion circuit 9 and prints it on paper.

Further, the CPU 3 and the DPRAM 8 are connected by a data bus 11, an address bus 12, and a control bus (not shown), and an address inversion circuit (not shown) consisting of an address selector and an inverter is connected between the CPU 3 and the DPRAM 8.
An address conversion circuit i>13 is interposed. This address inversion circuit 13 receives a selection signal S for the front side and the back side of the printed surface from the CPU 3, switches its operation, and outputs the address data of line F shown in the figure, which is not inverted on the front side.
On the back side, the address data of the R line shown in the figure is outputted via an inverter. Thus, when printing on the back side,
From page memory 5 to D P RAM for front side printing
When data is bit-expanded into 8, the column address indicating the horizontal address for a predetermined data unit is reversed horizontally. Furthermore, it includes a transfer address changing circuit (address decoder) 14 for changing the transfer address output from the CPU 3, and a timing generation circuit 15 for generating a timing signal for the D P RAM 8. Then, the address signal and the selection signal S for the front side and the back side of the printing side are inputted from the CPU 3 to the address decoder 14, and the timing generation circuit 15
A predetermined DPRA receives the transfer signal T1 output from
Output M control timing signal T2 to DPRAM8,
There are mainly four types of DPRAM control timing: write, read, transfer, and refresh. In addition, the data line between the DPRAM 8 and the parallel-to-serial conversion circuit 9 has one line for the print data on the back side.
A data inversion circuit 16 that inverts data bit by bit is provided. The data inversion circuit 16 receives the front side and back side selection signal S and switches between forward connection and reverse connection of data using hardware, and determines the horizontal direction (left/right direction) address for the data on the back side. In this embodiment, the rearrangement of the indicated column addresses in word units is performed by horizontally inverting data in units of 16 bits (Do to D15) adjacent to each other in one raster.

Next, FIG. 2(a) shows the data storage area of the DPRAM 8 for data on the front and back sides as seen from the CPU 3.
This will be explained using b). Each of the transfer address sections A and B on the front and back sides is configured such that when some data is written by the CPU 3 to an address in the same address section, the timing generation circuit 15 reads it, and the data for one raster corresponding to the address is read. It is provided to function to transfer print data from the DPRAM 8 to the parallel-to-serial conversion circuit 9. Figure 2(a). As shown in (b), the address of the data output from the cpU3 is the print data storage area on the front side on the row address and column address of DPRAM8, because the image is inverted for the back side data as described above. The print data storage area A and the print data storage area B on the back side are set so as to be developed at positions shifted in the column address direction.

Therefore, the storage positions of each of the transfer address sections A and B are set to a position apart from each print data area in the column address direction. Therefore, each transfer address section A seen from CPUB
, B are at different positions in the column address direction. In the above process, the CPU 3 performs a write operation to expand bit data to a predetermined address of the DPRAM 8 based on the page data (including address data) stored in the page memory 5. In addition, DPRAM8 has CP
Based on the predetermined address data and transfer signal from U3, one scan data (for example, data for 4096 dots) of the portion corresponding to the transfer address is read out of the image bit data written in the DPRAM8, and the parallel The data is transferred and output to the engine 10 via the serial conversion circuit 9, allowing printing on a predetermined position on the paper. The image information is transferred from the DPRAM 8 to the engine 10 by
This is performed by a timing signal T2 output from the timing generation circuit 15 based on a predetermined address designation from the CPU 3 and a transfer signal T1 from the address decoder 14 based on the front/back selection signal S. That is, one of the transfer address sections A or B is set in the address decoder 14 depending on whether the print side specified by the CPU 3 is the front side or the back side. Then, the address decoder 14 determines whether the data is a transfer command based on the read address data and the currently set transfer address, and if it is a transfer command, transfers the transfer signal T1 to the timing generation circuit. Output to 15. In response to this, the timing generation circuit 15
outputs signal T2 to DPRAM8 at a predetermined timing. In this way, the address decoder 14
If the selection signal S from S selects the front side, the transfer signal T
On the other hand, if the selection signal S selects the back side, the transfer signal T1 is output only when the address in the transfer address section B is specified. FIG. 3 (a>(b) shows CPU3, DPRAM8,
The situation of address inversion and data inversion of the print data part and transfer address part in one raster on the front and back sides in the engine 10 is shown. For normal paper sizes such as A4, C
Viewed from PU3, the print data area on the front side is 1 raster (
4096 dots) (0 to 15 dots are the non-image area, 16 to 2415 dots are the image area, and 24 dots are the image area.
The 16th to 4079th dot area is the non-image area), and the transfer address area is set to the right end (4080th to 4095th dot area). On the other hand, as mentioned above, on the back side, CPU3
Since the address inversion circuit 13 performs address inversion between the DP RAM 8 and the DPRAM 8, both the print data area and the transfer address area are set at positions opposite to the front surface. Furthermore, as can be seen from FIG. 3(b), the data on the back side is reversed horizontally in 16-bit units between the DPRAM 8 and the engine 10 by the data inverting circuit 16. )(c), Figure 5(a>(b)(c)
shows the concept of reversing the address and data on the front and back sides of the page memory 5, DPRAM 8, and engine 10.Here, an example where one character is 32 x 32 dots is shown, and the page memory 5 actually has is stored in code data format. As can be seen from Figure 5,
Regarding the data on the back side, the storage position of the data in the page memory 5 by the CPU 3 is reversed vertically in character units in advance, and when bits are expanded from the page memory 5 to the DPRAM 8, the row address is reversed vertically in units of 1 rask. ing. In this embodiment, this is done using program software. At the same time, the address inversion circuit 13 performs horizontal inversion of the column address in units of 16 bits. Also, when outputting from the DPRAM 8 to the engine 10, the data inversion circuit 16 converts the 16 pits into 1 bit.
The left and right sides are reversed bit by bit. As is clear from the above description, according to this embodiment, C
PtJ3 synchronizes with the transfer signal that is output in response to specifying the data on whether the print side is the front side or the back side and a predetermined address, and transfers the data on the front side to the transfer address section A (second
Data can be transferred to the engine 10 only when each address in the figure (Figure 2) and the address in the transfer address section B (Figure 2) for the data on the back side are specified correctly, so erroneous transfers may occur. Things will go away.

Furthermore, the data from the D P RAM 8 is converted into serial data by the serial-to-parallel converter circuit 9 through a forward connection or reverse connection made by the hardware of the data inversion circuit 16 in units of 16 bits, and then sent to the controller of the engine 10. It is now output. Now, if we were to arrange this kind of 16-bit data using software, it would require 16 shift operations, which would take time, but doing it in hardware would reduce the burden on the software. First, it is possible to significantly shorten the operating time.

In the above embodiment, the vertical inversion is performed by the CPU program, and the horizontal inversion in units of 1 bit within a predetermined data unit is performed by the data inversion circuit 16. The means for this can be configured as appropriate. [Effects of the Invention] As described above, according to the present invention, when performing horizontal and vertical inversion of the image required in the back side printing mode in a double-sided printing device, especially when developing data on an image buffer, Regarding horizontal inversion, the hardware configuration in which an address conversion circuit is interposed in the address bus for the image buffer in which bit data is developed is used to perform horizontal inversion of data, which greatly reduces the load on the CPU. At the same time, the operating time can be shortened. Furthermore, this hardware configuration is simple, and together with the burden placed on software, costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a double-sided printing device according to an embodiment of the present invention, and FIGS. 2(a) and 2(b) are CPUs in the same device.
Figures 3(a) and 3(b) are diagrams showing the storage state of data on the Karamina Image Bar Sofa, and Figures 4(a) and 4(a) are diagrams showing the address and data reversal status of data for one rask on the front and back sides. )<b)(C) and FIGS. 5(a), 5(b), and 5(c) are conceptual diagrams showing the reversal of images on the front and back sides, respectively. 3.
...CPU, 5...Page memory, 8...DPRA
M (image buffer), 10...printing mechanism section, 12
... Address bus, 13... Address inversion circuit (address conversion circuit), 16... Data inversion circuit, S...
・Selection signal for front and back sides. Applicant: Brother Industries, Ltd. Agent: Patent Attorney: Yasuo Itaya No. J Figure +6 1-':7)-

Claims (1)

[Claims] (1) A page memory in which code data such as characters and figures is stored, an image buffer in which bit data corresponding to the code data in this page memory is developed, and one scan of the bit data developed in the image buffer. A raster scan type double-sided printer that is equipped with a printing mechanism that sequentially receives data output and performs printing operations, and a CPU that controls all of these, and has a back-side printing mode that prints images such as characters and figures by flipping them horizontally and vertically. In the printing device,
When setting the back side printing mode, means for vertically inverting a row address indicating a vertical address in a predetermined data unit; means for horizontally inverting a column address indicating a horizontal address in a predetermined data unit; means for performing left-right reversal in 1-bit units in predetermined unit data that has been left-right reversed, and the means for performing left-right reversal in the predetermined unit data includes an address between the CPU and the image buffer. A raster scan type double-sided printing device characterized by an address conversion circuit interposed in a bus.