JPH02296314A - Manufacture of chip component - Google Patents
Manufacture of chip componentInfo
- Publication number
- JPH02296314A JPH02296314A JP1116958A JP11695889A JPH02296314A JP H02296314 A JPH02296314 A JP H02296314A JP 1116958 A JP1116958 A JP 1116958A JP 11695889 A JP11695889 A JP 11695889A JP H02296314 A JPH02296314 A JP H02296314A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- electrode film
- outermost
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電子機器の小型化・軽量化・薄形化に寄学する
電子回路部品の一種である積層セラミックコンデンサな
どのチップ部品の製造方法に1関す2、−7
るものである。[Detailed Description of the Invention] Industrial Application Field The present invention relates to a method for manufacturing chip components such as multilayer ceramic capacitors, which are a type of electronic circuit component that contributes to the miniaturization, weight reduction, and thickness reduction of electronic devices. This is related to 2.-7.
従来の技術
近年、電子機器の軽薄短小化に伴い、積層セラミックコ
ンデンサなどのチップ部品の需要がますます高まりつつ
ある。このようなチップ部品におりて、本発明者らは先
に特開昭63−15401号公報にて、端子電極部の表
面を平滑にし、プリント基板に実装する際における半田
付けの信頼性を向上させるようにした構造を提案した。BACKGROUND OF THE INVENTION In recent years, as electronic devices have become lighter, thinner, and smaller, demand for chip components such as multilayer ceramic capacitors has been increasing. Regarding such chip components, the present inventors previously reported in Japanese Unexamined Patent Application Publication No. 15401/1983 that the surface of the terminal electrode portion is made smooth to improve the reliability of soldering when mounting on a printed circuit board. We proposed a structure that allows
このチップ部品の製造工程を積層セラミックコンデンサ
を例にとり、第2図(A)〜(D)と共に説明する。ま
ず、例えばチタン駿バリウムなどのセラミック誘電体の
表面に内部電極としてPdなとのit合金系のメタルグ
レーズペーストラスクリーン印刷法により所定の形状に
塗布し、これを順次操り返してセラミック誘電体と内部
電極が交互に積層したシートを作)、このシートを必要
とする寸法の個片状に打抜き加工し、相対1i5]する
端面部に交互に内部電極が露出したコンデンサ素子材料
を作った。これを1aoo’cの高温で焼成して、積層
され、かつ焼11@された個片状のセラミックコンデン
サ素子を作製した。第21図(ム)は上記のようにして
作製されたセラミックコンデンサ素子であシ、1はセラ
ミック誘電体、2はPb系系内型電極ある。The manufacturing process of this chip component will be explained using a multilayer ceramic capacitor as an example, with reference to FIGS. 2(A) to 2(D). First, a metal glaze paste based on IT alloys such as Pd is coated as an internal electrode on the surface of a ceramic dielectric such as titanium or barium using a screen printing method, and this is sequentially manipulated to form a ceramic dielectric. A sheet in which internal electrodes were alternately laminated was produced), and this sheet was punched into individual pieces of the required dimensions to produce a capacitor element material in which internal electrodes were exposed alternately on the opposite end faces. This was fired at a high temperature of 1 aoo'c to produce laminated and fired ceramic capacitor elements in the form of individual pieces. FIG. 21(m) shows a ceramic capacitor element manufactured as described above, in which 1 is a ceramic dielectric and 2 is a Pb-based internal type electrode.
次に、第2図(B)に示すように上述した如くして作っ
た個片状のセラミックコンデンサ素子の両端部に導電1
生金属であるAgペーストを塗布、焼付けしてAg系電
極膜3を形成した。ここではAgを使用しているが、C
u、 Niおよびそれらの合金など、導電1生をもつも
のであれば使用可能である。Next, as shown in FIG. 2(B), a conductive wire is attached to both ends of the individual piece-shaped ceramic capacitor element made as described above.
Ag paste, which is a raw metal, was applied and baked to form an Ag-based electrode film 3. Although Ag is used here, C
It is possible to use materials that have electrical conductivity, such as U, Ni, and alloys thereof.
次いで、第2図(G)に示すように上述した如くAg系
電極膜3を両端部に形成したセラミックコンデンサ素子
の両端部の上記Ag系電極暎3の上にバレルメッキ法に
より、導電性金属であるN1を用い、Ni膜4を厚さ3
〜5μmにて形成した。Next, as shown in FIG. 2(G), conductive metal is deposited by barrel plating on the Ag-based electrode layers 3 at both ends of the ceramic capacitor element having the Ag-based electrode films 3 formed at both ends as described above. Using N1, the Ni film 4 has a thickness of 3
It was formed at ~5 μm.
次に、第2fl(D)に示すようにセラミックコンデン
サ素子の両端部のNi膜4の上に同じくバレルメッキ法
により、導電性金属であるSnまたはSnとPbの合金
を用論、半田膜5を厚さ3〜5μmにて形成した。Next, as shown in the second fl (D), a conductive metal such as Sn or an alloy of Sn and Pb is applied to the Ni film 4 at both ends of the ceramic capacitor element by the same barrel plating method. was formed with a thickness of 3 to 5 μm.
その後、端子電極部の最外層金属膜である半田膜5の融
点より高温で加熱溶融処理を施し、第2図(E)に示す
ように最外層部・成膜としての半田1模5aを形成する
ことにより、積層セラミックコンデンサを作製していた
。ここで、上記加熱溶融処理は上述した特開昭63−1
5401号公報に示されるように、例えば第2図(D)
に示す状態に作製されたセラミックコンデンサ素子をロ
ジン系フラックスに浸漬した後、半田膜5の融へよりも
高い温度にてカ典処浬を行うことにより、端子電極部の
最外層部に再溶融金属膜からなる半田膜5&を形成する
ことができる。Thereafter, heating and melting treatment is performed at a temperature higher than the melting point of the solder film 5, which is the outermost layer metal film of the terminal electrode part, to form a solder 1 pattern 5a as the outermost layer and film, as shown in FIG. 2(E). By doing so, a multilayer ceramic capacitor was manufactured. Here, the above-mentioned heating and melting treatment is performed in the above-mentioned Japanese Patent Application Laid-open No. 63-1
As shown in Publication No. 5401, for example, FIG. 2(D)
After immersing the ceramic capacitor element manufactured in the state shown in , in a rosin-based flux, the outermost layer of the terminal electrode part is remelted by performing a heat treatment at a temperature higher than the melting temperature of the solder film 5. A solder film 5& made of a metal film can be formed.
また、半田j摸5(6a)の下地(ここではN1嘆4)
はこの半田膜5(5a)よりも融点が高くしかもこの半
田膜5(5a)と親和性の良い金属材料で構成されてい
ることが必要である。Also, the base of Handa j 5 (6a) (here N1 4)
It is necessary that the metal material has a higher melting point than the solder film 5 (5a) and has good affinity with the solder film 5 (5a).
発明が解決しようとする課題
しかしながら、このような本発明者らが先に提案したチ
ップ部品の製造方法では、端子電極部の最外層電極膜で
ある半田膜6を加熱溶副(した際に表面張力による溶融
金属の移動が起シ、角部における1模厚がなくなってし
まうという事態が発生していた。このため、第21図(
E)に示すように上記最外層電極膜の角部Aにおいては
、最外層電極膜である半田j摸5(5a)の方から敢え
て第2層目の金属膜、すなわちN1膜4が露出した状態
となり、この金属膜(Ni+摸4)の酸化などによりプ
リント基板への実装半田付は時に、その部分へは半田が
付着しないという半田付は不良が不良する可能性が犬で
あるという問題点を有していた。Problems to be Solved by the Invention However, in the method of manufacturing a chip component previously proposed by the present inventors, the solder film 6, which is the outermost electrode film of the terminal electrode part, is heated and melted (when the surface is A situation occurred in which the molten metal moved due to the tension, and the thickness of the molten metal at the corners was lost.
As shown in E), at the corner A of the outermost electrode film, the second metal film, that is, the N1 film 4, was deliberately exposed from the solder layer 5 (5a), which is the outermost electrode film. Due to the oxidation of this metal film (Ni+Picture 4), mounting solder on the printed circuit board is sometimes difficult, and soldering does not adhere to that part, which is a problem. It had
本発明はこのような間頂点を解決しようとするもので、
実装半田付は時における半田付は不良が発生することの
ないチップ部品の製造方法を提供することを目的とする
ものである。The present invention attempts to solve this problem,
The purpose of mounting soldering is to provide a method for manufacturing chip components that does not cause defects.
課題を解決するだめの手段
この課9項を解決するだめに本発明は、機能素子の両4
部に少なくとも一層以上の電極1漠の下地となるSnま
たはSnとPbの合金以外の金4からなる導電1金属膜
を形成し、さらに前記下地の導6 ベーノ
電性金属膜の上に設けられる電極膜の最外層電極膜をそ
の融点が前記最外層電極膜の方から数えて第2層目のS
nまたはSnとPbの合金からなる電極膜の層1点より
低いSnとPbの合金にて形成した後、前記最外層電極
膜の融点と前記最外層電極膜の方から数えて第2層目の
電極膜の継面の中間温度で加熱溶融処理を施すようにし
だものである。Means for Solving the Problems In order to solve the problem in section 9, the present invention provides two functional elements.
A conductive metal film made of gold other than Sn or an alloy of Sn and Pb is formed on at least one layer of the conductive metal film as a base for the electrode 1, and a conductive metal film is formed on the base conductive metal film. The outermost electrode film of the electrode film has a melting point S of the second layer counting from the outermost electrode film.
layer of an electrode film made of an alloy of Sn or Sn and Pb. After forming an alloy of Sn and Pb with a lower temperature than one point, a second layer counting from the melting point of the outermost electrode film and the outermost electrode film is formed. The electrode film is heated and melted at an intermediate temperature on the joint surface of the electrode film.
作用
この製造方法によれば、端子電極部の最外層部の金属膜
が加熱溶融されているため、溶融時に働く表面張力によ
り表面積が加熱溶融前より小さくなり、これにより表面
が平滑化され、保存中に異物の付着やガスの吸着が極端
に減少し、長期間の保存に対しても半田付けの信頼面を
確保することができる。また、溶融時に表面あるいはく
ぼみの内部に・吸着・吸蔵していた異物、ガス類も放出
されるため、最外層の膜自体も不純物を含まない清潔な
嘆となり、半田膜れ性および半田付は信頼性の向上につ
ながることとなる。そして、加熱溶融処理は最外層電極
膜の融点とこの最外層電極膜の方から数えて第2層目の
電極膜の融点の中間の温度で行うため、溶融されるのは
最外層電極膜のみであり、表面張力による溶融金属の移
動が起った場合、角部において露出するのは最外層電極
膜の方から数えて第2層目の電極膜であるが、この第2
層目の電極膜もSnまたはSn とPbの合金で形成さ
れていることにより、ブリ/ト基板への実装半田付は時
に角部へは半田が付着しないという半田付は不良が発生
することはなく、半田付けによる信頼性を向上させるこ
とができることとなる。Effect: According to this manufacturing method, since the metal film of the outermost layer of the terminal electrode is heated and melted, the surface area becomes smaller than before heating and melting due to the surface tension that acts during melting, which smooths the surface and makes it easier to store. The adhesion of foreign matter and adsorption of gas inside the product are extremely reduced, ensuring reliable soldering even during long-term storage. In addition, since foreign substances and gases that have been adsorbed or occluded on the surface or inside the recesses are released during melting, the outermost layer itself becomes clean and free of impurities, and the solder film brittleness and solderability are reduced. This will lead to improved reliability. Since the heating and melting treatment is performed at a temperature between the melting point of the outermost electrode film and the melting point of the second electrode film counting from this outermost electrode film, only the outermost electrode film is melted. When molten metal moves due to surface tension, it is the second layer of electrode film counted from the outermost electrode film that is exposed at the corner.
Since the electrode film in the second layer is also made of Sn or an alloy of Sn and Pb, there is no possibility that soldering defects may occur when soldering to a printed circuit board, where the solder sometimes does not adhere to the corners. Therefore, the reliability of soldering can be improved.
実施例
以下、本発明の一実施例について図面を参照しながら説
明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
第1図(ム)〜(I’)は本発明の一実施例による積層
セラミックコンデンサの製造工程を示す断面図であ〕、
端子電極部分を形成する工程を主体的に示してしる。FIGS. 1(M) to (I') are cross-sectional views showing the manufacturing process of a multilayer ceramic capacitor according to an embodiment of the present invention.
The process of forming the terminal electrode portion is mainly shown.
第1図(ム)〜(F)において、1はセラミック誘電体
、2はPd系内部屯極、3はAg系電極膜、4はNi膜
であり、これらは第2図の従来例と同一のものである。In Figs. 1 (M) to (F), 1 is a ceramic dielectric, 2 is a Pd-based internal electrode, 3 is an Ag-based electrode film, and 4 is a Ni film, which are the same as the conventional example in Fig. 2. belongs to.
また、6はSn膜、7はSnとPbの組成比が60 :
40である半田膜、71Lは加熱溶融処理されたSn
とPbの組成比が60:40である半田膜である。Further, 6 is a Sn film, and 7 is a Sn film with a composition ratio of Sn and Pb of 60:
40 is the solder film, 71L is Sn that has been heat-melted.
The solder film has a composition ratio of Pb and Pb of 60:40.
次に、本実施例による積層セラミックコンデンサの製造
工程を説明する。まず、第1図(ム)〜(G)までの工
程は、従来例の第2図(ム)〜(0)までの工程と同じ
であり、説明は省略する。そして次に両端部にdi膜4
を形成したセラミックコンデンサ素子の上記両端部の上
記Ni膜4の上に、第1図(D)に示すようにバレルメ
ッキ法によシ、導電性金属であるSnを用い、Sn膜6
を厚さ3〜6μmにて形成した。次いで、第1図IC)
に示すように上述した如(Sn膜7を形成したセラミッ
クコンデンサ素子の両端部のSn膜6の土に、同じくバ
レルメッキ法によシ、導電性金属であるSnとPbの組
成比が60:40である半田を用^、半田膜7を厚さ1
〜2μmに形成した。Next, the manufacturing process of the multilayer ceramic capacitor according to this example will be explained. First, the steps from FIG. 1(M) to FIG. 1(G) are the same as the steps from FIG. 2(M) to (0) of the conventional example, and the explanation thereof will be omitted. Then, DI film 4 is placed on both ends.
As shown in FIG. 1(D), a Sn film 6 is deposited on the Ni film 4 on both ends of the ceramic capacitor element formed with Sn, which is a conductive metal, by barrel plating.
was formed with a thickness of 3 to 6 μm. Then, Fig. 1 IC)
As shown in FIG. 2, the soil of the Sn film 6 on both ends of the ceramic capacitor element having the Sn film 7 formed thereon was coated with the same barrel plating method, and the composition ratio of Sn and Pb, which are conductive metals, was 60: Use a solder with a thickness of 40, and a solder film with a thickness of 1
It was formed to have a thickness of ~2 μm.
次に、上述したようにSnとPbの組成比が60 :
40である半田膜7を両端部に形成したセラミックコン
デンサ素子に対し、加熱溶融処理を施すことによシ、第
1図(F)に示すように加熱溶融処理されたSnとPb
の組成比が60 : 40である半田膜7aが形成され
る。本実施例における上記加熱溶融処理は、やはり本発
明者らが先に提案した特開昭63−29905号公報に
開示されている通り、ガラス製の筒状容器に高沸点液体
であるやし油を入れ、その容器中におけるやし油に下方
へいくのにしたがい低温となる温度勾配をもたせ、上記
容器中におけるやし油の高温部側よシ低温部側に第1図
(IC)に示すように両端部の最外層に半田膜7が形成
されたセラミックコンデンサ素子を移動させ、高温部に
て上記SnとPbの組成比が60: 40である半田膜
7を溶融させ、低温部にて冷却、固化させることにより
半田膜7aを形成する方法で行った。ここで、加熱溶融
処理部となる高温部の温度は、最外層部の方よシ数えて
第1層目である上記SnとPbの組成比が60:40で
ある半田膜7の融点(1sa’c)とその最10ページ
外層部の方よシ数えて第2層目である上記Sn膜6の融
点(232’C)の中間の温度である200 ℃とし、
溶融時間は1.5秒間とした。Next, as mentioned above, the composition ratio of Sn and Pb is 60:
By subjecting a ceramic capacitor element having a solder film 7 of No. 40 formed on both ends thereof to heat-melting treatment, the heat-melted Sn and Pb as shown in FIG.
A solder film 7a having a composition ratio of 60:40 is formed. The above-mentioned heating and melting treatment in this example was carried out using coconut oil, which is a high-boiling liquid, in a glass cylindrical container, as disclosed in Japanese Patent Application Laid-Open No. 63-29905, which was previously proposed by the present inventors. The coconut oil in the container is made to have a temperature gradient that becomes lower as it goes downwards, and the coconut oil in the container is heated from the high temperature side to the low temperature side as shown in Figure 1 (IC). The ceramic capacitor element with the solder film 7 formed on the outermost layer at both ends is moved as shown in FIG. The solder film 7a was formed by cooling and solidifying the solder film 7a. Here, the temperature of the high-temperature part, which is the heat-melting processing part, is the melting point (1 sa 'c) and the melting point (232'C) of the Sn film 6 which is the second layer counting from the outer layer part of the top 10 page, which is 200 °C,
The melting time was 1.5 seconds.
下記の第1表に、以上の説明と同様の方法にて各種の端
子電極構造をもつ試料を作製し、その時の加熱溶融処理
温度や、角部のSn膜またはSnとPbの合金膜の切れ
巾、86℃、85に湿中糟に240時間投入後の半田付
は信頼性、半田濡れ時間を示している。第1表中に示す
試料1が上記実施例によるものである。ここで、角部の
Sn膜またはSnとPbの合金膜の切れ巾は、セラミッ
クコンデンサ素子を断面研磨し金属顕微鏡を用いて測定
した。また、半田付は信頼性は半田の付着しない部分の
面積が端子電極部全体の6%以上に及ぶものを不良品と
した。また、半田濡れ時間はメニスコグラフ法にて測定
した。なお、表中の端子電極構造は、最外層部の方から
数えた層数と各層の成分を示している。Table 1 below shows samples with various terminal electrode structures prepared by the same method as explained above, and the heating melting treatment temperature and the breakage of the Sn film or Sn and Pb alloy film at the corners. Width, soldering after being placed in a humid bath at 86° C. and 85° C. for 240 hours shows reliability and solder wetting time. Sample 1 shown in Table 1 is based on the above example. Here, the cutting width of the Sn film or the alloy film of Sn and Pb at the corners was measured by polishing the cross section of the ceramic capacitor element and using a metallurgical microscope. In addition, regarding soldering reliability, those in which the area of the part to which no solder adhered accounted for 6% or more of the entire terminal electrode part were judged to be defective. Further, the solder wetting time was measured by the meniscograph method. Note that the terminal electrode structure in the table shows the number of layers counted from the outermost layer and the components of each layer.
上記第1表に示したように、端子電極荷造が最外層部側
から見て、Snまだは3nとPbの合金の単独層と、S
nまたはSnとPbの合金以外の金属j摸とからそれぞ
れ第1層目と第2層目が溝底されている試料4.5のよ
うな場合には、角部のSn膜まだはSnとPbの合金膜
の切れが生じ、半田付は不良が多く発生した。また、加
熱溶融処理の温度を最外層部の方から数えて第1層目お
よび第2層目の電極膜の融点より高温で行った試料6の
ような場合にも同様に半田付は不良が多く発生した。As shown in Table 1 above, when the terminal electrode packaging is viewed from the outermost layer side, there is a single layer of Sn, a single layer of 3N and Pb alloy, and S
In the case of sample 4.5, in which the first and second layers are made of a metal other than n or an alloy of Sn and Pb, respectively, the Sn film at the corner part is not yet Sn. Breaks occurred in the Pb alloy film, and many soldering defects occurred. Furthermore, even in cases such as sample 6, where the heating and melting treatment was performed at a temperature higher than the melting point of the first and second layer electrode films, counting from the outermost layer, the soldering was also defective. It happened a lot.
そして、最外層電極膜をSnとPbの合金にて形成し、
その最外層部4膜の方から数えて第2層目の電極膜をS
nまたはSnとPbの合金とから形成し、かつ最外層電
極膜の融点を第2層目の電極膜のそれより低いものとし
、しかも両者の融点の中間の温度で加熱4融処理を施し
た本発明にかかる試料1,2.3は、それぞれ第1表に
示すように良好な特[生結果が得られている。また、試
料2においては、最外層部の方から数えて第3層目にS
n膜を設け、その下に上述したN1膜、Ag系電極膜を
形成してAる例であり、この場合は最外層部の方から范
て第1層目のsV九=’e○/40の半田膜より第2層
目のSn/Pb =90/10の半田膜の方の融点が高
く、さらに第2層目のSn/Pb−90/10の半田膜
より第3層目のSn膜の方の融点が高AものとなってA
る。Then, the outermost electrode film is formed of an alloy of Sn and Pb,
The second electrode film counting from the outermost 4 films is
The outermost electrode film was formed from an alloy of n or Sn and Pb, and the melting point of the outermost electrode film was lower than that of the second electrode film, and was subjected to heating 4 melting treatment at a temperature between the melting points of both. Samples 1 and 2.3 according to the present invention had good characteristic results as shown in Table 1, respectively. In addition, in sample 2, S was found in the third layer counting from the outermost layer.
This is an example in which an N film is provided, and the above-mentioned N1 film and Ag-based electrode film are formed below it. The second layer Sn/Pb = 90/10 solder film has a higher melting point than the second layer Sn/Pb-90/10 solder film, and the third layer Sn/Pb-90/10 solder film The melting point of the membrane is high A
Ru.
なお、上記の実施例では積層セラミックコンデンサにつ
・ハてのみ説明しだが、本発明はこれに限定されるもの
ではなく、角板状チップ抵抗器などでも同様の効果が得
られるものである。また、端子電極部に形成するSn
まだはSnとPbの合金からなる少なくとも2層の電極
膜の下地は、主起実施例におけるN1膜とAg系電極膜
に限定されるものではなく、例えばCu暎とAg −P
b合金1僕の組み合せなどでもよく、要は少なくとも一
層以上のSnまだはSnとPbの合金以外のa属からな
る導電性金属膜が設けられていればよいものである。In the above embodiment, only a multilayer ceramic capacitor was described, but the present invention is not limited thereto, and similar effects can be obtained with a square plate-shaped chip resistor. In addition, the Sn formed on the terminal electrode part
The base of the at least two electrode films made of an alloy of Sn and Pb is not limited to the N1 film and the Ag-based electrode film in the main example.
A combination of B-alloy, 1-Pb alloy, etc. may be used, and the point is that at least one conductive metal film consisting of Sn and a-group other than the alloy of Sn and Pb is provided.
発明の効果
14 /、−7
以上のように本発明によれば、端子電極部の最外層電極
膜をその融点が前記最外層電極膜の方から数えて第21
−目のSnまたはSnとPbの合金からなる電極膜の融
点より低いSnとPbの合金にて形成した後、前記最外
層電極膜と前記最外層電極膜の方から数えて第2層目の
電極1摸の融点の中間温度で加熱溶融処理を施すことに
より、半田濡れ性の改善と長期の保存に対しての半田付
けによる信頼性が向上するという効果が得られる。特に
、加熱溶融処理は最外層部の方から数えて第1層目の電
極膜の融点と第2層目の電極膜の融点の中間は度で行っ
たため、溶融されるのは融点の低い最外層重+i、膜の
みであり、表面張力による宕融金属の移動が起った場合
、角部において露出するのは最外層部の方から数えて第
2層目の′電極膜もSnまたはSnとPb の合金か
ら形成されていることにより、プリント基板への実装半
田付は時に角部へは半田が付着しないという半田付は不
良が発生することはなくなシ、半田付けによる信頼性を
向上させることができるという効果が得られる。Effect of the Invention 14 /, -7 As described above, according to the present invention, the outermost electrode film of the terminal electrode portion has a melting point of 21st as counted from the outermost electrode film.
- After forming the electrode film with Sn or an alloy of Sn and Pb whose melting point is lower than the melting point of the electrode film made of an alloy of Sn and Pb, a second layer counting from the outermost electrode film and the outermost electrode film is formed. By heating and melting the electrode at a temperature intermediate to the melting point of the electrode, it is possible to improve the solder wettability and the reliability of soldering for long-term storage. In particular, since the heating and melting treatment was carried out at a temperature between the melting point of the first layer electrode film and the melting point of the second layer electrode film, counting from the outermost layer, the melting point was the lowest melting point. The outer layer weight + i is only the film, and if the molten metal moves due to surface tension, the electrode film of the second layer counting from the outermost layer is also Sn or Sn exposed at the corner. By being made of an alloy of Pb and Pb, soldering defects that sometimes occur when soldering to printed circuit boards does not adhere to the corners, and the reliability of soldering is improved. This has the effect of being able to do this.
第1図(ム)〜(F)は本発明方法にかかる積層セラミ
ツクコ/アンサの製造工程を示す断面図、第2図(ム)
〜(IC)は従来例における積層セラミックコンデンサ
の実速工程を示す断面図である。
1・・・・・セラミック誘電体、2・・・・・・Pd系
内部電極、3・・・・・・Ag系電極膜、4・・・Ni
膜、6・・・・8n膜、7 + 71L ・・・半田
膜。Figures 1 (M) to (F) are cross-sectional views showing the manufacturing process of a laminated ceramic wolf/answer according to the method of the present invention, and Figure 2 (M)
~(IC) is a sectional view showing an actual speed process of a multilayer ceramic capacitor in a conventional example. 1...Ceramic dielectric, 2...Pd-based internal electrode, 3...Ag-based electrode film, 4...Ni
Film, 6...8n film, 7+71L...solder film.
Claims (1)
となるSnまたはSnとPbの合金以外の金属からなる
導電性金属膜を形成し、さらに前記下地の導電性金属膜
の上に設けられる電極膜の最外層電極膜をその融点が前
記最外層電極膜の方から数えて第2層目のSnまたはS
nとPbの合金からなる電極膜の融点より低いSnとP
bの合金にて形成した後、前記最外層電極膜の融点と前
記最外層電極膜の方から数えて第2層目の電極膜の融点
の中間温度で加熱溶融処理を施すようにしたチップ部品
の製造方法。A conductive metal film made of a metal other than Sn or an alloy of Sn and Pb is formed on both ends of the functional element as a base for at least one electrode film, and further an electrode is provided on the conductive metal film as the base. The outermost electrode film of the film is Sn or S whose melting point is the second layer counting from the outermost electrode film.
Sn and P are lower than the melting point of the electrode film made of an alloy of n and Pb.
A chip component formed of the alloy of (b) and then heated and melted at a temperature between the melting point of the outermost electrode film and the melting point of the second electrode film counted from the outermost electrode film. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1116958A JP2730173B2 (en) | 1989-05-10 | 1989-05-10 | Manufacturing method of chip parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1116958A JP2730173B2 (en) | 1989-05-10 | 1989-05-10 | Manufacturing method of chip parts |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02296314A true JPH02296314A (en) | 1990-12-06 |
| JP2730173B2 JP2730173B2 (en) | 1998-03-25 |
Family
ID=14699950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1116958A Expired - Fee Related JP2730173B2 (en) | 1989-05-10 | 1989-05-10 | Manufacturing method of chip parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2730173B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04219913A (en) * | 1990-12-19 | 1992-08-11 | Kiyokawa Mekki Kogyo Kk | Brazed two-layer structure electrode of electronic element |
| JP2005294618A (en) * | 2004-04-01 | 2005-10-20 | Kyocera Corp | Electronic components |
-
1989
- 1989-05-10 JP JP1116958A patent/JP2730173B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04219913A (en) * | 1990-12-19 | 1992-08-11 | Kiyokawa Mekki Kogyo Kk | Brazed two-layer structure electrode of electronic element |
| JP2005294618A (en) * | 2004-04-01 | 2005-10-20 | Kyocera Corp | Electronic components |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2730173B2 (en) | 1998-03-25 |
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