JPH02296366A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate ion implantation by etching a second layer gate electrode material formed on a semiconductor substrate surface, an insulating layer surface, and the upper surface of first layer gate electrodes as far as the upper surface of the first layer gate electrodes, eliminating the insulating layer, and forming a second layer gate electrodes between the first layer gate electrodes. CONSTITUTION:After an insulating layer 6 is formed on the surface of a semiconductor substrate and the surface of a first layer gate electrodes 5 formed on the said substrate surface, the insulating layer 6 is anisotropically etched, and left only on the side surfaces of the first layer gate electrodes 5; a second layer gate electrode material 8 is deposited on the surface of the left insulating, layer 6, the upper surface of the first layer gate electrodes 5, and the surface of the semiconductor substrate 1; said material 8 is etched almost as far as the upper surface of the first layer gate electrodes 5; then the left insulating layer 6 is eliminated, thereby forming a second layer gate electrode 8a between the first layer gate electrodes 5. As a result, the first layer gate electrodes 5 and the second layer gate electrodes 8a do not overlap, so that unevenness is not present on the upper surface of the semiconductor substrate 1 and a flat structure is obtained. Thereby ion implantation is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device with highly integrated gate electrodes.

<Prior Art> In order to increase the integration of semiconductor devices, there is a limit to miniaturization of only one layer of gate electrodes, and a two-layer gate electrode structure has been used. In such a semiconductor device, as shown in FIG.
), a first layer gate electrode 3a and a second layer gate electrode 4a are provided on the Si substrate 1a, and a second layer gate electrode 3a is provided on the first layer gate electrode 3a for high integration. A second layer gate electrode 4a is formed so as to partially overlap the second layer gate electrode 4a. Then, Si is formed around the gate electrodes 3a and 4a.
An O□ film 2a is formed. Incidentally, FIG. 2(b) shows a case where a margin for alignment is provided between the gate electrodes 3a and 4a in order to avoid overlapping of the gate electrodes 3a and 48 described above.

<Problems to be Solved by the Invention> The semiconductor device illustrated in FIG. 2 has the following problems. That is, in the semiconductor device shown in FIG. 2(a), a part of the second layer gate electrode overlaps the first layer gate electrode, and the surface of the substrate is extremely uneven, so it is difficult to process such a surface. Moreover, this ion implantation becomes difficult in a semiconductor device in which ion implantation is performed from above the gate electrode after the gate electrode is formed. Further, in the semiconductor device shown in FIG. 2tb>, the surface of the substrate can be made flat, but the gate electrode cannot be highly integrated.

The present invention was created in view of the above circumstances, and includes:
By forming the layered gate electrodes using self-alignment technology, we have a more planar structure even though the electrodes are extremely integrated, and we can also improve An object of the present invention is to provide a method for manufacturing a semiconductor device that can store data by ion implantation.

<Means for Solving the Problems> In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention includes forming an insulating layer on the side surface of the first layer gate electrode formed on the surface of the semiconductor substrate, and then A material for the second layer gate electrode is formed on the surface, the surface of the insulating layer, and the upper surface of the first layer gate electrode, and then this material is etched to almost the top surface of the first layer gate electrode, and then the insulating layer is removed. A first layer gate electrode and an upper layer second layer gate electrode are formed.

<Operation> After forming an insulating layer on the surface of the semiconductor substrate and the surface of the first layer gate electrode formed on this surface, this insulating layer is anisotropically etched so that only the side surface of the first layer gate electrode is etched. Leaving the insulating layer, a 2Nth gate electrode material is deposited on the surface of the remaining insulating layer, the top surface of the first layer gate electrode, and the surface of the semiconductor substrate, and then this material is deposited on the surface of the first layer gate electrode. After etching up to the second surface, the remaining insulating layer is removed to form a second layer gate electrode between the first layer gate electrodes. Therefore, since the gate electrodes of the first layer and the second layer do not overlap, the top surface of the semiconductor substrate has a flat structure without any unevenness, and ions can be easily implanted from above the gate electrode.

<Example> Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a drawing for explaining this embodiment, in which FIG. 1(a) is a perspective view of a semiconductor device, and FIG. 1(b) to (i) are cross-sectional explanations at each manufacturing stage of the semiconductor device. A diagram,
It is a figure corresponding to the sectional view taken along the line A-A in FIG. 1(a).

As shown in FIG. 1(a), the S i 45 plate 1-. 1-
After forming a SiO□ film 2 to a thickness of approximately 300 mm in a high-temperature oxygen atmosphere, a linear pattern 20 is formed by photolithography, and then a MOS (MOS) transistor is formed using ion 1 using this pattern 20 as a mask. Source and drain regions 3 are formed on the surface of the Si substrate 1.

Next, after removing the pattern 20 and the SiO□ film 2,
In a high temperature oxygen atmosphere, as shown in FIG. 1(b), a gate thin film 4 of S+Oz film having a thickness of 100 to 300 wafers is formed. Then, on this Day 1 to Thin Film 4,
The first layer gate electrode 5 is patterned by lithography and etching.

After this, as shown in FIG. 1(C), an SjO□ film 6 is formed to a thickness of 2000 to 6000 nm on the surface of the Si substrate 1 and the surface of the Day 1 electrode 5 by chemical vapor deposition. Thereafter, as shown in FIG. 1(d), the 5i02 film 6 is etched to the desired thickness by anisotropic etching, leaving the SiO□ film 6 only on the side surfaces of the gate electrode 5.

Next, the exposed gate thin film 4 is removed, and the removed portion has a thickness of 100 to 30 mm, as shown in FIG.
A gate thin film 7 of 0 5iOz film is formed.

Furthermore, as shown in FIG. 1(f), gate thin films 7 and S
An electrode material 8 is deposited on the surface of each of the tO□ film 6 and the gate electrode 5 as a second layer gate electrode gate 1, and a low viscosity material 9 such as a photoresist is coated on this gate electrode material B.

After this, as shown in FIG. 1(h), the low viscosity material 9 and gate electrode material 8 are etched to the upper surface of the first layer gate electrode 5 by anisotropic etching. As shown, the first layer gate electrode 5 and the second layer gate electrode material 8
The 5iOz film 6 between the gate electrodes 5 and 5 is removed by wet etching, and the second layer gate I/electrode 8 is removed between the first layer gate electrode 5.
After forming gate electrodes 5 and 8a, an impurity 10 (for example, boron) is added as a channel stopper between gate electrodes 5 and 8a.
ion implantation.

Next, a 5iOz film is formed by oxidation in a high-temperature oxygen atmosphere, or NSG is deposited on the substrate surface by chemical vapor deposition.
An insulating film 11 such as PSG, BPSG, etc. is formed. Finally, a desired semiconductor device can be obtained by patterning electrode openings and electrode wiring (not shown).

<Effects of the Invention> As explained in Section 2 below, the method for manufacturing a semiconductor device of the present invention includes forming an insulating layer on the side surface of the electrode on the first layer gate 1 formed on the surface of the semiconductor substrate, and then forming the insulating layer on the side surface of the electrode. , a material for the second layer gate electrode is formed on the surface of the insulating layer and the upper surface of the first layer gate electrode, and then this material is etched to almost the top surface of the first layer gate electrode, and then the insulating layer is removed. 1 layer
”A second layer of gate electrodes is formed between the gate electrodes.

Therefore, according to the present invention, by forming the second layer gate electrode between the first layer gate electrodes using self-alignment technology, the gate electrodes can be made planar even though they are highly integrated. Because of the structure, the surface can be easily processed, and a semiconductor device in which data can be stored can be manufactured by performing ion implantation from above the gate electrode after forming the gate electrode.

[Brief explanation of drawings]

FIG. 1 is a drawing for explaining this embodiment, and the first
Figure (a) is a perspective view of a semiconductor device, showing a state in which a pattern has been formed for impurity implantation. FIGS. 1(b) to 1(i) are cross-sectional explanatory views at each manufacturing stage of the semiconductor device, and this cross-section is taken along the line AA in FIG. 1(a).
Corresponds to the cross section indicated by the line arrow. Figure 1(b) shows the state in which the first layer gate electrode is formed, Figure 1(C) shows the state in which the insulating layer is formed on the substrate and the first layer gate electrode, and Figure 1(d) shows the state in which the insulating layer is not formed. Figure 1(e) shows the etch-hacked state, Figure 1(e) shows the state with an insulating layer formed on the substrate surface, Figure 1(f) shows the state with the second layer gate electrode material deposited, and Figure 1(g) shows the second layer. Figure 1 (h) shows the state in which the gate electrode material has been etched, the first layer gate electrode and the second layer gate electrode have been formed, and Figure 1 (g) shows the state in which the insulating film has been formed on the surface of the substrate. Indicates the condition. FIG. 2 is an explanatory cross-sectional view of a semiconductor device for explaining a conventional manufacturing method of a semiconductor device, and FIG. 2(a) shows a part of the first layer gate electrode and the second layer gate electrode overlap In this case, FIG. 2(b) does not show the case where the first layer gate electrode and the second layer gate electrode are not overlapped. 1...Si substrate, 5...1st layer gate I/electrode,
6...SjO□ film, 8...2nd layer gate electrode material sum 1.8a...2nd layer gate electrode. Patent applicant Sharp Corporation

Claims (1)

[Claims] (1) After forming an insulating layer on the side surface of the first layer gate electrode formed on the surface of the semiconductor substrate, a material for the second layer gate electrode is applied to the surface of the semiconductor substrate, the surface of the insulating layer, and the top surface of the first layer gate electrode. a semiconductor device characterized by forming a second layer gate electrode between the first layer gate electrodes by etching the material to substantially the upper surface of the first layer gate electrode, and then removing the insulating layer. manufacturing method.