JPH02297619A - Disk controller with parallel transfer - Google Patents

Abstract

PURPOSE:To prevent a data error occurring due to a fault or malfunction, etc., by comparing a pass number with pass information, and transferring data when coincidence is obtained. CONSTITUTION:When the pass information 240 is analyzed with a pass decoder 61 at a subcontroller 51 and its own system is selected, a data transfer instruction 281 is outputted to a data transfer circuit 71. A synchronous circuit 81, when confirming the fact that all the subcontrollers 51-54 are set at states ready to receive the data, outputs a synchronism completion instruction 331, and also, a pass counter 111 counts the number of times of the output of a response signal 260. A pass number comparator 121 compares the output 351 of the pass counter 111 with the pass information 240, and outputs pass number noncoincidence 361 when noncoincidence occurs. In such a way, the pass information to designate the subcontrollers 51-54 and subcontrollers 55-58 alternately can be checked in data transfer between a host interface part 40 and the subcontrollers 51-58. Thereby, the data error due to the fault or the malfunction, etc., can be prevented occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a disk control device that performs parallel data transfer between a host processor and a plurality of disk devices via a plurality of data buffers.

[Conventional technology]

Conventionally, this type of disk control device has a host interface section that transfers L-byte data to and from a host processor when writing or reading data to or from N disk devices, and a disk device that has a data buffer. The host interface unit has N sub-controllers that transfer data of 1 byte width between the N sub-controllers, and the host interface unit transfers M (M=N/L) sub-controllers per 1-byte width to each L unit. Path information for sequential designation is output, and the designated subcontroller transfers data to and from the host interface unit.

[Problem to be solved by the invention]

In the above-mentioned conventional disk control device, each L subcontroller sequentially specified by the path information output from the host interface unit transfers data to and from the host interface unit. There is a drawback that data errors occur when path information is not specified sequentially due to malfunction or when data is transferred erroneously in a sub-controller.

[Means to solve the problem]

A disk control device for parallel transfer according to the present invention includes a host processor, N disk devices for recording a plurality of files in a fixed length, and a data buffer for storing data written to or read from the disk devices. N that controls writing and reading of data to the disk device
and a host interface unit to which M (M=N/L) subcontrollers are connected per 1 byte width for performing L-byte (1111) data transfer between the host processor and the host processor; a path decoder that analyzes path information output in order to sequentially designate each L subcontroller to which data is to be transferred from the host interface section in the subcontroller; and a path decoder that analyzes path information that is output to the subcontroller, and a path decoder that transfers data between the host interface section and the subcontroller. a path counter that counts the path number for each pass; a path number comparison circuit that compares the path number of the path counter with the path information from the host interface section; and a data transfer circuit that transfers 1-byte wide data between the host interface sections if no mismatch occurs in the comparison circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment is particularly an example of a disk control device that exchanges parallel data of 4 bytes (one word) with a host processor. The disk control device 20 has a host interface unit 4 that controls 4-byte data transfer with the host processor 10, and a data buffer that absorbs discrepancies in access times of the disk devices 31 to 38. It is composed of subcontrollers 51 to 58 that control writing and reading of data to and from 31 to 38, respectively.

Writing data to the disk devices 31 to 38 will be explained. When the host interface unit 40 receives write data from the host processor 10 via the data paths 201 to 204, the host interface unit 40 transmits path information indicating which of the subcontrollers 51 to 54 or 55 to 58 receives the data to the data path 240, and sends the write data to the host interface unit 40. data path 211
After outputting to 214, a transfer request signal 250 is output.

The host interface unit 40, for example, controls subcontrollers 51 to 54 when transferring the first word, subcontrollers 55 to 58 when transferring the second word, and subcontrollers 51 to 54 when transferring the third word. In order to specify alternately, path information is sequentially switched every time word data is transferred.

Next, referring to FIG. 2, the sub-controllers 51 to 58
will be explained in detail. Since each sub-controller has the same configuration, the sub-controller 51 will be representatively explained here. The path decoder 61 analyzes the path information 240 and, if its own system is selected, issues a data transfer instruction 281.
is output to the data transfer circuit 71. When the synchronization circuit 81 confirms via the line 271 that all of the subcontrollers 51 to 54 are ready to receive data, it outputs a synchronization completion instruction 331. Further, the pass counter 111 is
The number of times the response signal 260 is output is counted.

The path number comparison circuit 121 compares the output 351 of the path counter 111 and the path information 240, and outputs a path number mismatch 361 if a mismatch occurs. If the data transfer circuit 71 does not hold unwritten data in the data buffer 91, it outputs a transfer permission 321 to the synchronization circuit 81. When the synchronization completion instruction 331 is output from the synchronization circuit 81, the data transfer instruction 281 is output from the path decoder 61, and the path number mismatch 361 is not output from the path number comparison circuit 121, transfer from the host interface unit 40 is performed. Upon receiving the request signal 250, the data transfer circuit 71
receives 1 byte of data via the data path 211 and returns a response signal 260.

At this time, the subcontrollers 52 to 54 receive data via the data paths 212 to 214, respectively, but the response signal 2
60 will not be returned. Here, the subcontrollers that can output the response signal 260 are limited to the subcontrollers 51 and 55. However, if the path number comparison circuit 121 outputs the path number mismatch 361, the data transfer circuit 71 receives the transfer request signal 25 from the host interface unit 40.
Writing of erroneous data is prevented by not responding to 0 and canceling data transfer.

The host interface unit 40 has a sub-controller 51
When the response signal 260 is returned from the
After outputting the next word data to 11 to 214, a transfer request signal 250 is output. Further, the response signal 260
is the pass counter 1 of all subcontrollers 51 to 58
11 and updates the output 351 of the path counter 111. As a result, the output 351 becomes the sub-controller 55
The path number will be ~58. Therefore, the subcontrollers 55 to 58 next receive the data, and the subcontroller 55 returns a response signal 260. In this way, the subcontrollers 51 to 54 and the subcontrollers 55 to 5
8 alternately receive one word of data.

If the data transfer circuit 71 receives and holds data from the host interface section 40, it outputs write data to the data path 311 when the access permission 301 from the data buffer 91 is output, outputs a write instruction 291, and transfers the data. Store it in the buffer 91. The disk control unit 101 reads data stored in the data buffer 91 via the path 341 and writes it to the disk device 31 via the signal line 221. Sub controllers 52 to 58
Similarly to the sub-controller 51, each disk device 32
~Write data to 38.

Next, reading data from the disk devices 31 to 38 will be explained. The disk control unit 101 reads data from the disk device 31 via the signal line 221 and transfers the data to the path 34.
1 and stored in the data buffer 91. The data buffer 91 outputs access permission 301 if data is stored. When the access permission 301 is output from the data buffer 91, the data transfer circuit 71 reads and holds the data via the data path 311 and transfers the permission 301.
21 is output to the synchronization circuit 81. The data transfer circuit 71 receives data transfer instructions 281 . Synchronization completion instruction 331 from synchronization circuit 81. If the transfer request signal 250 is output from the host interface unit 4o and the path number mismatch 361 is not output from the path number comparison circuit 121, data is output to the data path 211 and a response signal 260 is returned. If the path number mismatch 361 is output, the data transfer circuit 71 does not respond to the transfer request signal 250 from the host interface section 40 and stops data transfer. The host interface section 40 is
When the response signal 260 is returned from the sub-controller 51, the data is received via the data paths 211-214 and transferred to the host processor 1o via the data paths 201-204. The subcontrollers 51 to 54 and the subcontrollers 55 to 58 alternately output one word of data, and the host interface section 4 sequentially receives the data.

〔Effect of the invention〕

As explained above, the present invention detects a failure by checking path information that alternately specifies the subcontrollers 51 to 54 and the subcontrollers 55 to 58 during data transfer between the host interface section and the subcontroller. This has the effect of preventing data errors due to malfunctions, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing the sub-controller 51 of FIG. 1. lO...Host processor, 20...
Disk control device, 31, 32. ~38...Disk device, 40...Host interface section, 51, 52. ~58... Sub controller,
61...Pass decoder, 71...Data transfer circuit, 81...Synchronization circuit, 91...
...Data buffer, 101...Disk control unit, 111...Pass counter, 121...
...Path number comparison circuit. Agent Patent Attorney Oto Uchihara 1X

Claims (1)

[Scope of Claims] A host processor, N disk devices that record a plurality of files in a fixed length, and a data buffer that stores data written to or read from the disk devices, and includes a data buffer for storing data written to or read from the disk devices. Data transfer of L byte width is performed between N subcontrollers that control reading and the host processor, and M (M=N/L) of the subcontrollers are connected per 1 byte width. In a disk control device having a host interface section that outputs path information for specifying L units for data transfer, each of the sub-controllers includes a host interface section for data transfer between all the sub-controllers and the host interface. The method is characterized in that it includes a transfer monitoring means for monitoring, a path information recognition means for recognizing the path information, and a data transfer circuit for selectively executing data transfer by the transfer monitoring means and the path information recognition means. Disk controller for parallel transfer.