JPH0229856B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to a diagnostic warning display device when a failure occurs in an automobile gasoline engine or the like equipped with a microcomputer-mounted engine control device. As interest in environmental conservation by preventing air pollution and the depletion of energy resources increases, control devices are designed to comprehensively control the operating conditions of automobile gasoline engines to improve exhaust gas conditions and improve fuel efficiency. As a result, microcomputers are being used to collect signals from sensors that provide various data that represent the operating status of the engine, such as a cooling water temperature sensor and an _O2 sensor that provides the oxygen concentration in exhaust gas. The electronic engine control device (EEC) controls various factors such as fuel intake, fuel supply amount, ignition timing, exhaust gas recirculation amount, and idle speed to ensure that the engine is always in the optimal operating state. It has come to be used. An example of a system in which such EEC is applied to a fuel injection type internal combustion engine is shown in FIGS. 1 to 6. Fig. 1 is a partial cross-sectional view schematically showing the entire engine control system.
6 and is supplied to cylinder 08. The gas burned in the cylinder 08 passes through the exhaust pipe 10 from the cylinder 08 and is discharged into the atmosphere. The throttle chamber 04 is provided with an injector 12 for injecting fuel, and the fuel injected from the injector 12 is atomized within the air passage of the throttle chamber 04 and mixed with intake air. A mixture is formed, and this mixture is supplied to the combustion chamber of the cylinder 08 through the intake pipe 06 when the intake valve 20 is opened. A throttle valve 14 is located near the outlet of the injector 12.
16 are provided. The throttle valve 14 is configured to mechanically interlock with the accelerator pedal and is driven by the driver. On the other hand, the throttle valve 16 is arranged so as to be driven by the diaphragm 18, and is fully closed when the air flow rate is small.As the air flow rate increases, the negative pressure on the diaphragm 18 increases, so that the throttle valve 16 It begins to open and suppresses the increase in inhalation resistance. An air passage 22 is provided upstream of the throttle valves 14 and 16 of the throttle chamber 04, and this air passage 22 includes a thermal air flow meter consisting of an electric heating element,
That is, a flow rate sensor 24 is provided, and an electric signal AF that changes depending on the air flow rate determined from the relationship between the air flow rate and the amount of heat transferred from the heating element is taken out. Since the flow rate sensor 24 made of this heating element (hot wire) is installed in the bypass air passage 22, it is protected from high-temperature gas generated when the cylinder 08 backfires, and it is also protected from being contaminated by dust in the intake air. It is also protected from. The outlet of this bypass air passage 22 is opened near the narrowest part of the bench lily, and the inlet thereof is opened on the upstream side of the bench lily. Fuel supplied to the injector 12 is supplied from a fuel tank 30 to a fuel pressure regulator 38 via a fuel pump 32, a fuel damper 34, and a filter 36. On the other hand, pressurized fuel is supplied from the fuel pressure regulator 38 to the injector 12 via a pipe 40.
Fuel is returned from the fuel pressure regulator 38 to the fuel tank 30 via the return pipe 42 so that the difference between the pressure in the intake pipe 06 where fuel is injected from the fuel pressure regulator 38 and the fuel pressure to the injector 12 is always constant. It's summery. The air-fuel mixture taken in from the intake valve 20 is transferred to the piston 5.
0 and is combusted by a spark from the ignition plug 52, and this combustion is converted into kinetic energy. The cylinder 08 is cooled by cooling water 54, the temperature of this cooling water is measured by a water temperature sensor 56, and this measured value TW is used as the engine temperature. A high voltage is supplied to the spark plug 52 from an ignition coil 58 in accordance with the ignition timing. Further, a crankshaft (not shown) is provided with a crank sensor that outputs a reference angle signal and a position signal at each reference crank angle and at each fixed angle (for example, 0.5 degrees) according to the rotation of the engine. The output of this crank angle sensor, water temperature sensor 56
output signal TW and electrical signal from heating element 24
The AF is inputted to a control circuit 60 consisting of a microcomputer or the like and subjected to arithmetic processing, and the output of this control circuit 60 drives the injector 12 and the ignition coil 58. Furthermore, the throttle chamber 04 has a throttle valve 1.
A bypass 26 is provided that straddles the intake pipe 6 and communicates with the intake pipe 06, and this bypass 26 is provided with a bypass valve 61 that is controlled to open and close. This bypass valve 61 faces the bypass 26 provided by bypassing the throttle valve 16, and is controlled to open and close by a pulse current, and the cross-sectional area of the bypass 26 is changed depending on the lift amount. The drive section is driven and controlled by the output of the control circuit 60. That is, the control circuit 60 generates an opening/closing periodic signal for controlling the driving section, and the driving section adjusts the lift amount of the bypass valve 61 based on this opening/closing periodic signal. Therefore, the injector 12 shown in FIG. 1 is controlled to control the air-fuel ratio (A/F) and fuel increase control, and the bypass valve 61 and the injector 12 control the engine speed at idle (ISC).
Do this. FIG. 2 shows an ignition system in which a pulsed current is supplied via an amplifier 62 to a power transistor 64, which turns on the transistor 64. As a result, the ignition coil 58 from the battery 66
Primary coil current flows to. When the input pulse current falls, the transistor 64 is cut off, and
A high voltage is generated in the secondary coil of the ignition coil 58. This high voltage is distributed via the power distributor 70 to each of the spark plugs 52 in each cylinder of the engine in synchronization with the engine rotation. FIG. 3 is for explaining an exhaust gas recirculation (EGR) system, in which constant negative pressure from a negative pressure source 80 is applied to a control valve 86 via a pressure control valve 84.
The pressure control valve 84 controls the ratio of the negative pressure of the constant negative pressure source to the atmosphere 88 according to the ON duty ratio of the repeated pulses applied to the transistor 90, and controls the state of application of the negative pressure to the control valve 86.
Therefore, the negative pressure applied to the control valve 86 is determined by the ON duty ratio of the transistor 90. The controlled negative pressure of the pressure control valve 84 causes the exhaust pipe 10 to flow into the intake pipe 0.
The amount of EGR to 6 is controlled. Figure 4 is an overall configuration diagram of a control system using a microcomputer, which includes a central processing unit 102 (hereinafter referred to as CPU), a read-only memory 104 (hereinafter referred to as ROM), and a random access memory 106 (hereinafter referred to as ROM). (referred to as RAM) and an input/output circuit 108.
The CPU 102 calculates input data from the input/output circuit 108 using various programs stored in the ROM 104, and returns the calculation results to the input/output circuit 108 again. RAM 106 is used for intermediate storage necessary for these operations. CPU102,
Various types of data are exchanged between the ROM 104, RAM 106, and input circuit 108 via a bus line 110 consisting of a data bus, a control bus, and an address bus. The input/output circuit 108 includes a first analog-to-digital converter 122 (hereinafter referred to as ACD1).
and a second analog-to-digital converter 12
4 (hereinafter referred to as ADC2) and angle signal processing circuit 1
26 and a discrete input/output circuit 128 (hereinafter referred to as DIO) for inputting and outputting 1-bit information. ADC1 has a battery voltage detection sensor 132
(hereinafter referred to as VBS) and cooling water temperature sensor 56 (hereinafter referred to as VBS)
(hereinafter referred to as TWS) and atmospheric temperature sensor 136 (hereinafter referred to as TAS)
) and vehicle speed sensor 138 (hereinafter referred to as VRS)
The outputs of the throttle angle sensor 140 (hereinafter referred to as θTHS) and the O ₂ sensor 142 (hereinafter referred to as O ₂ S) are added to the multiplexer 162 (hereinafter referred to as MPX), and the MPX 162 selects one of them.
Select one to convert analog/digital/conversion circuit 1
64 (hereinafter referred to as ADC). ADC16
The digital value that is the output of 4 is stored in register 166.
(hereinafter referred to as REG). The angle sensor 146 (hereinafter referred to as ANGS) outputs a signal indicating a reference crank angle, for example, 180 degrees crank angle (hereinafter referred to as REF), and a signal indicating a minute angle, for example, 1 degree crank angle (hereinafter referred to as POS). The signal is applied to the angle signal processing circuit 126, where the waveform is shaped. DIO 128 includes an idle switch 148 that operates when the throttle valve 14 returns to the fully closed position.
(hereinafter referred to as IDLE-SE), top gear switch 150 (hereinafter referred to as TOP-SW), and starter switch 152 (hereinafter referred to as START-SW)
is entered. Flow rate sensor 24 (hereinafter referred to as AFS) is ADC2
is input to analog/digital/conversion circuit 1
72 (hereinafter referred to as ADC), it is digitally converted and set in a register 174 (hereinafter referred to as REG). Next, the pulse output circuit and control target based on the calculation results of the CPU will be explained. The injector control circuit (denoted as INJC) is a circuit that converts the digital value of the calculation result into a pulse output. Therefore, a pulse with a pulse width corresponding to the fuel injection amount
INJ is made with INJC1134, AND gate 11
36 to the injector 12. The ignition pulse generation circuit 1138 (hereinafter referred to as IGNC) has a register (hereinafter referred to as ADV) for setting the ignition timing and a register (hereinafter referred to as DWL) for setting the primary current energization start time of the ignition coil.
These data are set by the CPU. Generates a pulse IGN based on the set data,
AND gate 11 to amplifier 62 detailed in FIG.
Apply this pulse IGN via 40. The opening rate of the bypass valve 61 is determined by the control circuit (hereinafter referred to as
ISCC) 1142 to AND gate 1144
is controlled by a pulse ISC applied via. ISCC 1142 has a register ISCD for setting the pulse width and a register ISCP for setting the repetition pulse period. The EGR amount control pulse generation circuit 178 (hereinafter referred to as EGRC) that controls the transistor 90 that controls the EGR control valve 86 shown in FIG. 3 has a register that sets a value representing the pulse duty.
It has EGRD and a register EGRP for setting a value representing the pulse repetition period. This EGRC
The output pulse EGR of is applied to transistor 90 via AND gate 1156. Further, the 1-bit input/output signal is controlled by the circuit DIO128. IDLE-SW as input signal
signal, TOP-SW signal, and START-SW signal. Further, the output signal includes a pulse output signal for driving the fuel pump. This DIO has a register DDR192 for determining whether the terminal is used as an input terminal or an output terminal,
Register DOUT for latching output data
194 are provided. The mode register 1160 is a register (hereinafter referred to as MOD) that holds instructions for specifying various states inside the input/output circuit 108. For example, by setting an instruction to the mode register 1160, the AND gates 1136, 1140, 1144,
All 1156 are activated or deactivated. Like this MOD register 11
By setting the command to 60, INJC and
You can control the stop and start of IGNC and ISCC output. As mentioned above, DIO 128 is a 1-bit signal input/output circuit, and is a register (hereinafter referred to as DDR) 1 that holds data for determining input or output.
92 and a register 194 (hereinafter referred to as DOUT) for holding data to be output.
This DIO 128 outputs a signal DJO0 for controlling the fuel pump 32. FIG. 5 is a program system diagram of the control circuit of FIG. 4. When the power is turned on by a key switch (not shown), the CPU 102 enters a start mode and executes an initialization program (INITIALIZ) 204. Next, execute the monitoring program (MONIT) 206 and execute the BACK GROUND JOB 2.
Execute 08. This background job includes, for example, the EGR amount calculation task (hereinafter referred to as EGR
CAL TASK) and a calculation task (hereinafter referred to as FISC) for the bypass valve 61 and injector 12 during warm-up operation. During the execution of this TASK, if an interrupt factor (hereinafter referred to as IRQ) occurs,
From the IRQ disclosure step 222, an IRQ factor analysis program 224 (hereinafter referred to as IRQ ANAL) is executed. This IRQ ANAL program is further
ADC1 end interrupt processing (hereinafter referred to as ADC1 END)
IRQ) program 226, ADC2 end interrupt processing (hereinafter referred to as ADC2 END IRQ) program 228, and certain period elapsed interrupt processing (hereinafter referred to as ADC2 END IRQ)
It consists of an engine stop interrupt processing (hereinafter referred to as INTV IRQ) program and an engine stop interrupt processing (hereinafter referred to as ENST IRQ) program, and issues a start request (hereinafter referred to as QUEUE) to each task that needs to be started, which will be described later. Each program in this IRQ ANAL program 224 ADC1 END IRQ226 and ADC2
Each task to which a QUEUE is issued by each program of END IRQ 228 and INTV IRQ 230 is level zero task group 252 or level 1 task group 2.
54, level 2 task group 256, level 3 task group 258, or tasks constituting each task group. The task in which QUEUE is generated by the ENST IRQ program 232 is the engine stop processing task 262 (hereinafter ENST
(written as TASK). This ENST TASK26
2 is executed, the control system starts again.
mode and returns to the starting point 202. The task scheduler 242 sets the execution order of the tasks so that they are executed starting with the task in which the QUEUE is occurring or the task with the highest level among the tasks whose execution has been interrupted (here, level zero is the highest). decide. When the execution of the task group is completed, the completion report program 260 (hereinafter referred to as EXIT) reports the completion. Based on this completion report, the task group with the highest level among the task groups waiting for execution is executed next. When there are no more suspended tasks or tasks with QUEUE, the task scheduler 242
The process then moves on to executing the background job 208 again. Furthermore, if an IRQ occurs while any of the level 0 task group to level 3 task group is being executed, the process returns to the starting point 222 of the IRQ processing program. Table 1 shows the activation of each task and its functions.

[Table] In this Table 1, IRQ ANAL
There are programs, TASK SCHDULER, and EXIT. These programs (hereinafter referred to as OS) are held at addresses A000 to A300 of the ROM 104 as shown in FIG. Furthermore, as a level zero program
AD1IN, AD1ST, AD2IN, AD2ST, RPMIN
There are various programs, usually INTV IRQ 10 [m
SEC]. As a level 1 program
There are INJC, IGNCAL, and DWLCAL programs.
It is activated every 20 [mSEC] of INTV IRQ. A level 2 program is the LAMBDA program, which is activated every 40 [mSEC] of INTV IRQ. There is a HOSEI program as a level 3 program, which is activated every 100 [mSEC] of INTV IRQ. There are also EGRCAL and FISC programs as background jobs. The above level zero program starts from address A700 of ROM104 in Figure 6 as PROG1.
Remembered by AAFF. Level 1 program is PROG2 at address AB00 of ROM104.
It has been stored in ABFF since then. The level 2 program is PROG3 at address AE00 of ROM104.
It has been stored in AEFF since then. Level 3 program is PROG4 at ROM10.4 address
Stored in AF00 to AFFF. Also, background job programs are held in B000 to B1FF. The above program
Lift the start address of each program from PROG1 to PROG4 (hereinafter referred to as SETMR)
is held from B200 to B2FF, and from PROG1
The value representing each program startup cycle up to PROG4 (hereinafter referred to as TTM) is from address B300 to B3FF
is stored in Other data is stored at addresses B400 to B4FF of the ROM in FIG. 6 as necessary. Following that, data ADV.MAP and AF.MAP for calculation,
Each EGR.MAP is memorized. Note that a detailed explanation of other operations will be omitted. Thus, according to the EEC mentioned above,
Almost all controls related to the engine, such as A/F control, can be appropriately performed, and the engine can fully meet the strict exhaust gas regulations, as well as provide an engine with excellent fuel efficiency. By the way, in general, when a car or other vehicle becomes malfunctioning due to a malfunction, it is extremely rare for the user to find the malfunctioning part and perform repairs or inspections on his/her own; in most cases, the user will have to request a repair shop to do the work. It is customary to find the malfunctioning part, repair it, and inspect it. However, as mentioned above, automobile engines equipped with EEC use a large number of various sensors and actuators, and their failure modes are diverse and diverse, and failures are rarely obvious from the outside. When a failure occurs, it is extremely difficult to identify the location where the failure occurred. In addition, many malfunctions can only be discovered when the engine operating conditions meet specific conditions, so even if a user complains of a malfunction, the same problem cannot be detected while the engine is actually operating. Unless the conditions are reproduced, the failure cannot be discovered. Therefore, in the conventional EEC, when a failure occurs, it is difficult to accurately diagnose it, and locating the failure location requires a high degree of skill and a lot of time. Therefore, the operation of the various sensors and actuators of the EEC mentioned above is constantly monitored and an alarm is issued when a failure is detected, and a memory means is provided so that the stored data does not disappear even when the EEC operation is stopped. If a malfunction occurs in any of the sensors or actuators, you can immediately know about it, and even after the engine has stopped,
A fault location self-diagnosis alarm device for EEC has been proposed which allows the fault location to be immediately known as it is, and an example thereof will be described below with reference to FIGS. 7 to 27 of the drawings. In this conventional example, most of the configuration as an EEC is the same as the conventional example shown in FIGS. 1 to 6, so only the different points will be explained in detail in the following explanation. FIG. 7 shows a conventional example of a control system in which a failure location self-diagnosis alarm display device is applied to EEC.The difference from the conventional example shown in FIG. A RAM 1104 is provided that is backed up and configured to operate as a memory that does not generate brightness.
A warning lamp 1106 and a display switch (hereinafter referred to as DISP-SW) 1108 are provided. And CPU102, ROM104, RAM1
By a microcomputer program such as 06,
Checks inputs from various sensors 132 to 148 including air flow rate sensor 24, water temperature sensor 56, etc., and inputs from various switches such as idle switch 148 to start switch 152, and checks inputs from various switches such as idle switch 148 to start switch 152, respectively, under predetermined timing and conditions. 12. The outputs of various actuators such as the fuel pump 32 and bipal valve 61, as well as the amplifier 62 and transistor 90 included therein, are checked, and if any abnormality is found in these inputs or outputs, the As shown in the figure, coded data corresponding to those abnormalities (hereinafter simply referred to as malfunction codes) is
It is written in the RAM 1104 and displayed on the alarm lamp 1106 as necessary. Therefore, if the above abnormality occurs while driving the car or when starting the engine, the warning lamp 1106 immediately displays the abnormality, allowing the driver of the car to continue driving without knowing that a malfunction has occurred. It is possible to prevent this from happening. The lighting mode of the warning lamp 1106 at this time is, for example, as shown in Fig. 9 a and b.
indicate cases in which an abnormality has already been detected before starting. As is clear from FIG. 9a, the lamp lights up when the key switch is turned on, and then goes out when the engine starts. This makes it possible to check that there is no abnormality in the alarm lamp 1106 itself. The lamp remains off as long as no abnormality occurs. Next, when a malfunction occurs, the light goes into a flashing mode in which the light is turned on for 0.6 seconds at 0.6 second intervals.
The light will continue to blink until the problem is resolved, and if the problem is resolved for some reason, it will remain off. At this time, if the engine stalls, the light will remain on as it does from the time the key switch is turned on until the engine starts. Furthermore, as is clear from FIG.
6 continues flashing. Furthermore, even if the engine stalls at this time, the flashing mode will not change this time. Therefore, simply by seeing the flashing warning lamp 1106, one can know that some kind of abnormality has occurred and that further continuation of the operation is no longer desirable. Next, when the display switch 1108 is operated, an input is given to the CPU 102 via the DIO 128, the operation mode of this control circuit becomes a fault code display mode, and the program is switched. When you enter this display mode program, RAM
The code is read from 1104, and the alarm lamp 110 is turned on according to the read code.
Since the lighting mode of 6 is controlled, a person who inspects or repairs a car, such as a service operator, can simply read the code from the flashing mode of this warning lamp 1106 to detect abnormalities in various sensors, actuators, etc. Since it is possible to identify the object and also know the nature of the abnormality at the same time, inspections and repairs can be carried out easily and accurately in a short period of time. The lighting mode of the alarm lamp 1106 at this time is, for example, as shown in FIGS. 10a to 10b. First, a shows the alarm lamp 110 when the display switch 1108 is operated to switch to the display mode and no malfunction has occurred up to that point.
6 lighting mode, the code at this time is [01] as shown in Figure 8, so after 2.4 seconds of preparation time has elapsed after the display starts, the code at this time is 0.3.
Repeat lighting for 3 seconds and turning off for 3 seconds 3 times. In this state, display switch 1108 is turned on.
keep it for as long as it takes. Next, when b is in display mode, by then
If an error occurs in which the ISC terminal shorts, and as a result, code [22] is stored in RAM 1104, after 2.4 seconds of preparation time,
1.2 seconds of lighting time with 0.6 seconds of turning off time 2
3 times, and then a blinking state in which the lighting time of 0.3 seconds occurs twice in succession is repeated 3 times. As is clear from these Figures 10a and b,
The number of flashes for 1.2 seconds following the 2.4 seconds of preparation time represents the 10s digit of the code, and the number of flashes for 0.3 seconds represents the 1s digit of the code.
It can be seen that the 3 seconds of lights-out time represents a code break. Therefore, in Figure 10a, the code is [01], so it lights up for 0.3 seconds once, and in Figure 10b, the code is [22], so it lights up twice for 1.2 seconds.
The lights appeared twice for 0.3 seconds each. In this way, display switch 110
Warning lamp 1106 that occurs when 8 is turned on
The code previously stored in the RAM 1104 can be visually read very easily depending on the lighting state of the code, and the location of the abnormality can be easily identified and the contents of the abnormality can be easily known. By the way, since such an EEC is equipped with a large number of sensors and actuators, there is a considerable possibility that malfunctions may occur at the same time or at multiple locations within a relatively short period of time. Therefore, in this conventional example, the RAM 1104
has multiple addresses, for example 3.
It is now possible to memorize specific fault codes. Therefore, in such a case, when the display switch 1108 is turned on and switched to the fault code display mode, the plurality of fault codes that have been stored up to that point are sequentially displayed three times as shown in Figure 10c. It is now displayed one by one. In other words, if the currently memorized fault codes were [22] and [15], code [22] would be displayed three times, followed by code [15] three times, and this would cause switch 1108 to be displayed. This will repeat until you turn it off. Therefore, even if a plurality of abnormalities have occurred up to that point, up to three abnormalities are stored and displayed in sequence, making it extremely easy to discover the malfunction. In addition, even if there is no problem,
The purpose of storing the code [01] in the RAM 1104 and reading it out and displaying it during the display mode is to confirm that no abnormality has occurred in the system including the RAM 1104. It can be done reliably. In this way, according to the above conventional example, when an abnormality occurs during engine operation, the abnormality occurs in the battery 110.
2 is encoded and stored in the RAM 1104, which operates as a non-luminous memory, so the location and contents of the problem can always be known with certainty even after the engine has stopped. Next, operations in the alarm mode and code display mode when a malfunction of the various sensors and actuators shown in FIG. 8 are detected will be described. Figure 11 is a flowchart showing the operation for identifying alarm mode and code display mode, which is incorporated into the level 2 task in the program system diagram shown in Figure 5, and is activated every 40 [mSEC]. ing. When entering this task, it is determined in step (hereinafter referred to as S) 1 whether the display switch 1108 is ON or not, and if NO, the process advances to S2.
Check the RAM 1104 to see if there is a defect flag, and if NO, proceed directly to EXIT.
When the result in S2 is YES, an alarm operation in S3 is performed. Also, if the result is YES in S1, move on to S4,
Performs code display operation. Figure 12 is a flowchart showing the details of alarm operation S3 in Figure 11.
In S31, it is determined based on the flag whether or not the time setting is completed. If the result in S31 is NO, the process advances to S32 to set the flag. This is for checking the completion of the time setting required in S31. Then in S33
Set the time to 0.6 seconds. This time setting is performed by setting an initial value to a counter. Finally, in S34, the state of the alarm lamp 1106 is reversed, and then the process goes to EXIT. Also, when the result in S31 becomes YES,
Proceed to S35 and determine whether 0.6 seconds have elapsed by looking at the counter set in S33. If the result is NO, subtract 1 from the time counter in S37 and proceed to EXIT. Furthermore, if the result in S35 is YES, the flag is reset in S38 and then the process proceeds to EXIT. Therefore, the next time this flow is entered, the process will proceed from S31 to S32. The result of executing the above flow is as follows. First, the first thing that comes into this flow is
As is clear from FIG. 11, this is when an abnormality occurs and the defect flag is raised in a state where there was no defect flag until then. Therefore, when entering S34 from S31 through S32 and S33, the warning lamp 1106 is still on.
is not lit. Therefore, in S34, lamp 110
6 lighting is performed. And after that, 40 [m
SEC] When entering this flow, the time counter is sequentially decremented in S37, and when 0.6 seconds have passed, it becomes 0, so the flag is reset in S38. So next time I go from S31 to S34 again, but this time the lamp is lit, so
This time, the lamp 1106 is turned off. Accordingly, the alarm operations shown in FIGS. 9a and 9b are performed by the flow shown in FIG. 12. It should be noted that the time counters referred to as S33, S35, S37, etc. are configured by software by the program of the CPU 102 using the memory area of the RAM 106 (Fig. 7), and it is clear from the above explanation. The initial value that should be set in S33 is 0.6 seconds, as shown in
The value divided by 40 [mSEC], that is, 15. Next, FIGS. 13 to 15 are flowcharts showing details of the code display operation S4 in FIG.
When entering this flow, first check the flag in S301 to determine whether the 2.4 second timer is set, and if NO, proceed to S302 and turn on the alarm lamp.
106 is turned off, a 2.4 second timer is set, and a flag is set. Next, I turn to S303 and check the flag to see if 2.4 seconds have elapsed. If the result in S301 is YES, skip S302 and proceed to S303. If the result here is NO
Head to S304 and subtract 1 from the 2.4 second timer there.
Next, check whether the 2.4 second timer has reached 0 in S305, and if NO, exit from EXIT, but if YES, exit from EXIT.
Set the flag in S306. By executing these steps S301 to S306, the light-off time of 2.4 seconds from the start of the display shown in FIGS. 10a and 10b is set. Note that the timer referred to here is the same as the time counter described above, and is configured in software. After this, the code is displayed in the manner shown in Figures 10 a to 10 b, but this point can be easily understood by looking at the flowcharts in Figures 13 to 15, so a detailed explanation will be provided. is omitted. Next, abnormality detection operations of the various sensors and actuators described above will be explained. In the above conventional example, when detecting an abnormality in a sensor, etc., the determination of whether or not there is an abnormality is repeated multiple times, for example, five times, and a temporary abnormality that happens to occur at the time of abnormality detection or noise that strays into the signal system, etc., may mistakenly cause an abnormal state. In order to eliminate detection results that have become false and to reliably detect only true abnormalities, the operation shown in the flowchart of FIG. 16 is performed. That is, when an abnormality detection program for various sensors, etc. is entered under predetermined conditions or timing, the operation shown in FIG. 16 is performed, and first, in S601, it is determined whether or not there is an abnormality. Note that the determination operation in S601 corresponds to various types of sensors and actuators, and some examples will be described later. If the determination result in S601 is NG, that is, abnormal, the process advances to S602 and the NG counter is incremented. This NG counter is for counting the number of judgments. Then I entered S603 and this NG
Check whether the contents of the counter are 5 or not. By the way, if the result for S601 is now NG for the first time, the result for S603 is of course
Since the answer is NO, proceed directly to EXIT and end this operation. Next time this flow starts, if the result in S601 becomes NG again, the above operation will be repeated, and each time the NG counter will be increased in S602.
1. Therefore, if the operation of this flow is started and the result in S601 is NG each time,
In other words, during that time, the abnormal condition continues and it is 5
The result in S603 becomes YES only when the abnormality is detected several times. In this case, the process proceeds to S604 to set the contents of the NG counter to 0, and then sets the defect flag indicating that an abnormality has been detected in S605. Then, in S606, NG processing is performed such as storing a code corresponding to the content of the abnormality at a predetermined address in the RAM 1104 according to FIG. 8, and the flow exits. Also, if the result in S601 is OK, that is, there is no abnormality, proceed to S607 and check the contents of the NG counter, and if it has not reached 0, that is, the result is NO, proceed to S608 and check the contents of the NG counter. Set the contents to 0 and proceed to S608. On the other hand, S607
If the result is YES, proceed directly to S609,
Check whether the defective flag is set or not. If the result is YES, clear the defective flag through S610 and then exit to EXIT. If the result is NO, proceed to EXIT.
Immediately exit to EXIT from S609. As a result of the operation according to the flowchart in FIG. 16, each time the judgment result in S601 becomes OK, that is, there is no abnormality, the NG counter is reset to 0 and the defective flag is cleared in S607 to S610. Therefore, the judgment result in S601 is 5 times,
The failure flag is set through S605 only when the result is NG continuously, that is, there is an abnormality, and abnormalities due to temporary abnormalities or false detections due to noise can be eliminated. Note that if the content of the NG counter in S603 is set to another number, the number of times the check is performed can be set to an arbitrary number accordingly. In addition, in this conventional example, after an abnormality occurs five times in a row and the failure flag is set and NG processing is performed,
Even if the result in S601 is OK, the defect flag is set and NG processing is performed again only when NG occurs five times in a row.However, once the defect flag is set, NG processing is performed again. It can be considered that the reason why the judgment becomes OK after the test is carried out is more likely to be due to an error being determined as normal than if the abnormality disappears.
If the determination becomes NG after that, the defect flag may be reset and NG processing may be performed immediately. In other words, in this case, even if the result in S601 is not NG five times in a row, S602 is immediately executed just once.
Then, it passes through S605. To this end, for example, a step may be provided after S610 to set the contents of the NG counter to 4. Next, the abnormality check of various sensors and actuators shown in S601 of FIG. 16 will be explained. FIG. 17 shows an example of an ignition system abnormality check system, in which an amplifier 62 is provided with a test input terminal 621, a test signal PA ₀ is supplied to the base of an amplification transistor Q62 via a transistor Q65, and a test output A terminal 622 is provided to take out the detection signal AI6. FIG. 18 is a flowchart showing the abnormality check operation. This ignition system abnormality check system is incorporated as one task in the engine stall task 262 (FIG. 5), and is activated when the engine stalls. When we start this flow, first we start with the signal at S801.
Examine AI6 and determine whether it is greater than 0.5V. At this time, the engine is stalled, so IGN is 1
, while the signal PA ₀ still remains at 0. Therefore, since the ON signal should be supplied to the base of transistor Q62,
If the result in S801 is YES, transistor Q
This means that an abnormality has occurred in transistor Q62 and the collector-emitter is open, so a defect flag indicating that transistor Q62 is open is prepared through S802, and the judgment result in S601 (Figure 16) is NG. Then I headed towards S602. Therefore, at this time, the code "38" is stored in RAM according to Figure 8.
1104. Furthermore, if the result in S801 is NO, proceed to S803 and first set the test signal PA ₀ to 1. and S804
Proceed to check the detection signal AI6 and find that it is 1.3V±
Determine whether it is within the 0.5V range. Note that this voltage value of 1.2V±0.5V is the forward voltage between the base and emitter of the transistor 64, so it goes without saying that it is necessary to set the voltage value appropriately depending on the type of transistor used as the transistor 64. do not have. Now, if the result in S804 is YES, it means that no abnormality has been detected, so we return the test signal PA ₀ to 0 for S805, and the judgment in S601 is OK, so as shown in Figure 16. Head to S606. On the other hand, if the result in S804 is NO, the next S806
Then, it is checked whether the voltage value of the detection signal AI6 is greater than 1.7V. If the result is NO, the harness part up to transistor 64 or transistor Q
62 and 64, and when the result is YES, it indicates that the harness part up to transistor 64 is open, so the code "36" or "37" to be stored in the RAM 1104 according to FIG. Prepare to set bad flag
This is done in S807 or S808, and then the test signal PA ₀ is returned to 0 in S809, and the determination result becomes NG. Next, a conventional example of abnormality checking operation of the air flow sensor AFS will be explained with reference to the flowchart of FIG. This operation is processed as one task of the level 2 task 256 in Fig. 5. When entering this flow, data from the AFS 24 (Fig. 7) is first fetched from the RAM 106 in S901, and then the data is judged in S902. Do this. As shown in Figure 20, this AFS24 generates an output voltage within the range under normal conditions, so when it is determined in S902 that the data is within the range, the determination result is unchanged.
OK. However, when the result in S902 is determined to be a low output state, the process proceeds to S903, prepares to set a defective flag corresponding to the low output, and exits with a determination result of NG. Therefore, at this time, the code "14" is stored according to FIG. Also, when the result in S902 is determined to be a high output state, the process goes to S904 to check whether the engine rotation speed is 4000 rpm or more, and if the result is YES, exits with OK. On the other hand, the result is
If NO, the process advances to S905, prepares to set a failure flag corresponding to the large output, and then exits to NG. Therefore, at this time, as shown in Figure 8,
Code "15" is memorized. In addition, here S904
The reason for this is that even if the AF data reaches the high output range, it is not abnormal when the engine speed is high. Next, FIG. 21 shows an example of an abnormality check system for the actuator that controls the idle speed, that is, the bypass valve 61. In the figure, 210 and 211 are detection signals PA6
and the output terminal of PA7, 212 is the input terminal of test signal PB7, Q213 is the amplification transistor, Q2
14 is a driving transistor, and Q215 is a detection transistor. FIG. 22 is a flowchart showing the abnormality check operation, in which background job 208 (fifth
(Figure) is executed as one program, and when this flow starts, the detection signal is first detected in S20.
PA6 and PA7 are read, and then it is checked in S21 whether signal PA6 is 0 or 1. Then, when the result becomes 1, the signal is sent in the following S22.
Check whether PA7 is 0 or 1, and if the result is 1, it is assumed that there is no abnormality and exits successfully. In other words, signal PA6
is 1, which means that the signal ISC is 1, so it is normal for both transistors Q213 and Q214 to be on, and therefore transistor Q21 is turned on.
5 should be off, so at this time the signal
If PA7 is also 1, it means that there is no abnormality. Also, if the result in S22 becomes 0, this indicates that one or both of transistors Q213 and Q214 is open, so proceed to S23 and prepare to set the defective flag.
Exit to. Therefore, at this time, the code "20" will be stored according to FIG. On the other hand, if the result in S21 becomes 0, proceed to S24, check signal PA7, and if it becomes 0, proceed to S24.
Proceed to OK. That is, if the signal PA6 is 0, the signal ISC is 0, transistors Q213 and Q214 are off, and therefore the transistor Q215 is on. Therefore, if the signal PA7 is also 0, an abnormal state occurs. However, if the result in S24 becomes 1, the next S25
After setting the test signal PB7 of the terminal 212 to 1, the signal PA7 is read in S26, and it is checked whether this signal PA7 is 1 or 0 in the following S27. When the result becomes 1, preparations are made to set the output shot defect flag before proceeding to S28, and then exits to NG. Therefore, the code "22" will be stored at this time. Also, if the result in S27 is 0, turn to S29,
The harness open defect flag is set and the flag is NG, and the code "21" is stored. That is, signal PA6 changes from 0 to transistor Q2.
13 and Q214 should be off and transistor Q215 should be on, so signal PA7 must be 0. However, signal PA7 becomes 1, which means that the base of transistor Q215 becomes 0.
It means becoming. Therefore, signal at S25
When setting PB7 to 1, if signal PA7 does not become 0, a signal is sent to the base of transistor Q215.
Since this means that PB7 is not given, it can be seen that the output is shot. Also, if the signal PA7 becomes 0 at this time, it means that the signal PB7 is applied to the base of the transistor Q215,
Therefore, it means that no voltage has been applied from the power supply +B through the solenoid valve 61 until then, and it is determined that the harness is open. Next, FIG. 23 shows an example of an abnormality check system for the pressure control valve 84, which is an actuator for EGR control, in which 901 and 903 are output terminals for detection signals PA4 and PA5, 902 is an input terminal for test signal PB5,
Q91 and Q92 are detection transistors.
Note that 90 is a transistor for driving the pressure control valve 84. FIG. 24 is a flowchart showing the operation of this abnormality check system, which operates as one of the programs of the background job 208 in FIG. When entering this flow, first the detection signal PA is detected at S40.
4. Read PA5, and then check whether signal PA4 is 1 or 0 in S41. If the result in S41 is 0, proceed to S42 and check whether signal PA5 is 1 or 0. If the result is 1, exit to OK. Also, when the result is 0,
A defect flag indicating that the transistor 90 is open is prepared through S43, and the process exits to NG. In other words, the reason why the signal PA4 becomes 0 in S41 is because the transistor Q91 is on, that is, the signal EGR
indicates that the current value has become 1, and the transistor 90 should also be on at this time. Therefore, if transistor 90 is normal, transistor Q92 is turned off, so when PA5 is checked in S42, if the result is 1, there is no abnormality and it is OK, and if the result is 0, transistor 90 is open abnormally and it is NG. be. Therefore, at this time, the code "23" is entered from Figure 8.
is memorized. Also, if the result in S41 is 1, proceed to S44,
Check signal PA5 and if it is 0 then OK
However, if the result becomes 1, proceed to S45 and first try setting test signal PB5 to 1. Then S46
After reading the detection signal PA5 in S47, it is checked whether it is 0 or 1. If the result in S47 is 1, S48
The output ground failure flag is prepared through S49, and when the result becomes 0, the harness open failure flag is prepared in S49, and each exit is NG. In other words, the signal PA4 becoming 1 in S41 means that the input signal EGR is 0.
Therefore, if the transistor 90 is normal, it should be off, and at that time the transistor Q92 is on, so if the detection signal PA5 is 0 in S44, it is OK. Further, if the result is 1 in S44, it means that the voltage from the power supply +B is not applied to the base of the transistor Q92, so try applying the test signal PB5 in S45. If transistor Q92 still does not turn on, that is, S47
When the result becomes 1, the transistor 90
If the short or output end of transistor Q92 is turned on and the result at S47 becomes 0, it can be seen that the path from the power supply +B to the base of transistor Q92 is open, that is, the harness is open. Therefore, when passing through S48, the code "25" is
Then, when passing through S49, the code "24" is stored. Next, an example of an abnormality check system for the fuel pump 32 is shown in FIGS. 25 to 27. FIG. 25 shows a circuit of a relay driving transistor Q32 of the fuel pump 32, and a detection signal PA2 is taken out from its collector. By the way, there are two types of abnormality checks for the fuel pump 32: one in normal operating conditions and one when the engine stalls. First, Fig. 26 shows the one during normal operation, and is checked every 10 minutes by a timer interrupt. First, in S60, the control signal DIO0 is set to 1 to turn off the transistor Q32. This is because under normal operating conditions, the fuel pump 32 is in operation and therefore the control signal is
This is because DIO0 is set to 0. Then, after a predetermined waiting time, it is checked in S61 whether the detection signal PA2 has become 0 or not. If the result is determined to be YES, the signal DIO0 is set to 0 in S62.
Return to OK and exit. Further, if the result in S61 is NO, the process proceeds to S63, where a defect flag indicating that the transistor Q32 has become defective in shot is prepared, and the process exits to NG. In other words, if transistor Q32 is normal, it is turned on and off by control signal DIO0, and detection signal PA2
is 1 if transistor Q32 is on, and 0 if it is off.
This is because it is supposed to be. Therefore, at this time, code "33" is stored. Next, FIG. 27 shows the operation when the engine stalls, which is performed by one program of the engine stall task 262 (FIG. 5). When entering this flow, first S72
The detection signal PA2 is checked and it is determined whether it is 0 or not. If the result is YES, the process advances to S71, where the output terminal short failure flag including the F/P relay is prepared, and the process exits to NG. In other words, at this time, since the signal DIO0 is still 0, the transistor Q32 should be on, but since the signal PA2 is 0, it can be determined that the output terminal is short. Therefore, at this time, code "34" will be stored. Also, if the result in S70 is NO, the next S72
First, signal DIO0 is set to 1 to turn off transistor Q32, and then signal PA is turned off again in S73.
Examine 2 and then determine whether it becomes 1 or not. If the result in S73 is NO, you can exit as is, but if it is YES, in S74, the fuel pump 32
The harness leading to this will set up an open defect flag and will fail. That is, at this time, even though the transistor Q32 is turned off, the voltage from the power supply +B appears as the signal PA2, which means that the output harness is open. Therefore, at this time, code "35" will be stored. In addition, the abnormality check when the engine stalls is 1.
Don't do it repeatedly. Therefore, steps other than S605 and S606 in the flow of FIG. 16 are omitted. By the way, although not specifically explained above, in such conventional examples, the abnormality check of the ROM 104 of the microcomputer is performed as one of the programs in various tasks using the initialization program 204 (see Fig. 5) or interrupts. I was just going to do it. However, checking this ROM 104 requires a considerable amount of processing time; for example, with an 8-bit microcontroller normally used for EEC,
It took about 200 [mSEC]. Therefore, if the ROM is checked in the initialization program as in the conventional example described above, if the starter switch is activated immediately after the key switch is turned on, the engine control There is a problem that initialization is insufficient, making it difficult to start.Also, when using an interrupt task, the load on the microcomputer becomes so large that it may not be able to adequately follow engine control. It was hot. Therefore, in the past, in order to solve these problems, it was necessary to increase the processing power of the microcomputer, which had the disadvantage of increasing costs. Additionally, related devices of this type include:
There are also JP-A-53-110724 and JP-A-53-123728.
For example, the disclosure in Publication No. The purpose of the present invention is to eliminate the drawbacks of the conventional example described above, to be able to sufficiently check the ROM without increasing the performance of the microcomputer, and to accurately perform self-diagnosis and display information when an abnormality occurs in the ROM. To provide an EEC self-diagnosis alarm display device designed to In order to achieve this object, the present invention is characterized in that when the control circuit is switched to a display mode of a fault code representing a self-diagnosis result, the ROM is checked and the fault code is stored. shall be. Embodiments of the self-diagnosis alarm display device according to the present invention will be described below with reference to the drawings. FIG. 28 is a flowchart explaining the operation of one embodiment of the present invention, and as is clear from this figure,
This embodiment incorporates the operation for ROM check into the code display mode in the flowchart shown in FIG.
It is activated every 40 [mSEC] by the task, and first the display switch 1108 (Figure 7) is activated in S1.
is turned on, and if the result is NO, that is, the display switch 1108 is turned on.
When it is OFF, an alarm operation is performed in S2 and S3 depending on the presence or absence of the defective flag, as explained in connection with FIG. 11. On the other hand, when the result in S1 is YES, that is, when it is detected that the display switch 1108 is turned on, the process goes to S5 to S10, which are newly installed in this embodiment, and first, in this S5, the ROM is turned on.
It is checked by looking at the flag whether or not the check in step 104 has been completed, and if the result is YES, the process immediately jumps to S4, where a fault code display operation is performed as explained in FIG. However, if the check end flag of ROM 104 is not set, this
The result in S5 is NO, so proceed to S6 next.
Starts the check operation of ROM104, then in S7
Check whether the ROM check has finished or not, and if the result is NO, that is, the check in S6 has not finished, exit directly through S4.
Exit to. On the other hand, the result in S7 is YES, that is, ROM104
When the check has finished, turn to S8,
At S8, the ROM check end flag is set. Therefore, from now on, when entering this flow, it will immediately pass through S4 from S5. Now, after setting the ROM check end flag in S8, the process proceeds to S9, where it is checked whether or not a defect has been detected in the ROM 104. The result on S9 is
If NO, that is, there is no abnormality in the ROM 104 and no fault was detected by the check in S6, the process exits directly through S4 and exits to EXIT, but if the result in S9 is YES, that is, a fault has been detected in the ROM 104. Sometimes through the next S10
Store the error code "51" in RAM1104 and then exit to EXIT. Therefore, when entering this flow from now on, a malfunction code indicating an abnormality in the ROM 104 will be displayed. As a result of the above, according to this embodiment of the present invention, only when the display switch 1108 is turned on and the device enters the code display operation mode,
An abnormality detection operation of the ROM 104 will be performed, and the results will be displayed. On the other hand, this display switch 1108
The switch is turned ON most of the time when the engine is stopped or when the engine is in idle mode, so the load on the EEC microcomputer is quite light. Therefore, according to the embodiment described above, even if a considerable load is applied to the microcomputer by checking the ROM 104, the control operation of the engine is hardly affected, and there is no possibility that the starting of the engine becomes uncertain. There will be no more of that. Next, an embodiment of the ROM check operation at S6 in FIG. 28 will be described. Now, assuming that the ROM 104 has a capacity of 8 bits for each address, as shown in FIG. 29, the data of each address is added together as is to obtain a total value. This total value should have a very large number of digits, but take the lowest 8 bits and make it the Sum, and compare it with a pre-determined reference value to see if the two are equal. When the results are equal, it is assumed that there is no abnormality in the ROM 104, and when the results are not equal, it is assumed that a malfunction has been detected. According to this embodiment, the ROM 104 can be checked extremely easily and with considerable accuracy. By the way, in the above embodiment, the RAM
A battery 1102 is provided for backing up the battery 1104, but this battery 1102 may be one that directly supplies voltage from an automobile battery without going through a key switch, or a separate dry battery or the like may be provided. . Of course, if the RAM 1104 is a non-luminous memory, these are unnecessary. In addition, a warning lamp 110 is used to display the malfunction code.
6 may be omitted, and another display means, for example, a means capable of directly displaying numbers, characters, etc., may be provided, or if necessary, a fault code may be displayed by connecting with a plug or the like. In this case, the contents of the RAM 1104 can be displayed as they are in numbers or characters. As explained above, according to the present invention, EEC
Since the ROM included in the microcontroller can be checked with almost no effect on the engine control status, troubleshooting and maintenance can be done easily and in a short time, eliminating the drawbacks of conventional technology. A low-cost microcomputer can provide a fault location self-diagnosis alarm display device that can provide safe and reliable engine operating conditions at all times.

[Brief explanation of drawings]

Figures 1 to 6 are diagrams showing an example of an electronic engine control system applied to a fuel injection type internal combustion engine. Figure 1 is a cross-sectional view of the engine including a part of the control system, and Figure 2 is a schematic diagram of the ignition system, Figure 3 is a system diagram of the exhaust gas recirculation system, Figure 4 is a block diagram of the overall configuration of the control system, and Figure 5 is a diagram of the overall configuration of the control system.
Figure 6 is a diagram of the program system, Figure 6 is a memory configuration diagram showing the program contents, Figure 7 is a block diagram of the overall configuration of an example of a fault self-diagnosis alarm display device, and Figure 8 is an explanation of an example of a fault code. Figures 9a and 9b are explanatory diagrams showing examples of lamp lighting modes during alarm operation, and Figures 10a to c
11 is an explanatory diagram showing an example of a lamp lighting mode during code display operation, FIG. 11 is a flowchart showing an example of a method for distinguishing between alarm operation and code display operation, and FIG. 12 is a flow chart showing an example of alarm operation. , FIGS. 13 to 15 are flowcharts showing an example of code display operation, FIG. 16 is a flowchart showing an example of a basic pattern of an abnormality check, and FIG. 17 is a circuit showing an example of an ignition system abnormality check system. 18 is a flowchart showing the operation, FIG. 19 is a flowchart showing an example of the abnormality check operation of the air flow sensor, and FIG. 20 is an explanatory diagram of the operation of the air flow sensor.
Fig. 21 is a circuit diagram showing an example of a bypass valve abnormality check system, Fig. 22 is a flowchart for explaining its operation, Fig. 23 is a circuit diagram showing an example of a pressure control valve abnormality check system, and Fig. 24 is a circuit diagram showing an example of a bypass valve abnormality check system. FIG. 25 is a circuit diagram showing an example of a fuel pump abnormality check system, FIGS. 26 and 27 are flowcharts for explaining the operation, and FIG. 28 is an embodiment of the present invention. FIG. 29 is a flowchart showing the ROM abnormality detection operation in FIG. 29, and is a conceptual diagram showing one embodiment of the ROM check. 104...ROM, 1102...Battery for backup, 1104...RAM constituting non-luminous memory, 1106...Warning lamp, 1108...
...display switch.

Claims (1)

[Claims] 1. While the engine is operating, self-diagnosis of various sensors and actuators necessary for engine control is continuously performed at predetermined timing and under predetermined conditions, and the results of this diagnosis are used for engine control. A self-diagnosis alarm for an electronic engine control device that stores data in a memory that can retain data even when the device stops operating, and reads the data from the memory and displays it on a predetermined display means by operating a predetermined switch. In the display device, a check means starts a self-diagnosis process of the read-only memory included in the engine control device on condition that a signal generated in response to the operation of the switch is input, and the check means detects an abnormality. and control means for storing data representing the abnormality in a memory capable of holding the data when detected, and configured to perform self-diagnosis of the read-only memory included in the engine control device. A self-diagnosis alarm display device for an electronic engine control device, characterized by: 2. In claim 1, the check means of the read-only memory includes means for adding data at each address of the read-only memory, and data of a lower predetermined digit of the addition result by the means. provided with a means to compare the data with reference data;
A self-diagnosis alarm display device for an electronic engine control device, characterized in that it is configured to detect an abnormality in the read-only memory based on a matching state of these data.