JPH02301830A - Information processing system - Google Patents

Abstract

PURPOSE:To improve the memory access processing speed of the system by simultaneously executing plural memory access in a logically consistent extent. CONSTITUTION:A register file 404 stores operands necessary for arithmetic operations and a priority score board 103 detects register conflict between plural processing units 1 and 2 and avoids the conflict in accordance with their priority. Data units 102 and 105 make data readout/writing processes between a memory and the register file 404 and a controller 104 detects memory address conflict between the data units 102 and 105 and decides executing order of the units 102 and 105 in accordance with their priority. Therefore, memory access is independently executed at the data unit corresponding to the each processing unit in a logically consistent extent. Thus the processing speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing system that performs data processing in parallel or serially.

[Conventional technology]

FIG. 4 is a block diagram showing the main part configuration of an information processing apparatus that employs this kind of conventional information processing method. This figure 4 was created by Carl Dobbs, Paul Reed and
Written by Tommy Ng: Supercomputing
g on Chip, VLSI SYSTEMS DES
IGN Vol, IX, No, 5. May 1988
．． It is based on what is shown in pp. 24-33, and in the figure, 401 is an integer unit that performs integer operations;
2 is a floating point unit 1-14 that performs floating point operations.
03 is a data unit that performs data read/write processing between memory and registers, 404 is a register file that stores information for data processing, 405 is a scoreboard that detects and avoids register conflicts, 40G
is an instruction unit that fetches, decodes, and transfers instructions to functional units, and 407, 408, and 409 are internal hashes.

Next, the operation will be explained. The instruction unit 406 is pipelined into three stages: instruction fetch, decode, and transfer, and passes the instruction to the decode stage after completing the fetch in one clock cycle. In the decoding stage, the instruction is partially decoded and a register request is issued to the scoreboard 405 in order to prefetch the operands necessary for the operation from the register file 404 to the functions UNISO 1 to corresponding to the instruction. Each register in register file 404 has a scoreboard bit that is set when that register is stalled and cleared when the data operation is complete.

Scoreboard 405, which receives the register request from instruction unit 406, examines the scoreboard bit and signals available to instruction unit 406 only if it is in the clear state. Upon receiving the availability signal from the scoreboard 405, the instruction unit 406 forwards the instruction to the corresponding functional unit. Each functional unit also has several pipeline stages and executes instructions using prefetched operands.

The data unit 403 also has one functional unit r, 3
pipelined into two stages.

In stage 1, address calculation is performed using prefetched operands, and the calculation result is passed to the next stage. In stage 2, the external data address bus is driven based on the sent address. If the sent instruction is a store instruction, the data to be stored at this stage is fetched from the register file 404 and the address and data are placed in the external lot. Stage 3 monitors the response of the memory system. In the case of a load instruction, the data bus is read at this stage and the data is taken into the register.

In the conventional method, data processing is performed using such a procedure.

[Problem to be solved by the invention]

However, in conventional information processing systems, as mentioned above, the instruction unit can only decode one instruction in one cross cycle, so only one operation result can be obtained in each cross cycle, and memory access processing There was a problem in that it was difficult to improve the speed.

This invention was made in order to solve the above-mentioned problems, and it is an information processing method that can simultaneously execute multiple memory accesses within a logically consistent range and improve processing speed. The purpose is to provide.

[Means to solve the problem]

In the information processing method according to the present invention, a register file 404 that stores information for shared data processing in a plurality of processing units 1 and 2, and a register conflict that occurs between the plurality of processing units 1 and 2 are provided. 102. Register conflict avoidance means (priority scoreboard 103) that has a function of detecting and avoiding according to priority, and a data unit compatible with each processing unit 1.2 that performs data read/write processing between memory and register file 404. 1
05 and the data unit 102.105 is detected, and the data 5=unit 102.105 is assigned according to the priority. ]05, and when a plurality of memory accesses are simultaneously issued from the instruction unit Idol, 106, the data unit I-102, 105 is executed in parallel according to the priority. It is characterized by performing data processing.

[Effect]

The register file 404 includes a plurality of processing units 1,
2 is shared and stores information for data processing. Register conflict avoidance means (priority scoreboard 103
) detects register conflicts occurring between a plurality of processing units 1 and 2 and avoids them according to priority. data unisol l-
102 and 105 perform data read/write processing between the memory and the register file 404. Control device 1
04 detects a memory address conflict that occurs between data units 102 and 1.05, and determines the execution order of data units 102 and 105 according to their priorities. Therefore, multiple memory accesses are
When issued simultaneously from 6, data Uniso h 102.1
In 05, data processing is performed in parallel according to the priority=6-.

[Embodiments of the invention]

FIG. 1 is a block diagram showing the main part configuration of an information processing apparatus employing an information processing method according to an embodiment of the present invention.

In FIG. 1, components corresponding to those shown in FIG. 4 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 1, 101 is an instruction unit that fetches the Nth (N=0.1...) instruction, decodes it, and transfers it to other functional units, and 06 fetches the (N+1)th instruction. 102 is a data unit that receives and receives load/store instructions from the instruction unit 101 and performs memory access;
105 is a data unit that receives load/store instructions from the instruction unit 105 and performs memory access;
3 has two instruction units 101.3. ], 104 is a priority scoreboard as a register conflict avoidance means that detects a register conflict occurring between two data units 102 and 105 and avoids it according to the priority, and 104 detects a memory address conflict that occurs between two data units 102 and 105 and avoids it according to the priority. 10
This is a control device that determines the execution order of 2.105. The processing unit 1 includes an integer unit 401, a floating point unit 402, an instruction unit 10, and a data unit 102.
It is equipped with The processing unit 2 is an integer unit 401,
A floating point unit) 402, a data unit 105, and an instruction unit 106 are provided.

Figure 2 shows each data unit 102 and 105 in the case where there is no memory address conflict and when there is a memory address conflict.
Instructions processed in 02.105 (load/store instructions)
This is a diagram showing how the operations of two data units 102 and 105 change depending on the situation.

FIG. 3 is an explanatory diagram showing the function of the control device 104 and the operation of the two data units. (a) The figure shows a case where there is no memory address conflict between two data units 102 and 105;
is processing load instructions, and data unit 7 105 is processing store instructions. (b) The diagram shows two data units]
, 01, and 103, there is a memory address conflict. (i) represents the case where all the instructions causing the memory address conflict are load instructions, and (11) represents the case where the instructions causing the conflict include one or more store instructions ( In the figure, the data unit 102 processes load instructions and the data unit 105 processes store instructions). 301 is a stage 1 for performing address calculation; 302 is a stage 2 for driving an external data address bus; and 303 is a stage 3 for monitoring the reaction of the memory system.

Next, the operation will be explained. Except for load/store instructions, each processing unit fetches instructions as in the conventional example.
Processes in the order of decryption, transfer, execution, and storage.

The operation of the control unit 104 and the two data units 102 and 105 for load/store instructions will be explained based on FIG. Load/store instruction is instruction unit 1
When transferred from data unit 01.106 to data unit 102.105 (■ in figures (a) and (b)), prefe = 9 - transferred operand (from register file 404 to stage in figures (a) and (b)) 1 to 1)) is used to calculate the address in stage 1. Once the address is determined, each data unit (102, 105) notifies the controller 104 of the transferred command and at the same time
Request the address calculated in (■ in figures (a) and (b)). The control device 104 holds all memory addresses and instructions (load/store) being processed in each stage of the two data units 102 and 105. The control device 104, which has received a memory address request from one or both data units, uses the memory address requested by the one data unit and the memory address processed at each stage of the other data unit (
(including memory addresses that are being bent). Memory address conflicts within the same data unit do not need to be bent since each data unit is pipelined. For example, data unit
-102, the controller 104 identifies the memory address requested by the data unit 102 and the stage 1. Stage 2. The memory addresses being processed in stage 3 are compared to determine whether a memory address conflict has occurred. As a result of the comparison, if no memory address conflict occurs, the control device 104 grants execution permission to the requested data unit (■ in the diagram (a)). In the case of the figure (a), both data units 101 and 105 perform memory access in parallel (■, ■ in the figure (a)).

When memory address conflict occurs between data units 10L105, there are two levels: conflict occurring between two instructions and conflict occurring between three instructions. A conflict between two instructions requires two data units 101, 10.
There is a conflict between the newly accepted instructions in the data unit 5, and a conflict between the newly accepted instructions and the instructions being executed in the preceding stage of the other data unit. Conflicts that occur between the three instructions include a conflict that occurs between an instruction that is currently being executed in the preceding stage, an instruction that is bending, and a newly accepted instruction, and a conflict that occurs between the instruction that is currently being executed in the preceding stage of the data unit 105, and a newly accepted instruction. There is a conflict between two newly accepted instructions. In either case, first the control bag W
104 checks whether the multiple instructions causing the conflict are all load instructions, and if they are all load instructions, parallel processing is possible, so the control unit 104 simultaneously executes them on the data units requesting the memory address. Issue permission ((b) figure (i)).

In the case of all load instructions, both data are uniso 1 to 102°105 as in the case where there is no memory address conflict.
performs memory access in parallel ((b) ■ in figure (i),
■). If one or more store instructions are included in the multiple instructions causing contention, parallel processing is not possible, so the control device 104 determines the execution order according to priority and issues execution permission. In this example, 0, the instruction already being executed in the preceding stage, the instruction 2 that is bending, the instruction 3 received by the data unit I-1 (1,02), the data unit I-2 In step (105), the priority of the received commands decreases in the order of received commands. If a conflict occurs between newly accepted instructions in two data units 102 and 105, priorities 0 and 1 are not applied, so priority 2 is used to transfer instructions to data unit 102.
Priority is given to orders that are marked. If there is a conflict between a newly accepted instruction and an instruction being executed in the preceding stage of the other data unit, the newly accepted instruction will be bent until the preceding stage finishes execution due to priority O. I have to throw it. When there is a conflict between an instruction currently being executed in the preceding stage, an instruction that is bending, and a newly accepted instruction, the currently executing instruction is given top priority with priority O, and then bending is given with priority 1. Orders take priority. Instructions being executed in the preceding stage of data unit 105 and 2
In a conflict between two newly accepted instructions, priority O gives priority to the currently executing instruction, followed by priority 2, which gives priority to the instruction accepted into data unit 102.

The data unit I/I, which has received execution permission, executes memory access in the same manner as in the conventional example. When the execution of the instruction is completed, in stage 3 each data unit 1.02, 105 informs the controller 104 of the memory address at which the processing has ended. (■ in (a) figure and (b) ■ in figure.

[phase]). Control device 1 that received the memory address
04 erases the held memory address and instructions (load/store). If there is a request for the next memory address, the control device 104 checks again whether there is a memory address conflict between the memory addresses, determines the execution order according to the priority, or executes the bending instruction if there is no request for the memory address. give permission.

In this way, the information processing system of the above embodiment processes instructions in parallel/serially in a plurality of processing units, detects and avoids register conflicts between processing units on the priority scoreboard, and processes data between the data units 71 and 71 in the control device. Detects memory address conflict that occurs in the process, determines the execution order according to the priority, and independently executes memory access within a logically consistent range in the data unit corresponding to each processing unit.

〔Effect of the invention〕

As described above, according to the present invention, a data unit is provided for each processing unit, register reading is performed independently and in parallel between each processing unit and the register file corresponding to each processing unit in the control device, and register writing is performed by each processing unit. Since this is performed independently between the unit and all register files, it is possible to simultaneously execute multiple memory accesses within a logically consistent range, resulting in the effect of improving processing speed in memory access processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part configuration of an information processing device that employs an information processing method according to an embodiment of the present invention, and FIG. 2 shows instructions and data units transferred to two data units in this embodiment. FIG. 3 is a block diagram illustrating the operation of the control device and the operation of the two data units in this embodiment. FIG. 4 is a block diagram showing the main part configuration of an information processing apparatus employing a conventional information processing method. 1.2...processing unit, 1.01,106...
・Instruction unit, 102. 105 ... Data Uniso I, 103 ... Priority scoreboard (register conflict avoidance means'), 104 ... Control device, 40
4...Register file. Agent: Masu Oiwa 1ji, (2 people) Procedural amendment (voluntary)

Claims (1)

[Claims] In an information processing device including an instruction unit that fetches, decodes, and transfers instructions and a plurality of processing units that perform data processing, a register that stores information for data processing to be shared among the plurality of processing units. Register conflict avoidance means that has a function to detect register conflicts that occur between files and multiple processing units and avoid them according to priority, and a control device having a function of detecting a memory address conflict that occurs between the data units and determining the execution order of the data units according to the priority, and a plurality of memory accesses are simultaneously issued from the instruction unit. The information processing system is characterized in that when the data unit is selected, the data units perform data processing in parallel according to the priority.