JPH02302183A - Signal processing circuit for ccd image pickup element - Google Patents

Abstract

PURPOSE:To reduce the noise for the horizontal blanking period by making the phases of two signal sampling pulses used for subtraction of correlation double sampling coincident with each other for the horizontal blanking period when a DC level is clamped. CONSTITUTION:Sample hold signals obtained respectively are given to a sample- and-hold circuit 2, and the phases are matched by a delay circuit 4 added to the output of the circuit 2 and the resulting signal is fed to a subtraction circuit 7, where the signals are subtracted together to obtain a difference signal. As a result, reset noise and low frequency noise superimposed on the signal are reduced. In this case, the phase of a pulse fed to a sample-and-hold circuit 3 is made equal to the phase of the pulse given to the sample-and-hold circuit 2 at a portion including the clamp period in the horizontal blanking period. Thus, a difference signal of two sample-and-hold signals after subtraction is zero and the noise attended thereto is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing circuit for a CCD type imaging device that reduces noise generated when horizontally clamping an output signal of a solid-state imaging device.

[Conventional technology]

Generally, in order to accurately reproduce the brightness level in a television camera, the output signal obtained from the imaging probe is clamped at a constant DC level of about m within the horizontal blanking period, and then adjusted to match the desired signal level. There is.

At this time, random noise existing within the horizontal blanking period is sampled and held by the clamp pulse, so sideband noise generated in the harmonics of the pulse mixes into the baseband.

This noise is called clamp noise, and when it is held in the clamp circuit, it becomes horizontal noise superimposed on one scanning line on the reproduced image, so it is easily noticeable and leads to deterioration of the S/N ratio.

On the other hand, the output signal of a CCD type imaging probe is generally subjected to noise reduction by a method called correlated double sampling described in Japanese Patent Laid-Open No. 10500/1983.

Correlated double sampling will be briefly described using FIG.

Figure 2 (a) schematically shows the output signal for each pixel obtained from the CCD type image sensor in synchronization with the horizontal clock pulse, and each horizontal clock cycle is a period during which only output amplifier noise exists, and reset. It is divided into a period t2 in which only noise exists, and a period t2 in which reset noise and pixel signals exist. FIG. 2(b) shows the reset pulse. Here, a signal obtained by sampling and holding the period t1 of only reset noise using the pulse shown in Fig. 2 (C) (Fig. 2 (e))
and the period t2 in which the reset noise pixel signal exists is set to the second period t2.
The signal sampled and held using the pulse shown in figure (d) (second
Figure (f)) is matched in phase, and their difference signal (Figure 2 (f)) is adjusted.
If g)) is obtained, reset noise can be reduced.

[Problem to be Solved by the Invention] However, in general, the cone f? of the output amplifier is determined by correlated double sampling. f', (t) is the phase difference between tx and 72 as φ
When, +' cas(t )= f n(t )
-fn (is converted to -φ), and sideband noise generated in the harmonics due to the sample-and-hold pulse is mixed into the baseband, resulting in an increase. Therefore, in a television camera using a CCD type imaging probe, reset noise and low frequency noise can be sufficiently reduced by correlated double sampling, but the noise of the remaining output amplifier increases with the addition of aliasing. There will also be an increase in traversal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal processing circuit for a CCL type imaging probe that minimizes the noise present during the horizontal blanking period, thereby minimizing the noise generated during the subsequent horizontal clamping operation. be.

[Means to solve the problem]

In the present invention, the noise in the horizontal blanking period is reduced by matching the phases of the sampling IJ pulses of the two signals in which correlated double sampling is performed during the horizontal blanking period in which the DC level is clamped.

〔Example〕

FIG. 1 shows a configuration diagram of the present invention. The sample-and-hold circuit 2 samples and holds the period t1 in which only the reset noise of the output signal of the CCVCC type imaging probe 1 (FIG. 3(a)) exists, and samples the period tz in which the reset noise and pixel signal exist. - Sample and hold in hold circuit 3. Each sample and hold pulse is generated by a pulse generator 5
Supplied from. Next, the obtained sample and hold signals are matched in phase by a delay circuit 4 added to the output of the sample and hold circuit 2, and then added to a subtraction circuit 7 for subtraction to obtain a difference signal. As a result, reset noise and low frequency noise superimposed on the signal are reduced. At this time, the phase of the pulse sent to the sample-and-hold circuit 3 is changed by the horizontal clamp part phase conversion circuit 6 as shown in FIG. 3(b).

As shown in (c), the phase of the pulse sent to the sample-and-hold circuit 2 is set to be the same in the horizontal blanking period including the clamp period.

As a result, the difference signal after subtraction of the two sample-and-hold signals becomes zero, and the noise associated with it becomes the smallest.

Therefore, the output signal of the subtraction circuit 7 is applied to the horizontal clamp circuit Wt8.
After DC clamping during the horizontal blanking period, the NTSC signal 10 obtained through the signal processing circuit 9 is
In this case, aliasing noise due to harmonics of the clamp pulse can be minimized.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a signal processing circuit for a CCL type imaging cord that can obtain an imaging signal without an increase in noise even when horizontal clamping is performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal processing circuit according to an embodiment of the present invention;
Figure 2 is an explanatory diagram of correlated double sampling, and Figure 3 is an illustration of correlated double sampling.
FIG. 3 is an operation waveform diagram of the circuit shown in the figure. DESCRIPTION OF SYMBOLS 1... CCD type imaging probe, 2... Sample and hold circuit, 3... Sample and hold circuit, 4... Delay circuit, 5... Pulse generator, 6... Horizontal clamp part Phase conversion circuit, 7... Subtraction circuit, 8... Horizontal clamp circuit, 9... Signal processing circuit, 10... NTSC
output signal. ¥2 Diagram

Claims (2)

[Claims] 1. a first sample circuit and a second sample circuit that sample the sampled imaging signal at a sampling period; and a subtraction circuit that obtains a difference signal between the output signal of the first sample circuit and the output signal of the second sample circuit. and a clamp circuit for fixing the DC level of the output signal of the subtraction circuit, the signal processing characterized in that the sampling phase of the first sample circuit and the second sample circuit is made variable at a predetermined timing. circuit. 2. the first sampling the output signal of the image sensor;
2. The signal processing circuit according to claim 1, wherein the sampling phase of the second sampling circuit is made to match during a certain period including an operating period of the clamp circuit.