JPH0230229B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sampling pulse correction device that is effective for use in, for example, a system that receives and reproduces a television signal containing digital character, symbol, and graphic information.

In a communication system, when incoming digital data is sampled using a sampling pulse, the phases of the data bits and the sampling pulse are required to match with high accuracy. However, the sent data is not always sent with a stable phase due to disturbances or internal factors, and the sampling pulse may also have a phase shift due to temperature drift. For this reason, there is a need for automatic adjustment means for accurately matching the phase of the sampling pulse with the incoming data.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a sampling pulse correction device with a simple configuration that can automatically correct the phase of a sampling pulse and also achieves high quality phase alignment accuracy. shall be.

Embodiments of the present invention will be described below with reference to the drawings.

The format of the television signal used in teletext broadcasting is set as shown in FIG. FIGS. 1a and 1b show vertical blanking period portions of the first field and the next field of a composite video signal, and V is a vertical synchronizing signal.

Teletext packets 1 and 2 are set at the rear of this vertical retrace period, for example, at the 20th H (H: one horizontal period) after the end of the previous field. The format of this teletext packet is set as shown in FIG. 1c. H is a horizontal synchronization signal, and 5 is a color burst. The teletext packet 2 is formed by a header section 6 and an information section 7. This teletext packet 2
The details are as shown in FIG. 1d.

That is, the header section 6 contains the clock run in signal CRI and the framing code.
It is composed of FC, identification code IDC, program codes PC1, PC2, etc.

The clock line signal CRI is a signal for adjusting the phase of the clock pulses necessary for sampling the data in this teletext packet. The framing code FC is a code that indicates the beginning of data. Identification eye code IDC is a code for identifying display format, transmission signal format, etc. Program code PC1,
PC2 is a code indicating the type of text information program.

The teletext packets described above are processed, for example, by a system as shown in FIG. 1
Reference numeral 1 denotes an input terminal to which an intermediate frequency of a teletext television signal is input. The signal applied to this input terminal is subjected to image detection by the image detection circuit 12. The video-detected composite video signal is input to a waveform shaping circuit 13 that extracts teletext packets and performs waveform shaping. Further, the composite video signal is input to a synchronization separation circuit 21 that separates a vertical synchronization signal V and a horizontal synchronization signal H.

The vertical synchronization signal V and horizontal synchronization signal H separated from the synchronization separation circuit 21 are sent to the vertical position counter 2.
2 is input. This vertical position counter 22 is
It is reset by the vertical synchronizing signal V, and the horizontal synchronizing signal H
, it is possible to obtain a sampling pulse corresponding to the position where the teletext packet is folded.

The sampling pulse obtained by the vertical counter 22 is input to the waveform shaping circuit 13. As a result, the teletext packet described in FIG. 1 is extracted from the waveform shaping circuit 13, and its waveform is shaped. The output obtained from this waveform shaping circuit 13 is input to a sampling circuit 14 and also to a clock run-in signal detection circuit 16.

The clock run-in signal detection circuit 16 extracts the clock run-in signal CRI shown in FIG.
This clock pulse generating circuit 17 has a function of generating continuous clock pulses in synchronization with the clock run-in signal. Continuous clock pulses output from the clock pulse generating circuit 17 are input to the sampling circuit 14 and used as data sampling pulses.

In the sampling circuit 14, various types of data as shown in FIG. The output of the sampling circuit 14 is also input to a framing code detection circuit 18.
This framing code detection circuit 18 performs detection by comparing a predetermined framing code and an input code, detects a point where the codes completely match, and detects the beginning of data in the buffer memory. This is what you set. Framing code detection circuit 18 is driven by clock pulses from horizontal position counter 23, for example.

The horizontal position counter 23 is reset by the horizontal synchronization signal H from the synchronization separation circuit 21, and counts the clock pulses from the clock pulse generation circuit 17. This horizontal position counter 2
The count information of 3 is also added to the address circuit 24. Further, this address circuit 24 includes:
The previous vertical synchronization signal is also input. This address circuit 24 can generate address data regarding the horizontal and vertical directions of the image obtained by the currently input composite video signal.

As described above, the buffer memory 15 stores the contents of a teletext packet when it arrives. The data stored in this buffer memory 15 is processed by a microcomputer.

Central processing unit (hereinafter referred to as CPU) 30
decodes the data contents of the buffer memory 15. For example, what is the data format?
What the program is like.

For example, a case will be explained in which it is desired to display a weather forecast as a teletext broadcast. If it is desired to display the weather forecast, a command signal for processing the weather forecast data can be input by operating the keyboard 40. The weather forecast program is specified by the program code shown in FIG. For example, program code
Assuming that the data of PC1 is sending the weather forecast, this program code PC1 is
The calculation is processed by . As a result, if the data in the program code PC1 matches the data designated from the keyboard 40, it is determined that the data in the buffer memory 15 is data for a weather forecast. A command signal for reproducing the weather forecast specified from the keyboard 35 is stored in a random access memory (hereinafter referred to as RAM).

The weather forecast pattern data read from the buffer memory 15 is finally stored in the pattern memory 33 as character data and signal data.
The color data is stored in color memory 34.

The data read from the buffer memory 15 is itself stored in the pattern memory 33 as character data or storage data, but if the transmission method is a code transmission method, the data read from the buffer memory 15 is decoded and read. Predetermined character data, that is, characters, symbols, and graphic data may be read out from the only memory (hereinafter referred to as ROM) and stored in the pattern memory 33 or the like. Therefore, a character ROM 39 is also provided.

As mentioned above, character, symbol, and graphic data are stored in the pattern memory 33 based on the data derived from the buffer memory 15.
If a teletext packet in a vertical period is extracted only once, sufficient data for character display cannot be obtained. Therefore, each time there is a vertical synchronization period and each time a desired program is detected, the data is sequentially stored in the pattern memory 33.

When data is stored in the pattern memory 33 and color memory 34, address designation data specifying the storage address may be input together with the data to determine in which address the data is stored.

When data stored in the pattern memory 33 and color memory 34 is read out and displayed, the data in the pattern memory 33 is sent to the pattern decoder 35, and the data in the color memory 34 is sent to the color decoder 36 to be converted to DC. is converted to
The output interface 37 synthesizes the signals.

Then, it is combined with the composite video signal in a combining circuit 38. Pattern memory 33, color memory 34
The data read timing is based on a command signal from the CPU 30. The CPU 30 constantly decodes address data (corresponding to the current screen beam irradiation position) input from the address circuit 24. If this address data matches the desired display specification data set in RAM32,
Read signals corresponding to these address data are applied to the pattern memory 33 and color memory 34.

The display data is included in a program stored in the RAM 32, and various display formats can be set according to changes in this display designation data and program switching.

In a system operating as described above, it is important to sample teletext packet data without error in evaluating its performance.

Next, the sampling pulse generator according to the present invention will be explained. In FIG. 3, 51 is an input terminal to which a signal from the waveform shaping circuit 13 is applied, and this is connected to one input terminal of an AND circuit 52. A gate pulse for gating the clock run-in signal is input to the other input terminal of the AND circuit 52 through the input terminal 53. The gate pulse at input terminal 53 is also applied to the enable terminal of up-down counter 54. The output of the AND circuit 52 is output from the phase detector 5
5, and its phase is compared with the sampling pulse at the output terminal 56.

On the other hand, 60 is an original clock pulse generator;
The resulting pulse frequency is eight times the sampling pulse frequency. The output of this clock pulse generator 60 is input to a counter. The counter is a three-stage flip-flop circuit 61, 6.
3, 65, exclusive OR circuit 62, 6
4, 66, etc.

The output of the counter 54 is the data selector 6
8 and exclusive OR circuits 62, 64, 6
6 is input. The delay line of the delay device 67 is provided with a plurality of taps, and the output terminal of each tap is connected to each input terminal of the data selector 68. This data selector 68 selects an input terminal according to the content of data input to the control terminal.
Any one of the signals D ₁ to _{D 4} is selected and output to the output terminal D ₀ . The pulse obtained at this output terminal is used as a clock pulse for the up-down counter 54 and is passed through the flip-flop circuit 69 to the phase detector 55.
It is also used as a comparison pulse. Of course, it can also be used as a sampling pulse.

In the delay device 67 described above, the delay time for each stage is selected to be τ _D =1/4·1/8·1/f _S .

On the other hand, the phase detector 55 compares the phase of the clock line signal with a pulse obtained by frequency-dividing the sampling pulse. The phase difference appears across capacitor 57 as an error voltage. That is, the buffer circuit 56 is in an active state when the signal is "1", the capacitor 57 is discharged when the sampling pulse is "0", and charged when the signal is "1". If the period of "0" and the period of "1" are equal, the voltage across the capacitor 57 settles to its original state, that is, about half of the power supply voltage.
This voltage is input to a comparator 58 and compared with a reference voltage 59. This comparator 58 outputs "1" if the input voltage is higher than the reference voltage;
If it is low, "0" is output, which is input to the control terminal of the up-down counter 54.

Now, if the clock run-in signal and the sampling pulse are out of phase and the output of the comparator 55 becomes "1", the up-down counter 54 counts up at the falling edge of the sampling pulse. Assuming that the signal at the terminal _D4 has been derived, from this point on, the signal at the input terminal _D3 will be output and its phase will advance. In this way, if the output of the comparator 55 continues to be "1", the up-down counter 54
counts up one after another, and the signal derived to the output terminal D ₀ is from the initial position of D ₄ to D ₃ , D ₂ ,
The output changes to _D1 , then returns to _D4 , and an output appears at terminal C of the up-down counter 54, which inverts the phase of the clock input to the flip-flop circuit 63. Similarly, even the output phase of the flip-flop circuit 65 is controlled. Conversely, when the output of the comparator 55 is "0", that is, the phase is leading, the up-down counter 54 is
It performs a down-count operation, and the phase of the sampling pulse output is controlled to be delayed.

According to the above-described apparatus, the original clock pulse is frequency-divided by the flip-flop circuits 61, 63, and 65 to obtain the sampling pulse frequency. In this case, exclusive OR circuits 62, 64, 6 are provided on the input or output side of the flip-flop circuit.
6, and is configured to be able to invert the input phase or output phase. This is effective in widening and speeding up the phase adjustment range of the sampling pulse. Next, the sampling pulse obtained by frequency division as described above can be subjected to finer phase adjustment by a delay device 67 and a data selector 68. The up-down counter 54 is capable of up-counting or down-counting only during the gate pulse period applied from the input terminal 53, and holds the count value during other periods.
The lower bits of this up-down counter 54 are:
Since it is applied to the data selection control terminal of the data selector 68, adjustment by the lower bits means fine adjustment. The upper bit of the up-down counter 54 is also applied to the control terminal of the pulse inversion means of the frequency divider. This means coarse adjustment, i.e. quick adjustment and expansion of the adjustment range. The clock run-in signal period and the gate pulse must be synchronized, and this can be done, for example, by the following means. That is, the clock run-in signal detection circuit 16 uses a tuning circuit that tunes to the frequency of the clock run-in signal, and a pulse is generated when a high Q is obtained in this tuning circuit.

As described above, the present invention can provide a sampling pulse correction device with a simple configuration that can automatically correct the phase of a sampling pulse and can achieve high quality phase alignment accuracy.

[Brief explanation of drawings]

Figures 1 a to d are diagrams showing an example of the format of a television signal used in teletext broadcasting;
FIG. 2 is an explanatory diagram of the configuration of a system for processing data of a teletext signal, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. 52...AND circuit, 54...Up-down counter, 55...Phase detector, 60...Original clock pulse generator, 61, 63, 65...Flip-flop circuit, 62, 64, 66...Exclusive OR circuit , 67...Delay device, 68...Data selector, 69...Flip-flop circuit.

Claims (1)

[Claims] 1. A frequency divider having means capable of dividing the frequency of the original clock pulse and inverting the phase during the transfer of the clock pulse; a delay device that derives outputs with different amounts of delay; a data selector that can select and output one of the outputs with different amounts of delay; and the output of this data selector and a reference signal for data sampling. a phase detector that compares the phases of clock run-in signals and outputs a phase error voltage of both signals; a comparator that generates a positive or negative control output depending on the result of comparing the phase error voltage and a reference voltage; and this comparator. The count output of the lower bit is sent to the control terminal for data selection of the data selector, and the upper bit is sent to the control terminal of the pulse inversion means of the frequency divider. What is claimed is: 1. A sampling pulse correction device comprising: an up-down counter;