JPH02304662A - Electronic apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to electronic equipment, and particularly to electronic equipment configured by connecting a plurality of different devices in parallel via a common signal bus consisting of a plurality of signal lines. .

[Prior Art] Conventionally, there has been known a connection method for electronic devices in which a plurality of different devices are connected in parallel via a signal bus.

Various floppy disk interface systems, 5C3I interface systems, and the like are known as connection systems for such devices.

In this type of connection system, the following method is used to determine whether or not a device such as a personal computer serving as a main device is connected.

1) A method of installing a dedicated signal line in advance to identify whether a certain device is connected.

2) A method of accessing a device from the main device using software and determining whether the device is connected.

[Problems to be Solved by the Invention] However, the conventional configuration as described above has the following problems.

First, method 1) requires a dedicated signal line with the number of bits that can express a binary number corresponding to the maximum number of devices that can be connected. It must be an axiom.

In addition, method 2) requires access time to confirm the connection, and depending on the access method of the connected device, access from the main device may not be possible.
Connection confirmation may not be possible.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to enable connected devices to be identified easily, inexpensively, and quickly without impairing the expandability of the system.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an electronic device configured by connecting a plurality of different devices in parallel via a common signal bus consisting of a plurality of signal lines. An electrical resistor having a different resistance value within each of the plurality of devices is connected between the plurality of signal lines constituting the signal bus, and the voltage of a predetermined signal line among the plurality of signal lines is set to one of the plurality of devices. A configuration is adopted in which a device connected to a predetermined device via the signal bus is recognized by detection in the predetermined device.

[Operation] According to the above configuration, a device connected to a predetermined device can be recognized by a simple measurement process of detecting the voltage of the signal line forming the signal bus.

[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings.

FIG. 1 shows the configuration of an electronic device adopting the present invention.

In FIG. 1, reference numeral A is one of the devices constituting the system, and in this embodiment, it is a device used as a host such as a personal computer.

The device A has a CPU 24 including a microprocessor that controls various parts of the device (not shown). CPU
24 controls the entire device and determines connected devices according to a program described later stored in the ROM 24r.

Reference numeral B denotes a device connected to device A. In this case, device B is composed of peripheral equipment of device A, such as a printer, a magnetic disk drive, and various data output devices. Interface signal lines 11 to 13 of device A and device B are connected via a connector 90.

The signal lines 11 to 13 are configured as signal buses that can be connected in parallel.

Inside device A, signal line 11 is pulled up to the power supply voltage of device A (5V in this case), and signal lines 11 and 12 are connected by resistor 21, and signal lines 12 and 13 are
are connected by a resistor 22, and the signal line 13 is connected to ground potential.

Further, inside the device B, a resistor 31 is connected between the signal lines 11 and 12, and a resistor 32 is connected between the signal lines 12 and 13. A known input/output circuit inside device A or B is connected to the signal lines 11 and 12, so that data can be transferred between both devices based on a predetermined interface procedure.

Each resistance value R of the resistance 21.22 between the signal buses of device A or the resistance 31.32 between the signal buses of device B
11%R21%R12 and R22 are set to unique values for each device. The voltage of the signal line 12 is input to an AD converter 23, and after being digitized, it can be input to the CPU 24.

Therefore, by detecting the voltage of the signal line 12, the CPU 24 can detect whether or not the device B is connected.

Here, the resistance value R11, R of resistor 21.22.31.32
21%R12 and R22 are 200Ω and 100Ω, respectively.
Assuming 180Ω and 80Ω, if device B is not connected, the CPU 24 will receive 1.6Ω through the A/D converter 23.
Detects 6V.

On the other hand, when device B is connected as shown, the voltage of the signal line 12 is the divided voltage value when the power supply voltage of 5V is connected in series with the parallel connection of the resistor 21.31 and the parallel connection of the resistor 22.32. Therefore, with the above resistance value setting, it is approximately 1.59V.

On the other hand, device A is connected to device B via connector 90.
Instead, a device C as shown in FIG. 2 can also be connected. Within device C, signal lines 11.12 are connected by resistors 41 and signal lines 12.12, as shown in FIG.
13 are connected by a resistor 42.

Here, assuming that the resistance values R13 and R23 of the resistors 41.42 are 160Ω and 60Ω, respectively, when the device C is connected to the device A, the CPU 24 converts the voltage of the signal line 12 to 1 through the A/D converter 23. Detects 48V.

In this way, the CPU 24 of device A
13 can be identified via the voltage of the signal line 12. FIG. 3 shows a procedure for determining the connected device of the CPU 24 stored in the ROM 24r. Here, for ease of explanation, it is assumed that only one of device B to device C is connected to device A.

First, in step S1 of FIG.
Digitized voltage values of the signal line 12 when no device is connected to the connector 90, when device B is connected, and when device C is connected within a predetermined address in M24r. Remember. In the case of a ROM, a voltage value already stored is prepared, but the voltage value may be loaded from an external storage device or the like into a predetermined address of the RAM and used in step S1.

In step S2, the signal line 12 is connected via the A/D converter 23.
The voltage is read as a digital value, and the value is entered manually in step S3.

Next, in steps S4 to S6, the voltage value manually input in step S3 is compared with the three voltage values stored in step S1 to determine the connected device. Step S4~
If the device could not be identified in S6, proceed to step S.
7, it is determined that an unrecognized device is connected to the connector 90.

By performing the above-described determination routine at a predetermined timing, for example, at the time of system reset, the CPU 24 of device A
It is possible to quickly recognize what kind of device is connected to 13.

According to the above method, since a signal line for recognizing connected devices is not required, there is an advantage that the number of connected devices is not limited as in the conventional method. Further, there is an advantage that the connected device can be identified at high speed by reading the voltage of the signal line without performing data access to the connected device, and there is no limitation on the input/output interface procedure of the connected device.

The above description assumes that only either device B or C is connected, but signal line 1 of device A% BIC
Needless to say, even when devices 1 to 13 are connected in parallel, devices can be identified using the same procedure. In that case, the value of the terminating resistor to be inserted between the signal lines of each device is set separately according to the expected connection mode, and the voltage of the signal line 12 corresponding to the combination is set in advance. By memorizing the information, the connected device can be identified.

For example, in FIG. 1, the value of the resistance between the signal lines 11.12 of one connected device A, B, C... is R11, R12, R13...Rin, and the signal line 12.1 is
R21, R22, R23...R2n
, when the power supply voltage is V, the voltage Vx of the signal line 12 detected via the A/D converter 23 is shown as Can recognize connected devices.

Note that although the number of signal lines of the signal bus is limited to three in the above description, it goes without saying that the above technique is not limited to the number of signal lines. Also, it goes without saying that there is no need to connect a resistor to the pure gold signal on the signal bus.

[Effects of the Invention] As is clear from the above, according to the present invention, in an electronic device configured by connecting a plurality of different devices in parallel via a common signal bus consisting of a plurality of signal lines, the signal bus is configured. electrical resistances having different resistance values in each of the plurality of devices are connected between the plurality of signal lines, and the voltage of a predetermined signal line among the plurality of signal lines is detected in a predetermined device among the plurality of devices. By doing so, the device connected to the predetermined device via the signal bus is recognized. Therefore, the device connected to the predetermined device via the signal bus can be recognized by a simple measurement process of detecting the voltage of the signal line that constitutes the signal bus. This has the excellent effect of being able to recognize connected devices easily and inexpensively without increasing the number of signal buses and without impairing the expandability of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an electronic device adopting the present invention, FIG. 2 is a block diagram showing the configuration of equipment connectable to the device in FIG. 1, and FIG. 3 is a CPU shown in FIG. 1. FIG. 2 is a flowchart showing a control procedure. A to C... Devices 11 to 13... Signal lines 21.22.31.32.41.42... Resistance 23.
・・A/D converter 24...CPU2 4 r・
-ROM

Claims (1)

[Claims] 1) In an electronic device configured by connecting a plurality of different devices in parallel via a common signal bus consisting of a plurality of signal lines, there is resistance between the plurality of signal lines constituting the signal bus, which differs within each of the plurality of devices. A voltage of a predetermined signal line among the plurality of signal lines is detected in a predetermined device among the plurality of devices, thereby connecting the predetermined device to the predetermined device via the signal bus. An electronic device characterized by recognizing a device that is connected to the device.