JPH02305437A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive a shortening of processes and the improvement of a drive power of a MOS transistor by a method wherein a well formation process is performed in a self- alignment manner in one time of a photoengraving process and the concentration of an impurity in the vicinity of the surface, in which the channel part of the MOS transistor is positioned, of a substrate is made weak. CONSTITUTION:A resist patterning process for implanting an impurity in wells is performed one time only and a first conductivity type impurity P<+> is implanted in a high concentration and lowering its concentration in the vicinity of the surface of a substrate 1. Moreover, after a resist 4 is removed, an impurity B<+> to give a second conductivity type is implanted in the whole surface of the substrate 1 in a concentration lower than that of the P<+> and lowering its concentration in the vicinity of the surface of the substrate 1. Thereby, a photoengraving process has only to be performed one time only to a conventional method, in which two times of photoengraving processes were necessary, the wells 5 and 7 can be formed in a self-alignment manner and the processes are shortened. Moreover, the impurity in the wells at a place, where a channel part of a MOS transistor is positioned in the vicinity of the surface of the substrate, is little and an enhancement in the efficiency of the transistor, such as the improvement of the drive power of the transistor and the like, is contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a retrograde well in a self-aligned manner.

[Conventional technology]

In a semiconductor device integrated with MO3 type transistors, N
A CMO3 type semiconductor device constructed by combining both MO3 type or PMO3 type O3 transistors is widely sought after due to its advantages such as low power consumption, rather than a circuit consisting only of MO3 type or PMO3 type O3 transistors. In the CMO3 structure, since it is necessary to manufacture transistors of opposite channel conductivity types on the same substrate, it is necessary to form a well of a conductivity type opposite to the channel conductivity type for each transistor. Here, the CMO
In the type 3 configuration, a parasitic bipolar transistor is inevitably created, and due to factors such as noise on the power supply line, a large current flows that can destroy the device, resulting in so-called latch-up. For this purpose, a retrograde well having an impurity profile with a high concentration region at the bottom is used because it has the advantage of increasing latch-up resistance.

FIG. 5 shows a process of forming retrograde wells of two conductivity types in a semiconductor device by high-energy implantation according to a conventional method in order to obtain a CMO3 structure.

First, as shown in the cross-sectional view of FIG.
A field oxide film 2 is formed by the n of 5 ilicon method.

Subsequently, as shown in FIG. 5(b), a resist 4 is patterned on the p-well side to form a retrograde n-well 5, and an impurity such as phosphorus (P) that provides n-type conductivity is added at a concentration of 600%.
High energy such as keV, 5×10'! ~5×IO+3
Ion implantation is performed with an implantation amount of about C11-2.

Next, remove the patterned resist 4 as shown in FIG. 6(b), pattern the resist 6 on the n-well side to create a retrograde n-well 7, and apply an impurity such as boron (B') that provides p-type at a voltage of 200 keV, etc. High energy, 5X
Ions are implanted at an implantation dose of about 10th to 5×10 "ctm-", and then the resist 6 is removed.

[Problem to be solved by the invention]

In the conventional CMO3 manufacturing flow for retrograde wells using high-energy implantation, the photolithography process must be performed twice to form the wells, which lengthens the process and causes problems such as mask misalignment. Furthermore, since high-energy implantation is used, it is necessary to pattern a resist as thick as 3 μm, which makes dimensional control difficult and fine patterning difficult.

This invention was made in order to solve the above-mentioned problems, and it shortens the well process by forming wells in a self-aligned manner, and also provides a CMOS transistor having high performance MO3 type transistors.
An object of the present invention is to obtain a method capable of manufacturing a semiconductor device having an MO3 configuration.

[Means to solve the problem]

In the method for manufacturing a semiconductor device according to the present invention, in which two types of retrograde wells are formed, a resist patterning step for implanting well impurities is performed only once, and the first conductivity type impurity is increased to a high concentration. , and the impurity is implanted at a lower concentration near the substrate surface, and after the resist is removed, an impurity imparting the second conductivity type is implanted over the entire surface of the substrate at a lower concentration than above and at a lower concentration near the substrate surface. This is what I did.

[Effect]

In the well forming method of the present invention, the photolithography process is required only once, compared to the conventional method that requires two steps, and the well can be formed in a self-aligned manner, shortening the process. There is less well impurity at the location where the channel portion of the transistor is located, and high performance such as increased driving ability of the MO3 type transistor can be achieved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a method of forming a retrograde well of two conductivity types according to one embodiment of the present invention, and this method will be described below.

First, as shown in FIG. 1(a), a p-type silicon substrate 1
The normal LOCO3 method (Local
Oxidation of silicon (a method in which a nitride film is patterned on an underlying oxide film and the substrate is oxidized using this as a mask) is used to form a field oxide film 2 and define an active region 3 where elements such as transistors will be formed in a later process. do. Here, on the active region 3 there is a thickness of 30
Approximately 0% of the underlying oxide film remains.

Next, as shown in Figure Φ), retrograde n-well 5
The resist 4 is patterned to form.

Thereafter, phosphorus (P9) is implanted multiple times at a high energy of about 600 keV, varying the energy and the implantation amount, to form the retrograde n-well 5. At this time, in order not to increase the well impurity concentration in the shallow region of about 1000 m from the surface, low-energy implantation is not performed, and the implantation is performed throughout the entire region, and the implantation amount is the amount of boron (B'') shown below.

Specifically, 5 X 10" to 5 X 10" cm-
The amount of injection should be twice that of ``.

Next, as shown in FIG. 2C, after removing the resist 4 shown in FIG. The energy and implantation amount are varied and implanted multiple times, but as mentioned above, low energy implantation is not performed to avoid increasing the well impurity concentration near the surface. The implantation amount may be half of the implantation amount, that is, approximately 5.times.10'z to 5.times.10@13 C11-2 as in the conventional method, and the same impurity concentration profile as in the conventional method can be obtained except for the vicinity of the surface.

As a result, the n-well formed in Figure 1(b) was implanted more densely than in the conventional method, but due to the implantation of impurities giving the opposite conductivity type in Figure 1(C), the impurity concentration was the same as in the conventional method. , retrograde wells of two required conductivity types can be formed.

The solid line in FIG. 2(a) shows the impurity concentration profile under the active region 3 of the retrograde n-well 5, which was made with a higher concentration than the conventional method after the process shown in FIGS. is dropping. The dotted line in FIG. 2(a) shows a well impurity concentration profile in which the well concentration increases to the substrate surface in the conventional method.

Further, FIG. 2(b) shows the impurity concentration profile of the retrogradle well 7 with the conventional concentration after the process shown in FIG. 1(C) is completed, and the impurity concentration is reduced near the surface.

Further, FIG. 2(C) shows the impurity concentration profile of the retrograde n-well 5 after the process of FIG. 1(C) is completed,
It can be seen that the density shown by the solid line in FIG. 2(a), which is the profile before the same process, is canceled out and the density becomes appropriate.

After the above steps are completed, the impurity that gives n-type and p
The total amount of impurities that give a type is small, and even if the well concentration is adjusted to an appropriate level using impurities that give opposite conductivity types, the performance of the MO3 transistor will not deteriorate.

FIG. 3 shows a method for forming retrograde wells of two conductivity types according to a second embodiment of the present invention.
The method of the embodiment will be explained.

In FIG. 3(a), a field oxide film 32 is formed on the p-type silicon base +N31 by the usual LOCO3 method for element isolation, and an active region 33 in which elements such as transistors will be formed in a later process is defined. . Here active area 3
3, a variable underlay oxide film 32 with a thickness of about 300 layers remains.

Next, the resist 34 is patterned to form a retrograde n-well.

Then, using the resist 34 as a mask, phosphorus (P) is implanted into the retrograde n-well (38 in FIG. 3(d)).
form.

Next, as shown in FIG. 3(C), after removing the resist 34 shown in FIG. 3(b), boron (B4) is implanted into the entire surface of the substrate, and 39
) to form.

Here, the retrograde n-well and retrograde dollar well are formed by the following method.

To form such a well, as shown in FIG. The impurity layer 34 is formed by high-energy implantation exceeding 200 keV.The amount of implantation at this time is such that an inversion layer is formed under the field oxide film 32 by the voltage applied to the wiring material deposited on the field oxide film 32. The implantation amount may be such that the potential is not so high as to be an appropriate potential, that is, the implantation amount is such that the concentration directly under the field oxide film 32 is I x 10 "cea-".

This allows the junction capacitance to be lowered.

Next, in order to form a high concentration region 37 at the bottom, which is unique to retrograde wells, P ion implantation is performed at a high energy such as 3 MeV, or Bo ion implantation is performed at a high energy of 2 MeV.
A high concentration region 37 is formed by applying high energy such as V to a depth of about 2 to 4 μm.

Next, as shown in FIG. 3(C), the impurity implantation layer 34
The impurity concentration in the shallower region 36 is increased. P゛'s 600
Low energy below keV or 200ke of Bo
In addition to performing one or more implantations with low energy below V, the impurity implantation layer 34 and the high concentration region 37 are
The density of the intermediate region 35 between the two areas is increased. P9's 600k
energy of eV or more and 3 MeV or less, or Bo
1 with an energy of 200 ke or more and 2 MeV or less
Perform ion implantation once or multiple times.

Subsequently, in the process shown in FIG. 10(d), an annealing treatment is performed to activate the injection layer that was performed in FIG.

4(a) shows the impurity concentration profile under the field oxide film 32 of the silicon substrate 31 processed according to FIG. 3, and FIG. 4(Cb) shows the impurity concentration profile under the active region 33. By using the formation method, a deeper well is formed than in FIG. 2.

Then, by forming the retrograde n-well as described above at twice the concentration shown in Figure 2, and then forming the retrograde well at the concentration shown in Figure 2, the result as shown in Figure 3 (C) is formed. The p-well 39 formed in the process naturally has the impurity concentration shown in FIG. 2, and the n-well 38 formed in the steps shown in FIGS. 3(b) and 3(C) also has the impurity concentration shown in FIG. Retrograde wells of two conductivity types can be formed.

Although a p-type substrate was used in the above embodiment, an n-type substrate may also be used.Also, although the n-well was formed first, the p-well may be formed first to be denser than before.

〔Effect of the invention〕

As described above, according to the present invention, the well formation process is performed in a self-aligned manner in one photolithography process, so the process can be shortened, and the well formation process can be performed in a self-aligned manner in one photolithography process. Since the concentration is reduced, deterioration in transistor performance due to well impurities can be suppressed, and the driving ability of MO3 type transistors can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a manufacturing method according to a first embodiment of the present invention. FIG. 2 is a diagram showing the impurity profile of a well when the method of FIG. 1 is followed. FIG. 3 is a diagram showing a manufacturing method according to a second embodiment of the present invention. FIG. 4 is a diagram showing the impurity profile of a well when the method of FIG. 3 is followed. FIG. 5 is a diagram showing a conventional manufacturing method. 1.31 is a silicon substrate, 2.32 is a field oxide film, 3.33 is an active region, 4.34 is a resist, 5.38
is retrograde n-well, 6°34 is resist, 7.
39 is a retrogradle well, 34.34a is an injection layer, 35 is an intermediate region, 36 is a shallow region, and 37 is a high concentration region. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a method for manufacturing a semiconductor device having a CMOS structure, the step of forming a first conductivity type well and a second conductivity type well following a field oxidation step of a semiconductor substrate includes a step for forming a first conductivity type well. a step of patterning the resist, a step of forming the impurity of the first conductivity type well at a high concentration by one or more ion implantations, a step of removing the resist, and a step of forming the impurity of the second conductivity type well by the 1. A method for manufacturing a semiconductor device, comprising the step of forming the impurity at a concentration lower than that of a single conductivity type well by one or more ion implantations.