JPH0230558B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses a time-division multiplex transmission system, in particular, connects a plurality of terminals to a central control and monitoring device via a pair of signal lines, and cyclically calls each terminal. The observed values of analog quantities observed by transducers connected to the terminals are converted into digital quantities and transmitted to the central control and monitoring device, and the observed values obtained from each terminal are displayed in the central control and monitoring device. Related to time division multiplex transmission system.

Generally, in this type of time division multiplex transmission system, a general-purpose A/D converter is used to convert observed values of analog quantities into digital quantities.
Almost the same maximum allowable input value of the A/D converter is used. Now, for example, if the maximum allowable input value of the A/D converter is 2V, then 1999
shall be output. In other words, general-purpose A/D
A/2 with an output of 3 1/2 found in the converter
The D converter converts the analog signal from the transducer into a digital signal. When doing this, with the conventional type, for example, 20 to 50A
To convert the current that varies between
It is necessary to use a transducer with Since the measurement results in fluctuations, measurement in this manner has the drawback of poor accuracy. Another problem is that in the conventional transducer 10, as shown in FIG.
The observed quantity becomes an analog signal and is input to the A/D converter 11, and becomes a multi-digit digital signal and is stored in the latch 21 for each digit. At this time, the output of the A/D converter 11 The number of bits is equal to the number of input bits of latch 21,
In order to indicate which digit the signal output from the A/D converter 11 is, a digit data signal D 1 is output from the data output terminals P ₁ , P ₂ , P ₃ , and P ₄ of the A/D converter 11 _. , D ₂ , D ₃ , D ₄ are output, and the latch 2 is activated by these digit data signals D ₁ , D ₂ , D ₃ , D ₄ .
1 is opened and closed. However, the observed value stored in the latch 21 as a digital quantity is inputted from the data input terminal D _I of the tri-state buffer 22, and the control signal Sc from the central control and monitoring device 1 is input.
The control terminals C ₁ , C ₂ , and the control terminals of the terminal circuit 4 are formed by
Digit selection signals N ₁ , N ₂ , N ₃ , output from C ₃ , C ₄ ,
When N ₄ matches that digit, it is input from the latch 21 to the monitoring input terminal Ts of the terminal circuit 4 through the tristate buffer 22 and is transmitted from the terminal 3 to the central control and monitoring device 1 via the signal line 2. It is. Selecting the digit of a digital quantity with such a configuration has the disadvantage that the circuit becomes complicated and the number of components increases. Furthermore, it is necessary to perform sampling to convert an analog quantity into a digital quantity, but in the conventional case, as shown in FIG. and a termination signal generation terminal E which outputs a termination signal when the output of the A/D converter 11 outputs all the signals of each digit, and the sampling period of the A/D converter 11 is set independently of other signals. The observed quantity, which is a sampled analog quantity, is converted into a digital quantity, and the time period in which each digit of the digital quantity corresponding to the analog quantity is outputted once from the A/D converter 11 has become a period of repeated sampling. For example, it is assumed that the next sampling is performed at the point when one digit of the observed value, which has become a multi-digit digital quantity, is transmitted and the data is transmitted to the central control and monitoring device 1. As shown in the figure, the A/D converter 11, which was outputting 1082 at the time of the first sampling, outputs 946 at the time of the next sampling.
Assuming that the observed value changes to 946 after transmitting a signal for one digit of 1082, that is, 1, then the central control and monitoring device 1 will display 1946, and the conventional configuration described above would not be able to make an error. In some cases, the central control and monitoring device 1 malfunctioned due to the transmission of information.

As mentioned above, the conventional time division multiplex transmission system has various drawbacks, and the present invention was made to solve these problems. Using a transducer that outputs an analog quantity approximately equal to the maximum allowable input value of the A/D converter in response to the maximum value of and transmit it,
Another objective is to simplify the circuit configuration and reduce the number of components, and another objective is to synchronize the A/D converter with the central control and monitoring device to provide reliable information. It is about transmission.

Hereinafter, specific embodiments of the present invention will be described in detail based on the drawings. As shown in FIG.
A plurality of terminal devices 3 are connected through the terminal device 3, and the central control and monitoring device 1 outputs a transmission signal S _T as shown in FIG. 4a to each terminal device 3. Cyclically called. That is, the transmission signal S _T is composed of a start signal Ss, an address signal S _A , a control signal Sc, and a return waiting signal _SW arranged in chronological order, and each terminal device 3 is ready to receive the start signal Ss. The address signal S _A is a signal for cyclically calling each terminal device 3, each having a unique address. Terminal 3 with matching address
outputs an address match signal from the address output terminal _TA and prepares to receive the next control signal Sc.
The control signal Sc selects the monitoring input to be transmitted to the central control and monitoring device 1 from among the monitoring inputs input to the terminal circuit 4 of each terminal device 3 from the monitoring input terminal _Ts , and is used to select the monitoring input to be transmitted to the central control and monitoring device 1. The monitoring input applied to the monitoring input terminal Ts designated by the control signal Sc within the interval is outputted from the return output terminal _TR as a return signal S _R as shown in FIG. 4b,
It is transmitted to the central control and monitoring device 1. Here, the terminal circuit 4 of the terminal device 3 is configured as shown in FIG. 5, and has a signal input terminal T _I connected to the transmission line 2, and an address signal S _A. A signal processing logic unit 5 selects the control signal Sc from the transmission signal _ST , and separates the address signal S _A selected by the signal processing logic unit 5 from the control signal Sc and outputs the control signal to the control terminals C ₁ , C ₂ , C ₃ , digit selection signal N ₁ from C ₄ ,
The control signal discriminator 6 that outputs N ₂ , N ₃ , N ₄ , the address of the terminal 3 input in advance to the address setting terminal T _B and the address signal S _A output from the control signal discriminator 6 It has an address discrimination section 8 which outputs an address match signal when a match occurs, and a monitoring input terminal Ts, and returns the parallel monitoring input to the central control monitoring device 1 within the return waiting signal S _W section as a serial return signal S _R. and a monitoring input return unit 9. In this embodiment, the monitoring input is 4 bits, 4 bits 1 like a BCD code signal.
digit signal is applied to the monitoring input terminal Ts. In the present invention, since the purpose is to transmit the analog quantity observed by the terminal device 3 to the central control and monitoring device 1, the monitoring input terminal T _S of the terminal circuit 4 receives the output from the transducer 10. An observed quantity consisting of an analog quantity is converted into a digital quantity by an A/D converter 11 and is applied. Here, assuming that the maximum allowable input value of the A/D converter 11 is 2V and that it outputs 1999 at that time, the maximum value of the output of the transducer 10 will be a value lower than 2V but close to 2V. Adjust accordingly. That is, it is assumed that the observed quantity of interest is current, which changes in the range of 20 to 50 A, and that the transducer 10 outputs 2 V when the input is 60 A. In this way, when the observed value is 60A, the A/D
The output of the converter 11 is 1999, so there is no overrange in the target range, and the input voltage of the A/D converter 11 is 0.1V.
The observation amount corresponding to 3A is 3A, and the density of the amount of information transmitted to the central control and monitoring device 1 becomes high. On the other hand, in the central control monitoring device 1, it is difficult to understand if _60A is displayed as 1999, so as shown in FIG. A constant multiplier circuit 13 having a multiplication factor is provided to output the return signal S _R
I am trying to display it after multiplying the digital amount by several times. For example, for 60A as in the example above
If it is displayed as 1999, by tripling the digital amount of the observed value included in the return signal S _R ,
All you have to do is display 6000. (In this case, the position of the decimal point can be chosen arbitrarily.)
In this embodiment, the transducer 10 of each terminal 3
A constant multiplier circuit group 14 is constructed by setting a plurality of rows of constant multiplier circuits 13 each having a different magnification in accordance with the input of the constant multiplier circuit 13 in the constant multiplier circuit group 14
To determine whether to multiply the return signal S _R by a constant value, the constant multiplier circuit 13 reads out the data in the memory 15 which is set to select the multiplying factor according to the address signal S _A.
It is becoming more and more of a choice. In other words, when a terminal device 3 having a transducer 10 that requires double magnification is called up using an address signal S _A , the terminal device 3 corresponding to that address is connected at the same time as the address signal S _A is generated. The memory 15 selects the necessary magnification for the transducer 10, and operates the constant multiplier circuit 13 having a 2x magnification, and operates the 4x constant multiplier circuit 13 if the magnification is 4x. Return signal S _R processed in this way
is decoded by the display processing section 16 and displayed on the display section 17, which is composed of LEDs, liquid crystal display elements, and the like. Reference numeral 18 in the figure is a memory input key, which is used to input and store a magnification corresponding to the transducer 10 of the terminal device 3 in the memory 15.

The display on the central control and monitoring device 1 is performed as described above, but on the other hand, the A/
In order to apply the output of the D converter 11 to the monitoring input terminal Ts of the terminal circuit 4, an interface as shown in FIG. 7 is used. For example, if the output of the A/D converter 11 is 4 bits representing one digit, such as a BCD code, and the output terminal Q of the A/D converter 11 is 4 bits, then
In order to output a digital quantity of digits, it is necessary to output the digital quantity one digit at a time, and to indicate which digit is being output, the number of bits equal to the total number of digits, In other words, when outputting 4 digits, 4-bit digit data output terminals P ₁ , P ₂ , P ₃ ,
Digit data signals D ₁ , D ₂ , as shown in FIG. 8 from P ₄
D ₃ and D ₄ are output cyclically so that the digits advance sequentially to indicate the digit, and on the other hand, when the terminal circuit 4 receives the control signal Sc indicating the digit requested by the central control and monitoring device 1. A digit selection signal as shown in FIGS. 8 and 9 is output from the control terminals C ₁ , C ₂ , C ₃ , C ₄ having the same number of bits as the digit data output terminals P ₁ , P ₂ , P ₃ , P ₄ . N ₁ , N ₂ , N ₃ , N ₄ are shown. These digit selection signals N ₁ , N ₂ ,
N ₃ , N ₄ continue to output digit selection signals N ₁ , N ₂ , N ₃ , N ₄ for selecting one digit until receiving the next control signal Sc, and digit data signals D ₁ , D ₂ , Like D ₃ and D ₄ , the digits are output cyclically in order. Signals obtained from terminals of the same digits, digit data output terminals P ₁ , P ₂ , P ₃ , P ₄ and control terminals C ₁ , C ₂ , C ₃ , C ₄ , which output such signals. The AND circuit 19 is used to obtain the logical product of . That is, the first digit terminals of digit data output terminals P ₁ , P ₂ , P ₃ , P ₄ and the first digit terminals of control terminals C ₁ , C ₂ , C ₃ , C ₄ are
At this time, the clock signal Cp input to the clock terminal Ck of the latch 21 as shown in FIG. 8 appears at the output of the AND circuit 19.
When the digital quantity is four digits or multiple digits as in this embodiment, the logical sum of the outputs of each AND circuit 19 is obtained by the OR circuit 20, and the output of the OR circuit 20 is connected to the clock of the latch 21. The signal Cp may be used. The clock signal Cp obtained in this way is applied to the clock terminal Ck of the latch 21.
The latch 21 opens only when the digit data signals D ₁ , D ₂ , D ₃ , D ₄ and the digit selection signals N ₁ , N ₂ , N ₃ , N ₄ indicate the same digit. The output is sent back to the central control and monitoring device 1 via the terminal circuit 4. With the above configuration, there is no need to use as many latches 21 as there are digits as in the conventional case, and the interface between the A/D converter 11 and the terminal circuit 4 has a simple configuration, and the number of parts is small. It will become.

By the way _, to synchronize the A/D converter _{11 and the} central control/monitoring device 1, as shown in FIG. This is achieved by connecting C ₁ to the reset terminal R of the A/D converter 11. By connecting in this way, the sampling start signal Sp as shown in FIG. 9 is output to the reset terminal R. will be applied. That is,
The analog quantity that becomes the input to the A/D converter 11 is when the first digit signal of the digit selection signals N ₁ , N ₂ , N ₃ , N ₄ is output in response to the control signal Sc from the central control and monitoring device 1. Sampling is started at the same time, and after sampling ends, the digit selection signals N ₁ , N ₂ , N ₃ , and N ₄ that are cyclically output are held at the same value until the 1st digit selection signal N ₁ is output again. It continues to do so. After the analog quantity once sampled in this way is converted into a multi-digit digital quantity by the A/D converter 11, it continues to maintain the same value until the digital quantity of all digits is sent back to the central control and monitoring device 1. Therefore, the drawback of the conventional method is that sampling is performed many times until all the digits are returned, resulting in inaccurate observed values returned to the central control and monitoring device 1. It is. In the figure, S _L is a sampling signal.

As described above, in the present invention, a plurality of terminal devices are connected to a central control monitoring device via a pair of signal lines, and when the central control monitoring device calls each terminal device, the called terminal device The analog quantity observed by the transducer connected to the terminal is converted into a multi-digit digital quantity by the A/D converter, and the A/D converter sequentially outputs the digital quantity for each digit. A digit data signal is sent back from the terminal via the latch and outputs a digit data signal indicating the digit being output, and corresponds to a digit selection signal formed within the terminal in response to a control signal transmitted from the central control and monitoring device. In the time-division multiplex transmission method, in which the digital value of the digit is retrieved and transmitted to the central control and monitoring device, and the observed value transmitted from each terminal device is displayed on the central control and monitoring device, the first step is to The maximum value of the output of the connected transducer is set to be approximately equal to the maximum allowable input value of the A/D converter, and a constant is set to the central control and monitoring device at a multiplier according to the ratio of the input and output values of the transducer. Since a constant multiplier circuit is provided to correct the multiplied observed value and the displayed value to be equal, it is possible to increase the ratio of the output analog amount of the transducer to the allowable input value of the A/D converter. This has the advantage that it is possible to transmit accurate observed values, and the maximum observed value approximately corresponds to the maximum allowable input value of the A/D converter.
Even when multiple terminals measure different observable quantities and the ranges in which the values fluctuate are different, A/
There is an advantage that the relative errors caused by the D converter can be made approximately equal, and the reliability of the observed values displayed by the central control and monitoring device can be made approximately equal. In addition, in the above-mentioned time division multiple transmission system,
Second, the digit data signal output from the A/D converter and the digit selection signal formed in the terminal according to the control signal from the central control and monitoring device are used to perform the logical product of signals corresponding to the same digit. Since the clock signal is a latch, there is no need for a latch for each digit as in the conventional case, and only one latch is required for the entire circuit. This has the advantage that the number of interface parts can be reduced and the circuit configuration can be simplified. Furthermore, in the above time division multiplex transmission system, thirdly, by connecting the control terminal of the first digit among the control terminals of the terminal circuit and the reset terminal of the A/D converter, the selection output of the first digit can be made. Since sampling is started at the same time as the output, the sampling start time is controlled by the control signal from the central control and monitoring device, and the A/D converter and the central control and monitoring device are synchronized. As a result, there is no need to display the numerical value at the time of sampling two or more times as in the past, and display the numerical value at the time of sampling that differs for each digit.
This has the advantage that highly accurate observed values can be transmitted.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional terminal, Figure 2 is a block diagram showing a conventional terminal device.
3 is a schematic configuration diagram of the present invention; FIG. Figure 5 is a block diagram showing the same terminal circuit as above.
FIG. 6 is a block diagram showing the main parts of the central control and monitoring device same as above, FIG. 7 is a block diagram showing the terminal device same as above, FIG. 8 is an operation explanatory diagram showing a time chart of the terminal device interface, FIG. 9 is an operation explanatory diagram showing a time chart of a sampling start signal, in which 1 is a central control and monitoring device, 2 is a signal line, 3 is a terminal device, 4 is a terminal circuit, 10 is a transducer, and 11 is an A/D Converter, 13 is a constant multiplier circuit, 14 is a constant multiplier circuit group, 21 is a latch, D ₁ ,
D ₂ , D ₃ , D ₄ are digit data signals, Sc is a control signal,
_N1 , _N2 , _N3 , _N4 are digit selection signals, Cp is a clock signal, Sp is a sampling start signal, and R is a reset terminal.

Claims (1)

[Scope of Claims] 1. A plurality of terminals are connected to a central control and monitoring device via a pair of signal lines, and the central control and monitoring device cyclically calls each terminal, and the called terminals are called by a transducer. The observed analog quantity is converted into a digital quantity by an A/D converter, the output thereof is transmitted to a central control and monitoring device, and the observed value transmitted from each terminal device is displayed on the central control and monitoring device. The maximum value of the output of the transducer connected to the terminal device is set to be approximately equal to the maximum allowable input value of the A/D converter, and the constant multiplier circuit is composed of a plurality of constant multiplier circuits each having a different multiplier within the central control and monitoring device. Configure a doubler circuit group,
By selecting a constant multiplier circuit with a magnification corresponding to the transducer of each terminal from the constant circuit group, the observed value transmitted from each terminal is corrected so that the value corresponding to the observed value is displayed. A time division multiplex transmission system characterized by: 2 A plurality of terminal devices are connected to the central control monitoring device via a pair of signal lines, and the central control monitoring device cyclically calls each terminal device, and the called terminal device receives the analog quantity observed by the transducer. The A/D converter samples and converts it into a multi-digit digital quantity. When the sampling start signal is input to the reset terminal, the A/D converter holds the same value until the next input to the reset terminal, and converts each digit. Control is transmitted from the central control and monitoring device by sequentially outputting digital quantities for each output and sending the output back to the central control and monitoring device via the terminal circuit, and cyclically outputting a digit data signal indicating the digit being output. The digital quantity of the digit corresponding to the digit selection signal that is cyclically output from the terminal circuit of the terminal device according to the signal is read out and transmitted to the central control and monitoring device, and the central control and monitoring device monitors the observations transmitted from each terminal device. to display the value,
The logical product of the digit data signal output from the A/D converter and the signals corresponding to the same digit among the digit selection signals output from the terminal circuit and having a pulse width larger than the cyclic cycle of the digit data signal is used as the latch clock signal. A time division multiplex transmission system characterized by transmitting digital quantities read from latches to a central control and monitoring device. 3. The time division multiplex transmission system according to claim 2, wherein a digit selection signal corresponding to the first digit among the three digit selection signals is inputted to a reset terminal of an A/D converter.