JPH0230611B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation circuit used in a switching power supply of a quick charging circuit.

Conventional switching power supplies using the so-called PWM method fix the oscillation frequency and control the switching time width to control the output, and the circuit configuration is simple, but because it has a single oscillation frequency, , the reference oscillation frequency and its harmonic components are generated with sharp peak values, and in order to comply with the standard values for electric field strength, terminal noise, terminal power, etc. regulated in each country, it is necessary to insert a filter or This required changes to the printed circuit board design. Figure 3 shows terminal noise data for the band from 10KHz to 300KHz when the reference oscillation frequency of a switching power supply using the conventional PWM method is 30KHz.As shown in the figure, the reference frequency and its harmonic components are occurs with a sharp peak value.

The present invention was made to solve these problems of the conventional example, and uses a switching power supply or the like to alternately switch between two reference oscillation periods, thereby averaging the variance of the noise spectrum. Therefore, it is an object of the present invention to provide an oscillation circuit that can reduce the peak level of generated noise.

The configuration of the present invention will be described below with reference to illustrated embodiments. FIG. 1 shows a circuit diagram of an embodiment of the present invention. In the figure, DB is a commercial AC power supply Vs
This is a diode bridge that full-wave rectifies the alternating current voltage, and its rectified output is smoothed by capacitor _C1 and supplied to pulse transformer Tf.
In addition, Tr is a step-down transformer that steps down the AC voltage of the commercial AC power supply Vs, and its output is connected to the diode D ₁
It is half-wave rectified by C2 and smoothed by capacitor _C2 . A Zener diode Dz is connected across _R13 to both ends of the capacitor _C2 , and the regulated voltage Vcc generated across this Zener diode Dz
is supplied to each part as circuit power. The current flowing through the primary coil of the pulse transformer Tf is switched by turning on and off the transistor _Q3 . Diode D ₂ clamps the back electromotive force generated when transistor Q ₃ is turned off. The electromotive force generated in the secondary coil of the pulse transformer Tf is half-wave rectified by the diode _D3 , and charged to the capacitor _C4 via the choke coil Lc.
D ₄ is the flywheel diode. A secondary battery such as a NiCd battery is connected to both ends of capacitor _C4 .
BT is connected. However, the capacitor
The terminal voltage of C ₄ is divided by a voltage dividing circuit of resistors R ₁₁ and R ₁₂ and applied to the negative side comparison input of comparator CP ₂ . A reference voltage divided by a resistor _R9 and a resistor _R10 is applied to the positive comparison input of the comparator _CP2 . Therefore, when the terminal voltage of capacitor _C4 exceeds a predetermined reference level, the output of comparator _CP2 becomes L level, turning off transistor _Q3 . At the base of the transistor Q ₃ there is a resistor R ₈
The output of comparator CP ₁ is applied through. The positive comparison input of this comparator CP ₁ has a reference voltage Vr divided by resistors R ₃ and R ₄ .
is being applied. Resistor R ₅ is connected in parallel to resistor R ₄ via transistor Q _1. Therefore, when transistor Q 1 is on, the reference voltage Vr becomes a low voltage Vl, and conversely, when transistor Q ₁ is off, _the reference voltage Vr becomes a low voltage Vl. , reference voltage Vr
becomes a high voltage Vh. On the other hand, comparator CP ₁
The terminal voltage of capacitor _C3 is applied to the negative side comparison input of. This capacitor _C3 is adapted to be charged via a resistor _R2 . The capacitor _C3 is connected to the output of the T-type flip-flop FF via the resistor _R1 . Therefore, when the output of the flip-flop FF is at H level, the capacitor _C3 is rapidly charged; When the output is at L level, capacitor _C3 is charged slowly.
Further, the charge in the capacitor _C3 is discharged through the resistor _R14 when the transistor _Q4 is turned on. this transistor
_Q4 and the aforementioned transistor _Q1 are turned on by the bias current flowing through the resistor _R6 , but when the output of the comparator _CP1 becomes H level, the transistor _Q2 is turned on through the resistor _R7 . Since it is turned on and bypasses the bias current, transistors Q ₄ and Q ₁ are turned off.

2A to 2E show the voltages at points A to E of the circuit shown in FIG. 1, respectively. First, when the output of flip-flop FF is at H level, capacitor _C3 is charged relatively quickly as shown in Figure 2A.
Reference voltage determined by the voltage division ratio of resistor R ₃ and resistor R ₄
Reach Vh. As a result, the output of the comparator CP ₁ becomes L level as shown in FIG. 2B, and the transistor Q ₂ is turned off.
Q ₁ and Q ₄ are turned on, and the output of flip-flop FF becomes L level as shown in FIG. 2C. At this time, a reference voltage determined by the voltage division ratio of resistors R ₃ , R ₄ and R ₅ is applied to the positive side comparison input of comparator CP ₁ . Also, the charge in the capacitor _C3 is rapidly discharged through the resistor _R14 . When the terminal voltage of the capacitor _C3 drops to the reference voltage Vl, the output of the comparator _CP1 becomes H level again, the transistor _Q2 is turned on, and the transistors _Q1 and _Q4 are turned off.
Therefore, the reference voltage Vr of the comparator CP ₁ returns to the high voltage Vh again, and the capacitor C ₃ is connected to the resistor R ₂
is charged via. In this case, the output of flip-flop FF is at L level, so
The terminal voltage of capacitor _C3 rises relatively slowly. Therefore flip-flop FF
When the output of flip-flop FF is at H level, the oscillation period _T1 becomes short, and conversely, when the output of flip-flop FF is at L level, the oscillation period _T2 becomes long. Note that when the output of comparator CP ₁ is at H level, transistor Q ₃ is turned on and the terminal voltage of capacitor C ₄ increases;
When this terminal voltage exceeds the predetermined reference level Vth as shown in Figure 2E, the output of the comparator _CP2 becomes L level as described above, so the base potential of the transistor _Q3 becomes as shown in Figure 2D. The transistor Q ₃ is forcibly clamped to the L level as shown in FIG.
is to be turned off.

As described above, in the embodiment shown in FIG. 1, the output of the flip-flop FF is alternately inverted to H level and L level, so that the oscillation periods _T1 and _T2 are alternately inverted. Yes, but
If the flip-flop FF were removed and one end of the resistor _R1 was grounded, the oscillation period would be fixed at _T2 . Figure 3 shows the frequency components of the noise voltage in this case, and the oscillation frequency is 30KHz.
The reference frequency and its lower harmonic components exceed the level of the noise prevention standard St. On the other hand, Figure 4 shows the frequency components of the noise voltage when the oscillation period is alternately switched between T1 _{and T2 and} the oscillation frequency is alternately switched between 30KHz and 50KHz. The noise voltage for all frequencies is below the level of noise prevention standard St. As is clear from a comparison between FIG. 3 and FIG. 4, according to the present invention, low-order harmonic components up to several times the oscillation frequency can be significantly reduced.

The present invention is constructed as described above, and includes a flip-flop whose output is alternately inverted according to the pulses output from the pulse oscillation circuit, and the output of this flip-flop is connected to the oscillation cycle switching input of the pulse oscillation circuit. Because of this, the two oscillation periods can be alternately switched and used, and the spectrum of noise caused by harmonics, etc., is distributed and averaged, and the peak level of noise can be reduced as a whole. It is something that you have.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2A
-E are explanatory diagrams of the same operation as above, FIG. 3 is a noise characteristic diagram of the conventional example, and FIG. 4 is a noise characteristic diagram of the present invention. CP ₁ is a comparator, R ₁ and R ₂ are resistors, C ₃ is a capacitor, and FF is a flip-flop.

Claims (1)

[Scope of Claims] 1. A flip-flop whose output is alternately inverted by pulses output from a pulse oscillation circuit is provided, and the output of this flip-flop is connected to an oscillation cycle switching input of the pulse oscillation circuit. Oscillation circuit. 2. The oscillation according to claim 1, wherein the oscillation cycle of the pulse oscillation circuit is set by a CR time constant circuit, and the time constant of the CR time constant circuit is switched by the output of a flip-flop. circuit.