JPH02306341A - Microprocessor - Google Patents

Abstract

PURPOSE:To prevent the disturbance of a pipe line processing as much as pos sible by masking the execution preparation completion state of an instruction decoded by means of a decoder during a period until a branching condition designated with a condition branching instruction is defined. CONSTITUTION:The queue ready mask control circuit 410 of an instruction decoding unit 40 masks queue ready signal IDQRD 0-2 for the instruction decod ed in the decoder 400 after the condition branching instruction by a mask signal INV0-2, and it releases the mask signal INV0-2 by a BREN signal from a branching definition signal output circuit 408. Thus, the flow of the pipe line processing is not stopped or the stop can be controlled to a minimum even if the condition branching instruction is decoded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pipeline processing microprocessor, and more particularly to an improvement of an instruction decode unit of a pipeline microprocessor.

[Conventional technology]

In a pipeline microprocessor, there is an instruction prefetch unit (PDU) that prefetches instructions, an instruction decode information unit (IDU) that decodes the prefetched instructions, and the effective address of the operand address based on the operand access information from the same unit. Each unit, such as the memory management unit (MMU) that performs calculations and the instruction execution unit (EXU) that executes instructions based on decode information from the IDU, executes each required process according to a predetermined pipeline processing flow. It's 1~. Therefore, the IDU typically decodes 12 an instruction that is several steps after the instruction that the EXU is currently executing.

[Problem to be solved by the invention]

Incidentally, a conditional branch instruction is often used in a series of instructions to be executed. A conditional branch instruction controls the flow of instructions to be processed depending on whether the branch condition specified by the instruction is satisfied based on the program status flag, which is controlled by the result and state of the instruction executed by the EXU. It is something. When such a conditional branch instruction is transferred to the IDU, the IDU decodes the instruction, but the EXU decodes the instruction currently being executed and/or the actual execution between the currently executing instruction and the conditional branch instruction. If the decoded instruction in is an instruction that changes the contents of the program status flag, it cannot be determined whether or not to branch until the EXU executes such an instruction.

Therefore, when the IDU decodes the conditional branch instruction,
It is common practice to stop decoding subsequent instructions until the branch condition specified by the instruction is determined. Only 1. Therefore, this means stopping the flow of pipeline processing, leading to a speed bottleneck in the microprocessor. As described above, conditional branch instructions can be cited as a major cause of disrupting the microprocessor's b/f line processing.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a microprocessor in which disturbances in pipeline processing caused by conditional branch instructions are reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microprocessor including an instruction teconic unit that prevents disturbances in pipeline processing as much as possible even when a conditional branch instruction is decoded.

[Failure to solve the problem]

The microprocessor according to the present invention includes a decoder that parses an instruction, a queue register that temporarily stores decode information from this decoder, and when the decode information stored in this register becomes ready for execution, decode information is sent from the register. an execution unit that receives and executes the read decoding information; and a means for reading out the decoded information, and in response to information indicating that the decoder has decoded the conditional branch instruction, the branch condition specified by the conditional branch instruction is determined. means for masking the ready-for-execution state of the instruction decoded by the decoder during a period until the branch condition is established; means for canceling the mask or changing the execution ready state to an execution disabled state, when the execution ready state is changed to an execution disabled state,
It is characterized in that the decode information of other instructions is stored in the queue register in which the decode information of the changed instruction is stored.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of a Vibrine microprocessor showing one embodiment of the present invention. A bus interface unit (BIU) 20 reads/writes data between memories (not shown) and peripheral devices (10) via a system bus 21. Briefetch/Briedecode Unison h (PDU) 301-1: communicates with the BIU 20 via the bus 21 and executes prefetching of instructions. PDU
30 holds the pre-fetched instruction stream and transfers the instruction stream to an instruction code unit (IDU) 4.
Buri-decoded so that it is easy to decode with 0, that is,
Opcode, addressing mode information.

The data is divided into data, etc., and transferred to the IDU 40 via the bus 31. The IDU 303 decodes the transferred code and transfers address information necessary for calculating the effective address of the operand to the memory management unit (MMU) 50 via the bus 42, while the instruction execution unit (MMU) 50 decodes the transferred address information. (EX
U) Information for instruction processing (position of operand data, type of arithmetic and logic operation processing, etc.) is transferred to the bus 41.

The MMU 50 calculates the effective address of the operand data based on the address information from the IDU 40, converts it into a real address, and issues an operand access request to the BIU 20 via the bus 51. Branch destination address information is bus 5
2 to the PDU 30. The MMU 50 uses the TLENDI signal to indicate that the address translation has been completed.
Notify DU40. The EXU 60 communicates with the BIU 20 via the bus 61 based on the decode information from the IDU 40, and starts executing instructions when the operands are ready.

The IDU 40 has a plurality of queue registers (Fig. 2) that temporarily store instruction decode information, and when unexecuted decode instructions are stored in all registers, the IDQFUL
An L signal is supplied to the PDU 30 to temporarily prohibit command transfer from the PDU 30. When all queue registers become empty, an IDQEMP signal is issued to temporarily prohibit the EXU 60 from receiving instructions. EXU60 is I
When the command food from DU40 is received, ■DQACK signal is generated. The EXU 506 also has a program status flag (not shown) that is controlled by the result or state of an executed instruction, and is specified by a conditional branch instruction and refers to the branch condition flag to determine whether the condition has been met. A TAKEN signal indicating this is supplied to the IDU 40. Based on this TAKEN signal, the IDU 40 generates a VCAN signal when the branch condition specified by the conditional branch instruction is satisfied, and generates a UCAN signal when it is not satisfied.

These signals are PDU30. Mnet tυ；1丑-BIU2
0 to notify whether the branch condition is met or not.

These BIU20. PDU30. IDU40. MMrJ
5Q and EXtJ60 are operating on the vibe line and are executing assigned processes in parallel to each other.

Referring to FIG. 2, IDU 40 according to the present invention is shown in more detail. Instructions from PDU 30 via bus 31 are decoded by decoder 400 according to a decoding sequence controlled by sequencer 401. Among the decoded information, operand address information is transferred to bus 42.
The instruction processing information is supplied to the MMU 50 via the bus 4.
13 through three queues 17 registers (IDQO, ID
Ql, 1DQ2) 402-404.

Each IDQ40:2-404 has a corresponding strobe signal QSLSTBO-2 to its write enable terminal WE.
The information stored on the bus 413 is temporarily stored by supplying the bus 413, and the information stored on the bus 413 to the EXU 60 is read by supplying the corresponding strobe signal EXQSLO-2 to the read enable terminal RE. These QSTs,
5TEO-2 and EXQS LO-2 are output from the queue register read/write control circuit 405. The circuit 405 responds to the IDQSTB signal generated every time the decoding of one instruction from the sequencer 401 is completed.
QSLSTBO-2 is generated in sequence, and the decoder 413
IDQ (0-2)402-40
4 to 4 in order. Each queue ready signal IDQRDYO from the queue ready control circuit 407
-2 and the IDQACK signal from EXU60
Q, 5LO-2 occur in order 1~IDQ (0-2)
The store information is sequentially transferred onto the bus 41 from 402-404.

The control circuit 407 responds to the signal TLENDI indicating that the address translation of the operand required by the decode instruction stored in IDQO-2 is completed, and converts the corresponding IDQRDY.
Generates O-2 signal. IDQRDYO-2 is the clear signal VQCL from the gyu-ready clear control circuit 411.
Each is cleared by RO-2. This IDU40
is a branch queue register pointer that stores the location of a register (IDQ) that stores decode information of a conditional branch instruction in response to a signal CBRA generated by the decoder 400 when the decoder 400 decodes the instruction. 406 and the FLAGM signal indicating that the instruction decoded from the decoder 400 is an instruction that can change the contents of the program status flag in the EXU 60, the branch condition specified by the conditional branch instruction is determined. The branch undetermined period detection circuit 409 notifies the TAK from the EXU 60 when the F HZ R signal becomes inactive.
A branch confirmation signal output circuit 4 that outputs a branch establishment signal vCAN and a branch failure signal UCAN determined based on the EN signal.
08. Unless a conditional branch instruction is decoded by the CBRAR signal, the signals VCAN and UCAN from the output circuit 408 are both at an inactive level.

Even after the decoder 400 has decoded the conditional branch instruction, the IDU 40 continues to use the instruction that follows the conditional branch instruction (or the instruction at the branch destination).
Since decoding continues, a queue ready mask control circuit 410 is further provided. The circuit 410 uses a mask signal INVO-2 to generate a queue ready signal IDQR for an instruction to be decoded after a conditional branch instruction.
Mask DY, 0-2 and BRENR from circuit 408
The mask signal INVO-2 is canceled by the signal.

If the instruction decoded after the conditional branch instruction is not an instruction to be executed depending on whether the branch condition is met or not, then
The clear circuit 411 clears the corresponding IDQRDY signal and prohibits the same instruction from being transferred to the EXU 60.

The operations of the circuits 405-411 described above are realized by the detailed circuit configurations shown in FIGS. 3A and 3H. Figure 3A shows the configuration of the circuits 405, 406, 408°409, and Figure 3B
is the circuit 407, 410, 4 related to the circuit queue 17 days.
11 is shown.

The operation will be explained below using the timing charts of FIGS. 1 to 3 and FIGS. 4 and 5. In this embodiment, when a conditional branch instruction is decoded, the instruction following the next address of the conditional branch instruction is pre-decoded.

Figure 4 shows the case where the branch condition specified by the conditional branch instruction is not satisfied, that is, the previously decoded instruction becomes valid, and Figure 5 shows the case where the branch condition is satisfied and the next instruction to be executed. is the instruction at the branch destination address, that is, the previously decoded instruction becomes invalid.

First, in FIG. 4, the decoder 400 starts decoding the instruction 0 before the conditional branch instruction (2), and the D-type flip-flop (D-F/F) 307 is decoded.

Assume that 317.360 stores "l".

Also, at this time, the EXU 60 is executing the instruction ■ stored in IDQ (2) 404, and
stores the instruction ■ between instruction ■ and instruction 0. Upon completion of the decoding of instruction O in the decoder 400, the sequencer generates IDQSTE, and as a result, AN
A QSLSTBI signal is generated from D-gate 312.

The decoding information of the instruction @ is thus IDQ(1) 403
Store in the store.

An SR type rough flip-flop (SR-F/F) 303 is set. IDQST delayed by delay circuit 314
The B signal causes D-F/Fs 316-318 to take in data on their D inputs. Multiplexer (MPX) 31
Although not shown, 9-321 is controlled by the VCAN signal, and the signal is inactive level (low level).
In this case, each of the Q outputs of F/Fs 316-318 is selected.

Therefore, the Q output “1” of F/F 317 is F/F 3
18, and the F/F 317 takes in the On signal from the F/F 316. Instruction 0 is an arithmetic and logic operation instruction, and E
Since this is an instruction to change the contents of the program status flag in the XTJ60, the decoder 400
A double signal is generated and 5R-F/F 506 is set.

When the operand address calculation and return for the instruction [phase] is complete, the MMIJ 50 generates the TLENDI signal, which causes the 5R-F/F 354 to be set. 5
Since R-F/F366-368 is in the reset state,
Their outputs Nvo-2 are at a high level, and as a result, I indicates that instruction 0 is executable.
The DQRDYI signal becomes active high level. This level causes the AND gate 507 to turn υn and the FHzD signal to go high.

Note that if the instruction ■ or ■ is also an instruction that can change the contents of the program status flag, the corresponding F/F50
2,510 is in the set state, and the FHzD signal is already at a high level. DF/F 35 by the TLENDI signal delayed by the delay circuit 362.
9-361 takes in input data D. MPX363-
364 is also controlled by the VCAN signal, so the F/F
Q output “1” of 360 is taken into F/F 361,
The F/F 360 takes in the Q output "0" from the F/F 359, and the IDQRDY1 signal remains at active high level due to the F/F 354.

The decoder 400 starts decoding the conditional branch instruction (2). During the decoding, EXtJ60 completes the execution of the instruction ■, generates the instruction execution end signal EXQEND, and
-Reset F/F518. That is, 5R-F/
F502, 506°510 are the corresponding IDQOs
-2 stores information on whether the instruction stored in 5R-2 can change the contents of the program status flag;
F/F 518 stores information whether an instruction being executed by EXU 60 may change the contents of the program status flag. When the EXU 60 finishes executing the instruction, it takes in the instruction on the bus 41. In this explanation, EX
Since the QSLO signal is active high level,
I
Imported into XU60.

When the EXU 60 receives an instruction, it generates an IDQACK signal. This signal provides information (F/F
502 store data) is taken into )/'F 518. The Q output ``1'' of F/F 307 is taken into F/F 308 by the IDQACK signal, so the F/F
The Q output of 307 becomes ``0'', and the IDQRDYO signal is inverted from high level to low level. In response to this inversion, one-shot pulse generator 08504 generates one-shot pulse EXQEO to reset F/F 502. Further, due to EXQEO, the OR gate 373 of the cue ready clear control circuit 411 generates VQCLRO, and resets F'/F 301°353. I
The DQRDYO signal is thus at an inactive level. F/F308 takes in Pa1'' and IDQRDY1
Since the signal is already at active high level, EXQ
The SLI signal becomes active high level. Thus,
The instruction ■ stored in IDQI (403) is read onto the bus 41. The EXU 60 is currently executing instruction (2).

The QSLSTE2 signal is generated by the IDQSTB signal indicating the completion of decoding of the conditional branch instruction 0 by the decoder 400, and the decoding information of the instruction ■ is sent to IDQ2 (404).
be taken in. F/F 303 is set, and data "1" is transferred from F/F 318 to F/F 316. The branch condition of conditional branch instruction 0 is passed to EXU 60 via bus 412 in advance. Decoder 400 also activates the CBRA signal. The FLAGM signal is low and F'/F 510 remains reset.

The AND gate 341 activates the latch circuit by the CBRA signal and the QSLSTB2 signal. In other words, the position (ID
Q2="001") is taken into the latch circuit 322. AND gate 341 further sets 5R-F/F 343. The output CBRAQL of the F/F 343 is delayed by the delay circuit 372 and becomes an AND game) 369-371
5R-F/F368 is not set. INV2 remains at high level. CBR
The AND gate 327 is opened by the AQL signal, but at least F/F 506 is in the set state and IDQRDY
Since the I signal is at an active high level, the output FHzR of the OR gate 519 is at a high level, and the output of the AND gate 327 is held at a low level. Signal TLE indicating the end of effective address calculation and conversion of branch destination address
5R-F/F355 is set by NDI and ID
The QRDY2 signal becomes active high level. Teda '1°' moves from F/F 361 to F/F 359.

Since the IDU 40 pre-decodes the instruction 0 at the address following the conditional branch instruction (2), the decoder 400 starts decoding the instruction 0. During this decoding, EXU
60 completes the execution of the instruction (2) and resets the F/F 518. The EXU 60 further determines whether the branch condition specified by the conditional branch instruction 0 previously passed from the decoder 400 matches the contents of its own program status flag each time the execution of the instruction ends, and sends the result to T A K
Output as EN signal. However, at this time, FH
Since the 2R signal is high l/bell and indicates a branch undetermined period, AND gates 324 and 325 remain closed, and the branch determined signal output circuit 408 outputs a valid VCAN signal.
, does not generate a UCAN signal.

Since the EXQSLI signal is high level, EXU60
takes in instruction 0 and outputs an IDQACK signal. This signal causes the store information of F/F 506 to be
1'' (in other words, indicates that the instruction [F] is an instruction that can change the contents of the program status flag) is F
/F 518, and the FH2R signal maintains a high level. In addition, by the DQACK signal, EXQ
SLI is inverted from high level to low level, and F/F5
Q6°354.302 is reset. F/F 30
9 takes in "1".

The QSLSTBO signal is generated upon completion of the decoding of the instruction (2), and the decode information of the instruction 0 is stored in the IDQ(0) 402. If this instruction 0 is capable of changing the contents of the program status flag, a FLAGM signal is also generated and F/F 502 is set. At this point, since the IDQRDYO signal has not yet been generated, the AND gate 503 remains closed. F/F 302 is set and data “'1” is from F/F 316 to F/F 31
Move on to 7. QSLSTBO signal and delayed CBRAQ
, L signal opens the AND gate 369 and F/F
366 is set. That is, for instruction 0, the queue ready mask signal IVO takes an active low level at 1- with the instruction decoded in advance after the decoding of conditional branch instruction 0. Therefore, even when the operand address calculation and conversion of instruction 0 is completed and the F/F 353 is set, it is masked by the IDQRDYO signal)11Vo signal and the AND gate 350 and remains at a low level. Since the IDQRDYO signal is masked, F/
The contents of F502 are also masked by AND gate 503. The decoder continues to predecode instruction 0, and the decode information for instruction 0 is stored in IDQ(1) 403. As for instruction 0, IDQRD for instruction 0
The Y1 signal is masked, and the information of the F/F 506 is also masked. Since unexecuted instructions (1) and 0.0 are stored in IDQ (0-2) 402-404, respectively, and there is no space left in the queue register, the AND gate 300 generates an IDQFULL signal at an active high level.

As a result, the sequencer 401 temporarily suspends the subsequent decoding process and temporarily suspends the transfer of instructions to the PDU 30.

When EXU60 finishes executing instruction 0, F/F518
is reset, and as a result, the FHzR signal is inverted to low level. That is, the circuit 409 notifies the output circuit 408 that the branch undetermined period has ended by the low level of the F HZ R signal.

As a result, AND games) 324 and 325 are opened.

The EXU 60 also connects the preceding 1. Generates a TAKEN signal indicating whether the branch condition of the conditional branch instruction . In this description, since the branch is not yet completed, the TAKEN signal is at a low level. Therefore, the output circuit 408 keeps the VCAN signal at a low level, sets the UCAN signal at a high level, and outputs that the branch condition is not satisfied. VCAN, U
The F/F 343 is reset by the output BREN of the CAN signal through the OR gate 323, and as a result, the output circuit 408 invalidates both the VCAN and UCAN signals. The F/Fs 366-368 are also reset by the BREN signal, and each mask signal INVO-2 becomes high level. Therefore, the masking of the IDQRDYo and 1 signals is canceled and the 6F/1 signal becomes active high level.
The masking of the outputs of F502 and 506 is also canceled, and instructions 0,
0 can change the contents of the program status flag, the F HZ R signal goes high. Thus, instruction 0,0 becomes a valid instruction to be executed. Since EXQSL2 is output at the end of execution of instruction 0, EXU60 receives instruction ■ and outputs IDQ
Generates an ACK signal. EXQSI, 2 is inverted from high to low I2, F/F 355 is reset and IDQRD
The Y2 signal goes low. Also, F/F 303
is reset and the IDQFULL signal becomes low level, so the IDU 40 starts decoding the instruction 0. Furthermore, the data “1” is from F/F309 to F/F
To move to 307, EXQSLO becomes high level and instruction 0 is output to bus 412. The EXU 60 receives the conditional branch instruction (2), but since the instruction has already been executed, the EXU 60 processes the instruction (2) as a so-called NOP (no operation) instruction. The EXU 60 then receives instruction 0 and starts executing it.

As is clear from the above explanation, even if the conditional branch instruction ■ is decoded, PDU30. IDU40. The MMU 50 continues the subsequent processing, and when the branch is not taken, the preceding processing is not invalidated and the flow of the pipeline processing does not substantially stop.

On the other hand, if the branch condition of conditional branch instruction ■ is satisfied,
As the VCAN signal becomes active high level as shown in FIG.
74,376 generates clear signal VQCLR70,11
~, reset F/Fs 354 and 355. Therefore, even if INVo,1 becomes high 1/bell and the mask is released, IDQRl)YO,l becomes low level, and the decoded instructions 0,0 are not executed and become invalid. F/F301 and 302 are also reset and IDQFUL
The L signal becomes low level. By the VCAN signal, B
IU20. PDU 20 is instructed to fetch the branch destination instruction. Furthermore, the VCAN signal is an OR game)3
F/F316-318,359- via 15,560
360, MPX319-321, 36
4-365 is instructed to select pointer information "001" of the branch queue register from the latch circuit 322.

As a result, data "1"' is taken into F/Fs 316 and 359, and F/Fs 317, 318, and 360° 361 take in data "ON".In other words, it is used as a queue register to store decode information of the instruction at the branch destination address. ,
Queue register IDQ (2) that stores conditional branch instruction 0
) 404, the next register IDQ(0) 402 is specified. I~ Therefore, no inconvenience occurs in the flow of instructions to be transferred to the EXU 60. The F/F 355 is reset by the IDQACK signal generated when the EXU 60 receives the instruction (2), and the IDQRDY2 becomes low level. Therefore, all IDQRDYO-2 are at a low level, and the NOR gate 310 generates a high-level IDQEMP signal to notify the EXU 60 that no executable decoded instruction exists in the queue register IDQO-2.

In response, the EXTJ 60 temporarily suspends receiving instructions from the IDU 40 and suspends processing until an executable decoded instruction exists in the IDU 40. Therefore, malfunction of EXU 60 is prevented. The branch destination instruction 0 is transferred from the PDU 30 to the IDU 40, and the IDU 40 completes decoding of the instruction and calculates the operand address.
When the conversion is completed and IDQEMP becomes low level, E
The XU 60 resumes processing, picks up instruction 0, and executes it.

In this way, if the branch condition is satisfied, the decoding process of instructions 0 and 0 and operand address calculation are performed.

The conversion process will be invalidated, but the ID will remain unchanged until the branch condition is finalized.
U40. This means that MMU50 is working effectively, and the effect is great. Here, since the calculation and conversion of the branch destination address has already been completed, the PDU30 executes the instructions @, @,
By configuring the structure so that instructions ω and ■ which are branch destinations are also prefetched in advance, the PPU 30 executes instructions 0, . o can be immediately transferred to the IDU 40. In this case, the flow of Vibrine processing is minimized with interruptions. In FIGS. 4 and 5, instruction [F] is an instruction that does not change the contents of the program status flag, and when instruction ■ changes the same contents, the TAKEN signal is determined at the end of execution of instruction ■, Valid VCAN and UCAN signals are output.

It should be noted that the specific configurations shown in FIGS. 3A and 3B are examples for realizing the functions of each circuit 405 to 411 in FIG. 2, and it is a matter of course that they can be modified as appropriate to achieve the same function.

FIG. 6 shows another embodiment of the invention. Components that are the same as those in FIG. 1 are indicated by the same numbers. In this embodiment, a prefetch/branch prediction hit def-1 branch prediction unit U) 600 is provided in place of the prefetch/predecode unit PDU 30 shown in FIG. This unit 600 is
In addition to instruction prefetch control and predecode control,
It also performs branch prediction control. BPP for branch prediction control
The DU 600 has a register (CPFIAR) 601. which stores the address of the currently prefetched instruction. A register (BRAIAR) 602 that stores an address (branch source address) where a conditional branch instruction is stored. 1/register (BRDTAR) 603 that stores the branch destination address specified by the branch instruction. and a comparator 604.

The contents of the CPFIAR 601 are normally updated every prefetch by the number of bytes of the prefetched instruction. B.R.A.
The IAR 602 can store the branch source address of the previously prefetched conditional branch instruction.

Therefore, program processing progresses and BRAIAR602
When the conditional branch instruction at the branch source address is fetched again, the comparator 604 outputs the branch prediction hit signal HITBR.
Generate A. And BPPDU600 is BRDTA
Using the contents of R603, prefetching is performed from the instruction at the branch destination address instead of the instruction following the conditional branch instruction.

The branch prediction hit signal HITBRA is supplied to the branch confirmation signal output circuit of the IDU 40. However, in Figure 6, 408
7, this configuration differs slightly from that of FIG. 3A, as shown in FIG.

That is, the HITBRA signal is stored in 5R-F/F 701. The Q output of F/F 701 is a multiplexer (
MPX) 702. MPX702 is F/F 7
When the Q output of 01 is "L", the outputs of AND gates 324 and 325 are
On the other hand, when it is '0', the AND gate 32
The output of 4,325 is output as VCAN and UCAN.

The basic operation of the IDU 40 is as shown in Fig. 4, except that the instruction transferred to the IDU 40 after the conditional branch instruction is changed.
Same as Figure 5. That is, when a branch prediction hit occurs as a result of the BPPDU 600 prefetching the conditional branch instruction ■, F/F 70.1 is set and the BPP
DU600 then branches to the instruction 0. Prefetch o.

Therefore, in FIGS. 4 and 5, "decoding processing" and 1.
The flow of instructions shown in the figure is ■→0→■→...

The branch condition is determined at the end of execution of instruction 0, but if this condition satisfies the instruction 00 condition, the AND game) 324
, 325 are at the no/y level and low level, respectively. Since F/F 701 is set, AND
The output of gate 324 becomes UCAN. Thus, I.D.
Instructions 0.Qo, stored in 1. The decoding information of o is valid and executed. On the other hand, when the condition is not met, V C
Since the A and N signals become active high level, the ID
Q.O.

■Store instruction 0. o becomes invalid, and the process shifts to prefetch and decode processing of instruction O2°. BPPDU 60
If branch prediction misses even if 0 prefetches a conditional branch instruction, the same operation as in FIGS. 4 and 5 will occur.

In the above-described embodiment, the operand of the defooded instruction of the branch condition instruction (2) must be accessed after the branch is established. For this purpose, the BIU 20 has an access information holding unit 800, as shown in FIG. The circuit 800 has three buffer registers ADR in a queue configuration.
O (801).

ADR,1 (803), ADR2 (805),
Operand access addresses are stored in each register. Additionally, a tag flag BTO (8
02), BTI (804), and Br3 (805), to which CBRA and QL (Fig. 3A) are input. Therefore, operand address information of an instruction decoded after conditional branch instruction 0, that is, an instruction decoded during a branch undetermined period, is temporarily stored in the holding unit 800 together with tag information indicating that the branch is in the same period. The access controller 810 receives the contents of BTO-2, and if there is tag information, temporarily suspends operand access. Then, in response to VCAN, the content of the holding unit 800 is invalidated, and in response to UCAN, it is validated and access is started.

In addition, in FIG. 8, access priority information may also be added to each buffer, and access may be started from the one with the highest priority in response to UCAN.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a microprocessor that does not stop the flow of vibe line processing even when a conditional branch instruction is coded, or that stops the flow to a minimum.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of the IDU shown in FIG. 1, FIGS. 3A and B are circuit diagrams of the main parts of FIG. 5 is a timing chart showing the operation of the IDU when decoding a conditional branch instruction, FIG. 6 is a block diagram showing another embodiment of the present invention, and FIG. 7 is a diagram showing the output circuit 408' shown in FIG. 6. Circuit diagram, 8th
The figure is a diagram showing the main parts of the B I U shown in FIG. 1 or 6.

Claims (1)

[Claims] a decoder for decoding instructions; a queue register for temporarily storing decode information from the decoder; and means for reading the decode information from the register when the decode information stored in the register is ready for execution;
an execution unit that receives and executes the read decode information;
Means for, in response to information indicating that the decoder has decoded a conditional branch instruction, masking the execution ready state of the instruction decoded by the decoder during a period until the branch condition specified by the conditional branch instruction is determined. and means for unmasking the execution ready state or changing the execution ready state to a non-executable state in response to the establishment/non-satisfaction of the branch condition after the branch condition is established, A microprocessor characterized in that when the execution ready state is changed to a non-executable state, decode information of another instruction is stored in a queue register in which decode information of the changed instruction is stored.