JPH02307239A - Monitoring structure for electrical property of integrated circuit chip - Google Patents
Monitoring structure for electrical property of integrated circuit chipInfo
- Publication number
- JPH02307239A JPH02307239A JP12932889A JP12932889A JPH02307239A JP H02307239 A JPH02307239 A JP H02307239A JP 12932889 A JP12932889 A JP 12932889A JP 12932889 A JP12932889 A JP 12932889A JP H02307239 A JPH02307239 A JP H02307239A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit chip
- wiring pattern
- monitoring
- outer peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、集積回路チップに形成された配線バクーン
における異常の有無を評価するために用いられる集積回
路チップの電気特性モニタ構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure for monitoring electrical characteristics of an integrated circuit chip, which is used to evaluate the presence or absence of an abnormality in a wiring backcoup formed on an integrated circuit chip.
従来から、ＭＯＳ−ＦＥＴなどのような集積回路子ノブ
における所要の配線パターンは、ウェハプロセスによっ
て形成されている。そして、このウェハプロセスにおい
て発生する配線パターンの断線やエレクトロマイグレー
ションというような異常の有無を評価するためには、第
４図で示すように、半導体基板Ｗ上に形成された集積回
路チップ２０の隣接位置に電気特性モニタ部２１を設け
たのち、この半導体基板Ｗをウェハプロセスによって処
理するようになっている。Conventionally, a required wiring pattern in an integrated circuit child knob such as a MOS-FET has been formed by a wafer process. In order to evaluate the presence or absence of abnormalities such as disconnection of wiring patterns and electromigration that occur in this wafer process, it is necessary to After the electrical property monitor section 21 is provided at the position, the semiconductor substrate W is processed by a wafer process.
すなわち、このようにして半導体基板Ｗを処理すると、
集積回路チップ２０における配線パターン（図示してい
ない）が形成されるとともに、電気特性モニタ部２１内
の互いに離間した所定位置にはパッド２２．２２が形成
され、かつ、これらを互いに連結するモニタ用配線パタ
ーン２３が同時的に形成されることになる。そこで、パ
ッド２２．２２を用いてモニタ用配線パターン２３の有
する抵抗を測定すれば、その異常が検出されることにな
り、その検出結果に基づいて集積回路チップ２０に形成
された配線パターンにおける異常の有無が評価されるこ
とになる。That is, when the semiconductor substrate W is processed in this way,
A wiring pattern (not shown) in the integrated circuit chip 20 is formed, and pads 22 and 22 are formed at predetermined positions spaced apart from each other in the electrical characteristic monitoring section 21, and pads 22 and 22 are formed for monitoring to connect these to each other. The wiring pattern 23 will be formed simultaneously. Therefore, if the resistance of the monitor wiring pattern 23 is measured using the pads 22 and 22, the abnormality will be detected, and based on the detection result, the abnormality in the wiring pattern formed on the integrated circuit chip 20 will be detected. The presence or absence of this will be evaluated.
ところで、これらの集積回路チップ２０を製造するにあ
たっては、１枚の半導体基板Ｗから数多くの集積回路チ
ップ２０が得られるように考慮するのが当然である。そ
のため、この半導体基板Ｗ上に設けられる電気特性モニ
タ部２１のスペースができる限り狭く設定される結果、
これに形成されるパッド２２．２２の離間間隔は極力短
く設定されてしまうことになる。したがって、これらの
パッド２２．２２間に形成されるモニタ用配線パターン
２３の配線長は必然的に短くなってしまい、これの異常
を感度よく検出することによって集積回路チップ２０に
形成された配線パターンにおける断線やエレクトロマイ
グレーションというような異常の有無を評価するのは大
変に困難となっていた。By the way, in manufacturing these integrated circuit chips 20, it is natural to take into consideration that a large number of integrated circuit chips 20 can be obtained from one semiconductor substrate W. Therefore, as a result of setting the space of the electrical characteristic monitor section 21 provided on the semiconductor substrate W as narrow as possible,
The spacing between the pads 22, 22 formed thereon will be set as short as possible. Therefore, the wiring length of the monitor wiring pattern 23 formed between these pads 22, 22 is inevitably shortened, and by detecting abnormalities in this with high sensitivity, the wiring pattern formed on the integrated circuit chip 20 is It has become extremely difficult to evaluate the presence or absence of abnormalities such as wire breaks and electromigration in
この発明は、このような不都合に鑑みて創案されたもの
であって、製品となる集積回路チップに形成された所要
の配線パターンにおける異常の有無を６ｉ実に評価する
ことが可能な集積回路チップの電気特性モニタ構造を提
供することを目的としている。The present invention was devised in view of these inconveniences, and is an integrated circuit chip that can accurately evaluate the presence or absence of abnormalities in a required wiring pattern formed on a product integrated circuit chip. The purpose is to provide an electrical characteristic monitoring structure.
この発明は、半導体基板上に配設された集積回路チップ
と、これの隣接位置に設けられた電気特性モニタ部とか
らなる集積回路チップの電気特性モニタ構造であって、
前記集積回路チップの外周端縁に沿う表面上には、前記
外周端縁に沿って交互に凹凸を繰り返す段差部を形成し
、かつ、この段差部を含む前記表面上のほぼ全周にわた
るモニタ用配線パターンを形成する一方、前記電気特性
モニタ部には、前記モニタ用配線パターンの端末それぞ
れが接続されるパッドを形成したことを特徴とするもの
である。The present invention is an integrated circuit chip electrical characteristic monitoring structure comprising an integrated circuit chip disposed on a semiconductor substrate and an electrical characteristic monitoring section provided adjacent to the integrated circuit chip,
A step portion is formed on the surface along the outer peripheral edge of the integrated circuit chip, and a stepped portion is formed that alternately repeats unevenness along the outer peripheral edge, and a monitor is provided over almost the entire circumference of the surface including the stepped portion. While a wiring pattern is formed, the electrical characteristic monitor section is characterized in that pads to which respective terminals of the monitoring wiring pattern are connected are formed.
上記構成によれば、集積回路チップの外周端縁に沿う表
面上に段差部を形成し、かつ、この段差部を含む前記表
面上のほぼ全周にわたるモニタ用配線パターンを形成し
ているので、配線長が長くなるばかりか、段差部におい
て断線などの異常を起こし易くなる。そこで、電気特性
モニタ部に形成されたバンドを用いることにより、集積
回路チップの外周端縁に沿って形成されたモニタ用配線
パターンの有する抵抗を測定すれば、その異常が容易に
検出されることになり、この検出結果に基づいて集積回
路チップに形成された配線パターンにおける異常の有無
が確実に評価されることになる。According to the above configuration, the stepped portion is formed on the surface along the outer peripheral edge of the integrated circuit chip, and the monitor wiring pattern is formed over almost the entire circumference of the surface including the stepped portion. Not only does the wiring length become longer, but abnormalities such as wire breakage are more likely to occur at stepped portions. Therefore, if the resistance of the monitoring wiring pattern formed along the outer peripheral edge of the integrated circuit chip is measured using a band formed on the electrical characteristic monitoring section, abnormalities can be easily detected. Based on this detection result, the presence or absence of an abnormality in the wiring pattern formed on the integrated circuit chip can be reliably evaluated.
以下、この発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図はＭＯ，５−ＦＥＴのような集積回路子ノブの電
気特性モニタ構造を示す平面図であり、第２図は集積回
路チップの外周端縁を拡大して示す平面図、第３図は第
２図のＩＩＩ−ＩＩＩ線に沿う断面図である。Fig. 1 is a plan view showing the electrical characteristic monitor structure of an integrated circuit child knob such as MO, 5-FET, Fig. 2 is a plan view showing an enlarged outer peripheral edge of the integrated circuit chip, and Fig. 2 is a sectional view taken along line III-III in FIG. 2. FIG.
本実施例に係る電気特性モニタ構造は、半導体基板Ｗ上
に配設された集積回路チップ１と、これの隣接位置に設
けられた電気特性モニタ部２とからなっており、この集
積回路チップｌの外周端縁に沿う表面上には、第２図及
び第３図で示すように、その外周端縁に沿って交互に凹
凸を繰り返す段差部３が形成されている。そして、この
段差部３を含む集積回路チップ１の外周端縁に沿う表面
上には、後述するモニタ用配線パターン４が形成される
ようになっている。The electrical characteristic monitor structure according to this embodiment includes an integrated circuit chip 1 disposed on a semiconductor substrate W and an electrical characteristic monitor section 2 provided adjacent to the integrated circuit chip 1. As shown in FIGS. 2 and 3, a stepped portion 3 is formed on the surface along the outer peripheral edge of the base plate 3. The stepped portion 3 has irregularities that alternately repeat along the outer peripheral edge. A monitor wiring pattern 4, which will be described later, is formed on the surface along the outer peripheral edge of the integrated circuit chip 1, including the stepped portion 3.
なお、前記段差部３を構成する凸部は、集積回路チップ
１を構成する素子（図示していない）のフィールド酸化
膜を形成する工程で形成された第１層６と、ゲート１極
形成工程で堆積してバターニングされたポリシリコンか
らなる第２層７と、これらを覆う絶縁＋１９形成工程で
形成されたスムースコートといわれる第３層８とからな
っており、また、この段差部３の凹部は、素子における
コンタクトホールと同時に形成されている。とごろで、
前記第２層７は、ポリシリコンからなるものに限定され
るものではなく、例えば、Ｍｏ５ｉｚやＷ５ｉ２などの
ようなシリナイドからなるものであってもよい。Note that the convex portion constituting the stepped portion 3 is formed by the first layer 6 formed in the step of forming a field oxide film of the elements (not shown) constituting the integrated circuit chip 1, and the step of forming the gate single pole. It consists of a second layer 7 made of polysilicon deposited and buttered in step 3, and a third layer 8 called a smooth coat formed in the step of forming insulation layer 19 covering these layers. The recess is formed at the same time as the contact hole in the element. In Togoro,
The second layer 7 is not limited to being made of polysilicon, but may be made of silinide such as Mo5iz or W5i2, for example.
そこで、この半導体基板Ｗをウェハプロセスによって処
理すると、集積回路チップｌの外周端縁に沿う表面上に
は、段差部３を含んで外周端縁に沿う表面上のほぼ全周
にわたるモニタ用配線パターン４が形成されることにな
る。そして、このモニタ用配線パターン４が形成される
と同時に、電気特性モニタ部２内にはバッド５，５が形
成され、かつ、これらのバッド５．５のそれぞれにはモ
ニタ用配線パターン４の端末が接続されることになる。Therefore, when this semiconductor substrate W is processed by a wafer process, a monitor wiring pattern is formed on the surface along the outer peripheral edge of the integrated circuit chip l over almost the entire circumference of the surface along the outer peripheral edge including the stepped portion 3. 4 will be formed. At the same time as this monitor wiring pattern 4 is formed, pads 5, 5 are formed in the electrical characteristic monitor section 2, and each of these pads 5.5 has a terminal of the monitor wiring pattern 4. will be connected.
そこで、これらのバッド５，５を介してモニタ用配線パ
ターン４の存する抵抗を測定すれば、その異常が検出さ
れることになり、その検出結果に基づいて集積回路チッ
プｌに形成された配線パターンにおける異常の有無が評
価されることになる。Therefore, if the resistance of the monitor wiring pattern 4 is measured through these pads 5, 5, the abnormality will be detected, and the wiring pattern formed on the integrated circuit chip l will be determined based on the detection result. The presence or absence of abnormalities will be evaluated.
以上説明したように、この発明に係る集積回路千ノブに
よれば、半導体基板上に配線された集積回路チップの外
周端縁に沿う表面上に段差部を形成し、かつ、この段差
部を含む前記表面上のほぼ全周にわたるモニタ用配線パ
ターンを形成しているので、この配線パターンの配線長
が長くなるばかりか、段差部において断線などの異常を
起こし易いものとなる。そこで、電気特性モニタ部に形
成されたバ・７トを用いてモニタ用配線パターンの有す
る抵抗を測定すれば、従来例のような配線長の短いモニ
タ用配線パターンによる測定に比べ、その異常がより容
易に検出されることになり、この検出結果に基づいて集
積回路チップに形成された配線パターンにおける異常の
を無を確実に評価することができる。As explained above, according to the integrated circuit Sennobu according to the present invention, a stepped portion is formed on the surface along the outer peripheral edge of an integrated circuit chip wired on a semiconductor substrate, and the stepped portion is included. Since a monitor wiring pattern is formed over almost the entire circumference on the surface, not only the wiring length of this wiring pattern becomes long, but also abnormalities such as wire breakage are likely to occur at stepped portions. Therefore, if the resistance of the monitor wiring pattern is measured using the bar formed in the electrical characteristic monitor section, the abnormality will be detected compared to the measurement using the monitor wiring pattern with a short wiring length as in the conventional example. This makes it easier to detect, and based on the detection result, it is possible to reliably evaluate whether there is any abnormality in the wiring pattern formed on the integrated circuit chip.
第１図ないし第３図は本発明に係り、第１図は本実施例
に係る集積回路チップの電気特性モニタ構造を示す平面
図、第２図は集積回路チップの外周端縁を拡大して示す
平面図であり、第３図は第２図のｍ−ｍ線に沿う断面図
である。また、第４図は従来例に係り、集積回路チップ
の電気特性モニタ構造を示す平面図である。
図における符号１は集積回路チップ、２は電気時性モニ
タ部、３は段差部、４はモニタ用配線パターン、５はバ
ンド、Ｗは半導体基板である。1 to 3 relate to the present invention, FIG. 1 is a plan view showing the electrical characteristic monitor structure of an integrated circuit chip according to the present embodiment, and FIG. 2 is an enlarged view of the outer peripheral edge of the integrated circuit chip. FIG. 3 is a cross-sectional view taken along line mm in FIG. 2. Further, FIG. 4 is a plan view showing a structure for monitoring electrical characteristics of an integrated circuit chip according to a conventional example. In the figure, reference numeral 1 is an integrated circuit chip, 2 is an electrical time monitoring section, 3 is a stepped portion, 4 is a monitor wiring pattern, 5 is a band, and W is a semiconductor substrate.
Claims (1)
れの隣接位置に設けられた電気特性モニタ部とからなる
集積回路チップの電気特性モニタ構造であって、 前記集積回路チップの外周端縁に沿う表面上には、前記
外周端縁に沿って交互に凹凸を繰り返す段差部を形成し
、かつ、この段差部を含む前記表面上のほぼ全周にわた
るモニタ用配線パターンを形成する一方、 前記電気特性モニタ部には、前記モニタ用配線パターン
の端末それぞれが接続されるパッドを形成したことを特
徴とする集積回路チップの電気特性モニタ構造。(1) An integrated circuit chip electrical property monitoring structure comprising an integrated circuit chip disposed on a semiconductor substrate and an electrical property monitoring section provided adjacent to the integrated circuit chip, the structure including: an outer peripheral edge of the integrated circuit chip; On the surface along the edge, a stepped portion is formed that alternately repeats unevenness along the outer peripheral edge, and a monitoring wiring pattern is formed over almost the entire circumference on the surface including the stepped portion, 2. A structure for monitoring electrical characteristics of an integrated circuit chip, wherein the electrical characteristics monitoring section is provided with a pad to which each terminal of the monitoring wiring pattern is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12932889A JPH02307239A (en) | 1989-05-23 | 1989-05-23 | Monitoring structure for electrical property of integrated circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12932889A JPH02307239A (en) | 1989-05-23 | 1989-05-23 | Monitoring structure for electrical property of integrated circuit chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02307239A true JPH02307239A (en) | 1990-12-20 |
Family
ID=15006880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12932889A Pending JPH02307239A (en) | 1989-05-23 | 1989-05-23 | Monitoring structure for electrical property of integrated circuit chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02307239A (en) |
-
1989
- 1989-05-23 JP JP12932889A patent/JPH02307239A/en active Pending
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