JPH0236010B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to access control to a main memory device of an information processing system, and in particular, to dividing the area of the main memory device into multiple areas and dividing them into logically separate areas. This invention relates to a method for generating addresses and checking limits in a system used as a storage space.

One method of using an information processing system is a method called a virtual computer method.

A virtual computer system is a system in which multiple operating systems, the same or different, coexist within one computer under the control of a control program, and each is used as if it were an independent computer system (i.e., as a virtual computer). It is known as a method that allows

There are various control methods for such virtual machines, and due to the differences in their functions, some programs that are created to run on one virtual machine method may not be able to run on other methods. It is desired that an information processing system be equipped with a function that can support a plurality of different virtual computer systems.

One of the differences between different virtual computer systems, which requires the above-mentioned measures, is:
There is a method for allocating real main storage to individual virtual machines.

[Conventional technology]

One method of allocating real main storage area to virtual machines is to divide the main storage area into continuous areas for each virtual computer, and allocate one continuous area at a time.

FIG. 2 shows an address generation/monitoring mechanism provided in a device (main memory access control device) that controls access to the main memory in such a system.

The area allocated to one virtual machine is limited, for example, by a register pair consisting of a base register 1-1 and a limit register 1-2. Here, the base register 1-1 holds the lower limit main memory address of the allocated area, and the limit register 1-2 holds the size of the area.

Address registers 2-1, 3-1, 4-1 and limit registers 2-2, 3-2, 4-2 also constitute a similar address pair, and the figure shows that up to 4 virtual machines can coexist with 4 register pairs. This is an example of what you get.

The operating system of each virtual machine is
Since the allocated main memory area is controlled by treating it as the main memory of the own system starting from address '0', the contents of base register 1-1, etc. corresponding to the virtual machine are added to the address generated by the virtual machine. becomes the actual storage address on main memory.

To this end, each virtual machine requests access by adding a virtual machine identification number via a signal line 6 along with an access address via an address line 5 in a main memory access request.

The main memory access control device uses a signal obtained by decoding the virtual machine identification number on the signal line 6 by the decoder 7 to control the gate circuits 1-3, 2-3, 3-3, 4-3.
is controlled to select one of the register pairs, and the adder 8 adds the lower limit address of the selected base register 1-1 etc. and the address of the address line 6 to generate a main memory address.

At the same time, limit register 1 of the selected register pair
Comparator 9 compares the contents of -2, etc. with the address of address line 6, and if the address value of address line 6 is greater than the contents of limit register 1-2, etc., output line 1
0 is turned on, and this signal inhibits access to the main memory.

This occurs when the virtual machine requests access to an address outside the allocated area and there is some kind of error in the control of the virtual machine.

The second method for allocating real main storage space to virtual machines is to divide the main storage space into contiguous areas for each virtual machine on the virtual memory of the virtual storage system, and
This method allocates continuous areas one by one.

In this method, areas are allocated in units of relatively small memory blocks called pages on the real main memory, and there is no need for consecutive addresses between pages, so there is flexibility in allocating the real main memory area. .

On the other hand, the address issued by the virtual machine is obtained through address conversion using the virtual memory method to obtain the actual main memory address, and in most cases the virtual machine itself uses the same virtual memory method, so page-based virtual memory Address translation in this method is performed twice, slowing down the processing speed.

For this purpose, only one virtual machine (hereinafter referred to as a real main memory virtual machine) that uses the real main memory address as the main memory address of the virtual machine can be provided, and in particular, processing speed can be improved. The system is designed to be able to respond to cases with severe demands.

In this second method, a contiguous area of the required size starting from address '0' of real main memory is used as an area for the virtual computer, and A contiguous area of size is allocated, and areas at higher storage addresses are allocated to other virtual machines in page units.

Therefore, when checking the main memory address generated in a main memory access request, it is necessary to check whether the address exceeds the upper limit of the allocated area when accessing the real main memory virtual machine.
For access by other virtual machines, check that the address is within the virtual machine area at an address higher than the real main memory virtual machine's allocated area, that is, it is not outside the area delimited by the upper and lower limits of the allocated area. is necessary.

[Problem that the invention seeks to solve]

In order to accommodate the different virtual computer systems mentioned above, it has conventionally been necessary to provide different monitoring means for each main memory allocation system, which has been a problem in terms of the economy of the information processing system.

[Means for solving problems]

This problem is a main memory access control device that has a plurality of register pairs, a selection means, an address generation means, and first and second comparison means.
Each said register pair has a base address register and a limit register, said selection means selects one of said register pairs according to an input predetermined number designation, and said address generation means selects one of said register pairs according to an input predetermined number designation. adding the value held in the base address register of the selected register pair to generate a main memory address; The second comparison means generates an access inhibition signal when the input address value is larger than the value to be held, and the second comparison means determines whether the input address value , generates the access inhibit signal when the value is not greater than the value held by the limit register of the second specific register pair, and when the access inhibit signal is not generated,
This problem is solved by the address check method of the present invention, which is configured to perform access using the main memory address.

[Effect]

That is, the base address register and limit register necessary for the first method of allocating the virtual machine's main memory are also used for the second method, and the second method is used as a specific access mode as described above.
If this method is specified, another specific limit register is used to check the lower limit address in access by a virtual machine other than the real main memory virtual machine.

Therefore, the generation of addresses necessary for the first method/
By adding a small amount of circuitry to the monitoring mechanism, the second scheme of address generation/monitoring can be accomplished completely.

Furthermore, in the method of the present invention, address generation in the second method is performed in the same manner as in the first method.
The allocated area of the second method does not necessarily have to start from the real main memory address '0', and has the additional advantage of greater flexibility in area allocation.

〔Example〕

FIG. 1 is a block diagram showing the configuration of an address generation/monitoring mechanism according to an embodiment of the present invention. The basic configuration of this embodiment is the same as that in FIG. 2, and the same parts in both figures are designated by the same numbers.

In FIG. 1, a comparison circuit 20 and related circuits according to the present invention are added, but in the first virtual computer method, this added part has no effect,
It operates in the same manner as described above with respect to FIG.

When using the above-mentioned second virtual machine method, for example, the virtual machine identification number '10' is set as the identification number of the real main memory virtual machine, and the other virtual machines of the second method are The virtual machine identification number '01' shall be assigned. Other identification numbers (identification numbers '00' and '11' in the example shown)
can be used for each virtual machine of the first method if necessary. Here, the selection of each register pair in FIG. 1 is as follows:
-3 is selectively opened, the register pair of base register 1-1 and limit register 1-2 is selected, and gate 2-3 is opened with virtual machine number '01'.
Gate 3-3 with number '10', gate 4-3 with number '11'
shall be selected respectively.

The limit register 3-2 of the register pair designated by the virtual machine identification number '10' becomes the input of the comparator 9 when the register pair is designated as in the case of FIG. It is also constantly connected to the input of the comparator 20.

Comparator 20 compares the access request address from address line 5 with limit register 3-2, and turns on output line 21 when the access request address is not greater than the contents of limit register 3-2.

The signal on the output line 11 is controlled by the AND gate 22, and is an access request for the virtual machine with the identification number '01', and the signal on the signal line 23 indicates a specific access mode (virtual machine of the second virtual machine type). Only when there is a signal indicating access (indicating access by) is outputted to the access inhibition signal line 25 via the OR gate 24.

The output line 10 of the comparison circuit 9 is connected to the OR gate 24.
is also input, and generates an address inhibit signal as explained in FIG. 2 in both the first and second virtual machine systems.

When applying the above mechanism to the second virtual machine method, address register 2-1 and address register 3-1 are allocated as areas for the virtual machine of the second virtual machine method as described above. The same address value (for example, 0) indicating the start address of the continuous area is set, and the address line 5 is set by the adder 8.
A main memory address is generated by adding the value held in the base address register 2-1 or 3-1 to the address value input from the base address register 2-1 or 3-1.

Also, a required size area is allocated from the beginning of the virtual machine area to the real main memory virtual computer, and an address value (relative address within the virtual machine area) indicating the upper limit of the allocated area is stored in the limit register 3-2. Set the maximum address of the virtual machine area, which is the upper limit of the remaining area allocated to other virtual machines, in the limit register 2-2. By doing this, the real main memory virtual machine with identification number '10' can access The request is based on base register 3.
-1 and limit register 3-2 perform address generation and monitoring in the usual way, and access requests from other virtual machines that specify identification number '01' are sent from limit register 3-2 to limit register 2-2. It is specifically checked that the address lies in the interval .

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a mechanism for performing two different address checks on a virtual machine can be constructed economically, so that it has a remarkable industrial effect of expanding the usable area of an information processing system. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional address generation/monitoring mechanism. In the figure, 1-1, 2-1, 3-1, 4-1
is the base register, 1-2, 2-2, 3-2, 4
-2 is the limit register, 1-3, 2-3, 3-3,
4-3 is a gate circuit, 5 is an address line, 8 is an adder, 9 is a comparator, 20 is a comparator, and 25 is an access inhibit signal line.

Claims (1)

[Claims] 1. A plurality of register pairs 1-1, 1-2 to 4-1,
4-2, selection means 7, 1-3 to 4-3, address generation means 8, first and second comparison means 9,
20, each register pair having a base address register and a limit register, and the selection means selects one of the register pairs according to an inputted predetermined number designation 6. the address generating means selects the input address value 5;
and the value held in the base address register of the selected register pair to generate a main memory address, and the first comparison means 9 calculates that the input address value is
generates an access inhibition signal 10 if the value is greater than the value held in the limit register of the selected register pair; register pair 2
-1, 2-2 is selected, the access inhibition signal 11 is generated when the input address value is not larger than the value held by the limit register 3-2 of the second specific register pair. An address check method characterized in that the address check method is configured to execute access using the main memory address when the access inhibit signal is not generated.