JPH0237633B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can operate at high speed and reduce power consumption.

[Technical background of the invention and its problems]

Conventionally, as a method to reduce the delay in signal propagation on the word line, the word line is divided into W ₁ and W ₂ as shown in Figure 1, and a two-stage inverter is installed between them.
There was a method of providing an amplification (or boosting) circuit consisting of I ₁ and I ₂ . That is, the word line has an electrical resistance R
There is a problem in that a signal propagating through the word line is delayed due to the presence of the capacitance C. This signal delay can be understood in the form that the signal waveform becomes dull when considered from the viewpoint of the rise of the voltage waveform of the signal. Therefore, we divided the word line to reduce R and C.
In addition, by providing inverters I ₁ and I ₂ , the potential in the middle of the word line is boosted to sharpen the rise of the signal (in other words, increase the boost speed), thereby eliminating signal delay. be.

However, in the case of the above-mentioned conventional method, there was a problem in terms of economy in that the power consumption was large, except when the amplifier circuit was constituted by a C-MOS type transistor. In other words, among the many word lines that exist in the memory circuit, only one word line is selected in one read operation, and the potential of all other word lines is below V _SS (ground potential). It's on the level.
At this time, the gate potential of inverter _I2 is at the level of positive power supply potential _VDD . Here, in Figure 2, E/
The relationship between the input and output potentials and the current consumption of a D-type inverter is shown. As can be seen from Figure 2, the current consumption is greatest when the gate voltage is at _VDD . Therefore, all the word lines in the non-selected state are causing a large current consumption to flow in the inverter _I2 , and the magnitude thereof is proportional to the number of word lines.

[Purpose of the invention]

Therefore, the present invention maintains high-speed operation performance while
An object of the present invention is to provide a semiconductor memory device that enables low power consumption.

[Summary of the Invention] In order to achieve the above object, in the present invention, the word lines are separated in the middle of the extending direction, and the two word lines are separated between the preceding and succeeding word lines formed by the separation. A first switching circuit that can electrically interrupt the line is inserted to connect both word lines, and a boosting circuit that utilizes the bootstrap effect is installed at the connection point between the first switching circuit and the subsequent word line. Connect the switching circuit of 2,
It is also characterized in that a third switching circuit is connected to lower the potential of the subsequent word line to the potential it should have when not selected.

The first, second and third switching circuits are each controlled by a control signal synchronized with the selection signal. A capacitor may be added to the second switching circuit to enhance the bootstrap effect.

There may be a plurality of word line separation locations depending on the number of memory cells on the same word line, and the above-described configuration is adopted for each location.

〔Effect of the invention〕

According to the present invention having such a configuration, the second switching circuit that utilizes the bootstrap effect enables low power consumption without continuing to flow current when not selected, and effectively boosts the word line potential when selected. By increasing the signal propagation speed, the storage device can operate at high speed. In addition, the second switching circuit and the third switching circuit can work together to rapidly lower the word line potential in the non-selected state. It is possible to prevent a selection error from occurring due to a low-speed non-selection operation in which a selection signal is input to a word line.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. First, in order to facilitate understanding of the present invention, FIG. 3 shows a block diagram of a RAM circuit using static memory cells as an example of a semiconductor memory device. The outline is described below.

In FIG. 3, address designation signal A is input to address buffer 1. In FIG. The address buffer 1 converts the input address designation signal A to the signal level within the memory chip and outputs it to the row decoder 2. The row decoder 2 decodes the addressing signal A and outputs one word line 5 on the memory array 4.
A selection signal φ _S is output to the drive circuit 3 to select. Here, the selection potential of the word line is the positive power supply potential.
If V _DD , the potential of the selection signal φ _S is the negative power supply potential.
V _SS falls and the word line is boosted to V _DD potential.
On the other hand, when not selected, the selection signal φ _S is at the positive power supply potential.
V _DD rises and the word line is lowered to the V _SS potential level.

In addition, in FIG. 4, word line 5 and bit line 6
Although only one pair is shown, it is well known that these are actually combined in a matrix. 7 is a static memory cell.

First Example A first example is shown in FIG. In FIG. 4, the word line 5 is divided into two parts in its extending direction, a front-stage word line _W1 and a rear-stage word line ₂ . Note that one word line 5 is not necessarily divided into two as in this example, but may be divided into a plurality of parts; however, in this specification, in order to simplify the explanation, the word line 5 will be described as being divided into two. A first switching circuit consisting of a MOS transistor _Q1 is inserted in series between _the separated front-stage word line _{W1 and} rear-stage word line _W2 . The word line _W2 is connected intermittently. Further, a second switching circuit 8 and a third switching circuit 9 are connected to the connection point between the transistor _Q1 and the input of the subsequent word line _W2 .

Transistor _Q1 receives at its gate a first control signal _φW1 that changes in synchronization with the change in selection signal _φS , and connects and disconnects the source and drain, thereby connecting the previous word line _W1 and the subsequent word line _W2. connect or disconnect.

The second switching circuit 8 is constructed using MOS type transistors Q ₂ and Q ₃ . transistor
The source of Q ₂ is connected to the connection point A between the source of the transistor Q ₁ and the preceding word line W ₁ , the drain is connected to the gate of the transistor Q ₃ , and the positive side power supply voltage V _DD is applied to the gate. transistor
A first control signal φ _W1 is applied to the drain of Q ₃ ,
The source is connected to a connection point C between the drain of the transistor _Q1 and the subsequent word line _W2 . This second switching circuit 8 is a circuit for boosting the word line signal of the selected word line at the time of selection, and operates using the bootstrap effect as described later.

The third switching circuit 9 is constituted by a MOS type transistor _Q4 . The drain of the transistor _Q4 is connected to the connection point C, and the negative side power supply voltage _VSS is applied to the source. A selection signal φ _S is applied to the gate.
A second control signal φ _W2 is provided which is generated in synchronization with the change in (therefore, the first control signal). This third switching circuit 9 is a circuit for lowering the potential of word lines W ₁ and W ₂ to V _SS when not selected.

Next, the operation will be explained based on FIGS. 5, 6, and 7. Figures 5 a to d are selected, Figures 6 a to d
Similarly, FIG. 7 shows another example when the signal is selected, and FIG. 7 shows each signal waveform when the signal is not selected.

First, the operation at the time of selection will be explained (FIG. 5). Assuming that a word line is selected at time _t0 , the selection signal _φS falls to _VSS and is inverted by the drive circuit 3, so that the potential of the previous word line _W1 rises toward _VDD . Output side potential V _A of previous stage word line W ₁
If we pay attention to this, we can see something like Fig. 5c. During this time,
First control signal φ _W1 = V _SS , second control signal φ _W2 = V _DD
Therefore, transistor Q ₁ is non-conducting (hereinafter referred to as OFF) and Q ₄ is conductive (hereinafter referred to as ON), and the potential of the subsequent word line W ₂ is equal to V _SS regardless of whether it is selected or not. It has a potential. On the other hand, the potential V A at the connection point _A is connected to the previous word line W ₁ as shown in Fig. 5c.
The potential V _A is applied to the gate of the transistor Q ₃ via the transistor Q ₂ , and its gate potential V _B increases at the same rate as V _A (Figure 5d). Then, at time t _po , the gate potential V _B becomes the threshold voltage of transistor Q ₃
When V _T is reached, Q ₃ turns ON. However, at this time, the first control signal φ _W1 still remains at the potential of V _SS and the transistor Q ₄ is also ON, so the potential V _C at the connection point C does not rise, and therefore the potential of the subsequent word line W ₂ increases. Potential does not rise. Next, at time t ₁ when the gate potential V _B has risen to a certain extent, the first
The control signal φ _W1 changes to V _DD , and the second control signal φ _W2 changes to
When V _SS falls, the transistor Q ₃ is in the ON state and the channel portion is inverted, so the gate potential V _B is boosted by ΔV _B due to the capacitance between the gate and the drain, as shown in FIG. 5d. The boosted potential V _B tries to be discharged through the transistor Q ₂ because there is a potential difference between it and V _A , but if the conductance of the transistor Q is changed from time t ₀ to _{t 1} , By keeping the gate potential V B small enough to follow, a sudden discharge of the gate potential V _B will not occur.
The potential V C at point _C rises faster due to transistor Q ₃ being turned on. On the other hand, the rise of the potential V _C at point C boosts the potential V _A at point A due to the conduction of transistor Q ₁ , and the potential difference between V _B and V _B rapidly decreases. Of course, at the moment when the first control signal φ _W1 reaches the potential of V _DD , there is a relationship of V _A > V _C , so the potential of V _A momentarily decreases (Fig. 5c), but the sudden rise in V _C Due to the rising voltage, V _A is boosted in the same way as V _C. Furthermore, due to the bootstrap effect via the capacitance of the inverting gate of transistor _Q3 , which is in the ON state due to the rise of V _C , V _B
is boosted, thereby causing transistor Q ₃ to boost V _C without interruption. Then, when V _C reaches (V _DD − V _T ), transistor Q ₁ turns OFF.
Therefore, V _A is no longer boosted by V _C , but after that, the word line signal obtained by inverting the selection signal φ _S from the row decoder 2 by the drive circuit 3 causes V _A to rise to V _DD . Boosted. In addition,
The broken line in FIG. 5c indicates the first control signal φ _W1 =V _SS ,
It shows the change when the second control signal φ _W2 =V _DD remains in the state. In other words, the broken line shows the boosting speed at point A when the booster circuit of the present invention is not used.
Considering the delay caused by connecting W ₂ to the output end A of the preceding word line and the signal delay at the word line W ₂ itself, the termination of the subsequent word line W ₂ (i.e.
It is easy to imagine that the broken line in FIG. 4c would rise even more slowly at the end of a single word line that does not use any booster circuit. On the other hand, according to the present invention, the voltage rises rapidly as shown by V _C , so high speed is possible.

In the above explanation, an example was described in which the voltage is boosted once with the highest value as V _DD when the first control signal φ _W1 has a positive value (Figure 5b), but as shown in Figure 6a, the voltage is boosted twice. It may be boosted above V _DD for a period of time. In that case, a double bootstrap effect appears in the gate voltage _VB , and the potential at the point _C can be made to be a potential difference greater than _VDD (see FIGS. 6b and 6c). That is, the first control signal φ _W1 is boosted to V _DD at time t ₁ and further boosted at time t ₂ . Due to this boosting, the gate voltage V _B is boosted twice by ΔV _B1 and ΔV _B2 due to the bootstrap effect. By doing this, even the V _DD voltage level that is difficult to write into the memory cell becomes easier to write to since the word line potential becomes higher than V _DD . Of course, in this case, the drive circuit 3 receiving the selection signal φ _S from the row decoder 2 must also be able to output a voltage higher than V _DD . Although not shown in FIG. 6, the second control signal φ _W2 changes from the V _{DD voltage level to the V SS voltage} level at time t ₁ as in FIG. 5 a.
Operates falling to the voltage level.

Next, the operation when not selected will be explained (FIG. 7).
Now, the word line is unselected and the selection signal φ _S is
When V _DD rises, it is inverted by the drive circuit 3, so the potential of the previous word line W ₁ decreases as it approaches V _SS . On the other hand, at time _t2 almost at the same time as the non-selection, the first control signal φ _W1 changes to the potential of V _SS and the second control signal φ _W2 changes to V _DD . Therefore, the transistor _Q4 is turned on, and the potential at point C, _Vc , is discharged through the transistor _Q4 and drops toward _VSS . Also, at this time, the transistor
Since Q ₃ is also in the ON state, the first control signal is at the potential of V _SS , so the C point potential V _C is the transistor Q ₃
It also descends through (Fig. 7c). Then, the gate voltage V _B of transistor Q ₃ also falls due to the capacitor coupling by the inverting gate of Q ₃ (FIG. 7a). However, the potential V _A at point A is the transistor Q ₁
is turned OFF (φ _W1 =V _SS ), so it is discharged by the drive circuit 3 and falls (FIG. 7c). Therefore,
The gate voltage V _B drops due to the effect of the capacitance between the drain and gate of the transistor Q ₃ , and then becomes lower once than the potential at point A V _A via the transistor Q ₂ , but then drops along with the voltage V _A (Figure 7 d). . Thus, a transition from a selected state to a non-selected state is performed.

The circuit according to the present invention described above can be further configured with various modifications as shown in FIGS. 8 to 11, for example.

Second Embodiment In FIG. 8, this embodiment has a capacitor _CG added between the gate and drain of the transistor _Q3 in the first embodiment (FIG. 4).
By adding this capacitor C _G , the rise of the gate voltage V _B due to the rise of the first control signal φ _W1 is increased compared to the rise of the potential V _C at point C, and the voltage of the transistor Q ₃ in the initial operation at the time of selection is increased. The conductance is increased, thereby speeding up the boosting operation as the second switching circuit. However, the magnitude of C _G is limited to such a value that the gate voltage V _B of transistor Q ₃ on the unselected word line does not exceed its threshold voltage due to the rise of φ _W1 . This prevents the non-selected word line from being boosted via transistor _Q3 due to the rise of φ _W1 . The other configurations are the same as those shown in FIG. 3, so their explanation will be omitted.

Third Embodiment In FIG. 9, contrary to the case in FIG. 8, this embodiment adds a capacitor C _B between the gate and source of the transistor _Q3 , which increases the bootstrap effect on the selected word line. It is a strengthened version of

Fourth Embodiment In this embodiment shown in FIG. 10, the gate voltage is changed as shown in FIG. 5d in the first embodiment (FIG. 4).
This is an improvement made to solve the problem that V _B slightly decreases after time t ₁ . In other words, the reason for this decrease in V _B is that even if the voltage is increased by ΔV _B , a part of it is due to the capacitive coupling effect of the inverting gate due to the rise of the first control signal φ _W1 at time t ₁ .
The problem is that it is discharged through the transistor _Q2 which is in the ON state. This is transistor Q ₂
This is because the voltage of V _DD is always applied to the gate of . Therefore, in order to eliminate this discharge, transistor Q ₂ may be turned off at time t ₁ . Therefore, in order to turn off the transistor Q ₂ at the time t ₁ , in this embodiment, the second control signal φ _{W 2} that falls at the time t ₁ is applied to the gate of the transistor Q ₂ .

Fifth Embodiment In this embodiment shown in FIG. 11, a capacitor C _B is added between the gate and source of the transistor Q ₃ in the circuit of the fourth embodiment (FIG. 10). By adding this capacitor C _B , it is possible to prevent the word line potential from being boosted via the transistor Q ₃ due to the rise of the first control signal φ _W1 in the non-selected state.

In other words, when not selected, transistor Q ₃
is off, and although there is no capacitive coupling effect due to the inversion gate, due to the slight capacitive coupling effect due to the slight overlap between the drain and gate of transistor _Q3 , the gate of transistor _Q3 is turned off by the rise of the first control signal φ _W1 . Voltage V _B is slightly boosted. The boost of this gate voltage V _B is the transistor
When the threshold voltage V _T of Q ₃ is exceeded, the transistor Q ₃
is turned ON, and as a result, the subsequent word line _W2 is boosted. This results in incorrect selection. Therefore, by adding a capacitor C _B between the gate and source of transistor _Q3 ,
Transistor Q ₃ depends on the capacitance ratio between the drain and gate of transistor Q ₃ and the capacitor C _B.
The increase in the gate voltage V _B of the gate voltage V B is suppressed to below the threshold voltage V _T , thereby preventing the voltage increase of the subsequent word line W ₂ . A suitable value for the capacitor C _B that exerts such a suppressing effect is V _T >C _gsd /2C _gsd +C _S +C _B V _DD Therefore, C _B >C _gsd (V _DD /V _T -2) - C _S Given. Here C _gsd : Transistor Q ₃
Capacitance between the gate and source or drain in the OFF state, C _S : Capacitance other than the capacitance of the gate of transistor Q ₃ and C _B .

In the above embodiment, the gate of the MOS transistor Q ₂ is connected to the V _DD power supply or the second control signal source to initially select the word line on the previous stage word line W ₁ in accordance with word line selection. The signal is transferred to the gate of transistor Q ₃ to turn transistor Q ₃ on, and then when boosting the subsequent word line W ₂ using the first control signal, transistor Q ₂ is used to prevent the gate potential of transistor Q ₃ from dropping.
is in the OFF state. For this purpose of operation of the transistor Q ₂ , a constant voltage power supply, which is a little lower than the V _DD potential, is connected to the gate of the transistor Q ₂ , and the voltage of the subsequent word line W ₂ is boosted by the first control signal. The transistor Q ₂ may be easily turned off when the gate potential of Q ₃ is boosted. Furthermore, it has a signal waveform that rises with the selection of the word line,
When the first control signal source rises and the subsequent word line _W2 is boosted, a third signal source with a signal waveform with a slow rise speed is connected to the _gate of the transistor _Q2 , such that the voltage has not yet been fully boosted to the VDD potential. do,
The transistor Q ₂ may be easily turned off when the gate potential of the transistor Q ₃ is boosted. In either case, at the rising edge of the first control signal, transistor Q ₂ is activated on the selected word line.
On the other hand, in the unselected word line, transistor Q ₂ is in the ON state and the gate potential of transistor _{Q 3 is} set to the rising edge of the first control signal. In this case, boosting of the word line _W2 in the subsequent stage is prevented by making it difficult to boost the voltage. As described above, the word line potential boosting circuit according to the present invention is not limited to the first to fifth embodiments, and several modifications can be considered in connection thereof.

Note that the word line booster circuit according to the present invention can be applied not only to static circuits but also to dynamic circuits. FIG. 12 shows a circuit in which the first embodiment of the present invention is applied to a dynamic circuit using a transfer transistor _Q5 . Note that 10 is a word line drive circuit. Of course, not only the first embodiment but also the second to fifth embodiments can be similarly applied to dynamic circuits.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example in which a boost inverter is inserted between conventional separated word lines, and Figure 2 shows the relationship between the output potential and the input potential of the boost inverter in Figure 1, and the relationship with current consumption. 3 is a block diagram showing a RAM circuit using a general static memory cell. FIG. 4 is a circuit diagram showing a first embodiment of a word line of a semiconductor memory device according to the present invention. Figures 5 a to d are timing charts showing the operation waveforms of each part at the time of selection, and Figure 6 a.
~c is a timing chart showing the operation waveforms of each part when boosting the voltage in two stages at the same selection time, Figure 7a~
d is a timing chart showing the operation waveforms of each part when not selected, FIG. 8 is the second embodiment, FIG. 9 is the third embodiment, FIG. 10 is the fourth embodiment, and the eleventh embodiment.
The figure is a circuit diagram showing a fifth embodiment, and FIG. 12 is a circuit diagram showing another embodiment. W ₁ …Previous word line, W ₂ …Later word line, Q ₁ …
Transistor (first switching circuit), 8...Second switching circuit (transistor Q ₂ , Q ₃ ), 9
...Third switching circuit (transistor Q ₄ ), φ _S
...selection signal, φ _W1 ... first control signal, φ _W2 ... second control signal, V _DD ... positive side power supply voltage, V _SS ... negative side power supply voltage, C _B , C _G ... capacitor.

Claims (1)

[Scope of Claims] 1. In a semiconductor memory device, the word lines are separated in the middle of the extending direction, and between the preceding word line and the subsequent word line formed by the separation, there is a connection to the word line. A first switching circuit that is controlled by a first control signal synchronized with a change in the selection signal of the word line and becomes conductive when selected and non-conductive when not selected is interposed to connect both of the word lines, At the connection point between the switching circuit No. 1 and the subsequent word line, it is controlled by the first control signal to be conductive when selected to boost the selection signal, and to set the potential of the subsequent word line when not selected. A second switching circuit is connected to lower the potential to the desired potential, and the connection point between the first switching circuit and the subsequent word line is controlled by a second control signal synchronized with a change in the selection signal to become conductive. . A semiconductor memory device, characterized in that a third switching circuit is connected to lower the potential of a subsequent word line to a desired potential when not selected. 2. In the device according to claim 1,
The first switching circuit is composed of a MOS transistor whose source is connected to the output end of the preceding word line, whose drain is connected to the input end of the subsequent word line, and whose gate is connected to the first signal source. A semiconductor memory device characterized by: 3. In the device according to claim 1 or 2, the second switching circuit has a drain connected to the first control signal source and a source connected between the first switching circuit and the input end of the subsequent word line. a first MOS type transistor connected to the connection point;
1. A semiconductor memory device comprising: a second MOS type transistor having a source connected to an output end of a preceding word line and a drain connected to a gate of the first MOS type transistor. 4. In the device according to claim 1, 2, or 3, the third switching circuit has a drain connected to the input end of the subsequent word line, a source connected to the power supply, and a second switching circuit. A semiconductor memory device comprising a MOS transistor whose gate is connected to a control signal source. 5. In the device according to claim 3,
A semiconductor memory device characterized in that a capacitor is connected between the gate of the first MOS transistor and the connection point between the first control signal source or the first MOS transistor and a subsequent word line. 6. In the device according to claim 3,
A semiconductor memory characterized in that the gate of the second MOS transistor is connected to another power source, a constant voltage source, a second control signal source, or a signal source different from the first and second signal sources. Device.