JPH023822A - data processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device that executes a load instruction of a processor.

BACKGROUND ART FIG. 3 shows a configuration diagram of a conventional data processing device, in which 1 is a data buffer that holds data in an external memory, 4 is a data bus A that transfers data, and 5 is a data bus that transfers data. Bus B, 7 is a data bus C for transferring data, 2 is an input data bus for transferring data from data bus C7, 3 is for writing data on input data bus 2 and reading data on data bus A and data bus B. A register file 6 includes a plurality of registers, and data bus A4. An arithmetic circuit receives the data bus B5, performs arithmetic operations, and outputs the result to the data bus C7; 8 is a flag generation circuit that generates a flag from the result of the arithmetic circuit 6;

In the conventional device configured as described above, in the case of a load instruction to write data in the external memory to the register file 3, the data in the data buffer 1 holding the data in the external memory is sent to the data bus B5. After that, it passes through the arithmetic circuit 6 and is written into the register file 3 via the data bus C7. Here, with this load instruction, the MSB
If it is necessary to reflect a flag, etc., the flag generation circuit 8 generates the necessary flag from the result of the arithmetic circuit 6.

Further, FIG. 4 shows the vibe line operation in FIG. 3, and shows the external bus, arithmetic execution, and write (register file) stage. Here, it is assumed that the nth instruction is a load instruction. After the operation of the (n-1)th instruction is executed, the nth source data is output to the external bus, and the write stage follows the operation execution stage. Therefore, when a load instruction is executed, an empty space occurs in the pipeline.

Problems to be Solved by the Invention In the above configuration, when executing a load instruction that requires flag reflection, the data in data buffer 1 is written to the register file via the arithmetic circuit. The problem was that it took a long time to execute the instructions, resulting in empty space in the pipeline.

In view of this, an object of the present invention is to provide a data processing device that can execute load instructions at high speed.

Means for Solving the Problems The present invention is a data processing device comprising a register file into which data from an external bus is directly input, and a flag generation circuit which generates a flag from the input of the register file.

Effect of the Invention With the above-described configuration, the present invention allows data on an external bus to be written directly to a register file and at the same time generates a flag in a flag generation circuit, thereby making it possible to execute a load instruction requiring flag reflection at high speed.

Embodiment FIG. 1 is a block diagram of a data processing apparatus in an embodiment of the present invention. In Figure 1, 4 is a data bus A that transfers data, 5 is a data bus B that transfers data,
7 is a data bus C for transferring data; 2 is an input data bus for transferring data from the data bus C7 and an external bus;
3 is a register file that writes data to input data bus 2 and reads data to data bus B, and includes a plurality of registers; 6, data bus A4.
A calculation circuit inputs the data bus B5, performs calculations, and outputs the calculation result to the data bus C7. Reference numeral 8 denotes a flag generation circuit that receives data from the input data bus 2 and generates a flag.

The operation of this embodiment configured as above will be described below.

In the case of a load instruction that writes external memory data to a register file, the external bus data is input to input data bus 2.
and written to register file 3. Here, if this load instruction requires reflection of a flag such as the MSB flag, the flag generation circuit 8 immediately generates the necessary flag.

Further, even in normal inter-register calculations, the flag generation circuit 8 can generate a flag when the calculation result is output to the input data bus.

FIG. 2 shows the pipeline operation in this embodiment, and shows the external bus, arithmetic execution, and write (register file) stages. Here, it is assumed that the nth instruction is a load instruction. After the n-1st instruction is executed and the nth source data is output to the external bus, the write stage is immediately entered. Therefore, pipeline operations can be efficiently executed even when executing a load instruction.

As described above, according to this embodiment, with the configuration in which data is written directly from the external bus to the register file and the flag is generated by the flag generation circuit at the same time, load instructions that require flag reflection can be executed at high speed and efficiently. Pipeline operations can be executed.

As described in detail, according to the present invention, by writing data directly from an external bus to a register file and simultaneously generating a flag in a flag generation circuit, a load instruction that requires flag reflection can be executed at high speed. The practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data processing device in an embodiment of the present invention, FIG. 2 is a timing diagram showing the pipeline operation of FIG. 1, and FIG. 3 is a diagram showing the configuration of a conventional data processing device. The block diagram, FIG. 4, is a timing diagram showing the pipeline operation of FIG. 1...Data buffer 2...Input data bus, 3
...Register file, 4...Data bus A15.
...Data bus B16...Arithmetic circuit, 7...Data bus C, 8...Flag generation circuit.

Claims (1)

[Claims] A register file that directly inputs external bus data,
A data processing device, comprising: a flag generation circuit that generates a flag from input of the register file, and executes a load instruction at high speed.