JPH0240923A - How to make bipolar transistors - Google Patents

Abstract

PURPOSE: To form emitter stripe regions of about 0.1μm by growing an opposite conductivity type epitaxial layer on one conductivity type semiconductor substrate, forming base regions intruding into the substrate and emitter regions located in the epitaxial layer, covering the entire surface with a mask and forming windows for the emitter regions. CONSTITUTION: On an n<-> type Si substrate 12 is grown a p<++> type layer 18. Polycrystalline regions 22 at both ends of the layer 18 and isolation regions 16 intruding into the substrate 12 form mesa parts 14 of the substrate laminate. P<+> type base regions 21 intruded into the substrate 12 and n<+> type emitter regions 54 involved in the layer 18 above the regions 21 are formed by diffusion in the center of the mesa laminate. A p<++> type layer 34 for masking the entire surface, including them is epitaxially grown. Openings 44 are bored corresponding to the regions 54, the inner walls of the openings 44 are insulated by insulation elements 30 and thermal oxide layer 42 and conductive polycrystals 52 are buried therein, and emitter-contact layer 56 is formed on this surface, thus defining emitter windows by the layer 34 openings.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention relates to a method for manufacturing bipolar transistors;
In particular, the present invention relates to a method of forming an emitter window for a bipolar transistor having a self-aligned emitter-base region.

B. Prior Art In the manufacture of bipolar transistors, much research has been directed toward increasing the speed of the transistors. One way to increase the speed of the transistor is through transistor geometry. For high speed bipolar transistors, two critical dimensions are the emitter stripe width and the base thickness. The width of the emitter stripe is defined by the lateral dimension of the emitter region and the thickness of the base is defined by the longitudinal dimension of the base region. Because base resistance is a significant impediment to transistor speed, it is desirable to minimize both the emitter stripe width and the base thickness to produce transistors with low base resistance. Furthermore, the length-to-width ratio of the emitter must be as large as possible. Also, since the emitter length is determined by other manufacturing constraints, the width of the emitter stripe is the only dimension that can be adjusted to reduce base resistance.

In typical bipolar transistor manufacturing, the emitter windows that define the stripe width are positioned and dimensioned using photolithography. That is, a photolithographic mask is positioned over a layer of polysilicon epitaxially grown on a single-crystal silicon substrate, and an emitter window is then etched through the layer of polysilicon to expose regions of single-crystal silicon. Ru. Experience has shown that it is very difficult to etch emitter openings in the extrinsic base polysilicon layer without excessively etching the essential base region. Photolithographic methods for defining emitter windows have dimensional limitations, with the typical smallest emitter stripe width available being about 0.7 microns.

Additionally, the use of photolithographic masking techniques results in inaccuracies and poor reproducibility due to inadequate alignment with the intrinsic base.

Various techniques for defining emitter windows have been used to overcome the shortcomings of the prior art. US Patent No. 4499
No. 657 uses photolithography to simultaneously define emitter and base windows to reduce some of the effects of misalignment. However, the width of the emitter stripes is limited to a range of 0.5 to 2 microns.

US Pat. No. 4,504,332 discloses a self-aligned technique for manufacturing bipolar transistors. A thermal oxide layer, a silicon nitride layer, and a boron oxide layer are sequentially deposited on a single crystal silicon substrate. Using normal photolithography techniques, the windows are etched to form both the base and emitter. A layer of silicon is epitaxially grown over the entire substrate, with polysilicon formed over the insulating layer and single crystal silicon formed over the exposed areas of the substrate. Doping the polysilicon area (
g) An external base region is formed.

A conformal thermal oxide layer is then deposited over the polycrystalline and single crystal silicon regions and the thermal oxide is etched to expose the single crystal. An internal base region is then formed by implantation and an emitter region is formed by diffusion from a conformal, doped oxide layer. Contact openings for the emitter, base and collector are then formed in the oxide layer. The emitter and base are self-aligned, but the processing steps are many and complex. Additionally, because the emitter window is defined by conventional photolithography techniques, there is a limit to the width dimension.

PROBLEM SOLVED BY THE INVENTION It is an object of the present invention to provide a bipolar structure in which the emitter window is defined by the use of selective epitaxial growth of silicon.
The object of the present invention is to provide a method for manufacturing a transistor.

In accordance with the present invention, a transistor is provided that has a much narrower emitter stripe width than was possible in the prior art.

According to the invention, less than 0.5 microns, and even less than 0.1 microns.
Transistors with emitter stripe widths on the order of microns are provided.

Means for Solving the D0 Problem The method for manufacturing a bipolar transistor of the present invention includes the first
A substrate made of a semiconductor material of conductivity type is provided, and a second layer is placed on this substrate.
depositing a first layer of semiconductor material of a conductivity type by non-selective epitaxy. An element of insulating material is formed over a portion of the first layer, and a second layer of semiconductor material of a second conductivity type is formed over the first layer by selective epitaxy. This selective epitaxy causes a portion of the second layer to laterally overgrow a portion of the top surface of the element. As a result, an opening is formed in the second fuchu,
An exposed area is left on the top surface of the element. A layer of insulating material is formed on the second layer to narrow the aperture and reduce the exposed area of the element.

The exposed area of the element is removed through the aperture and the first
A portion of the layer is exposed to form a region of a first conductivity type in the first layer.

According to one embodiment of the invention, a substrate of a semiconductor material, such as silicon, of n-conductivity type includes a buried oxide isolation region (
A mesa (14) is provided, surrounded by (16). A first layer (18) of n-conducting type silicon is deposited over the mesa and isolation regions by use of conventional non-selective epitaxial growth techniques. This deposition forms a region of polysilicon (22) on the isolation region of the substrate and a region of monocrystalline silicon (20) on the mesa.
is formed. An element (30) of insulating material is formed over a portion of the single crystal region, comprising at least a barrier layer (silicon nitride layer) (24). An oxide layer (26), such as silicon dioxide, can also be provided between the silicon nitride I (24) and the first layer of silicon (18).

A second layer (32) of silicon of n-conductivity type is then deposited over the single crystal silicon and polysilicon regions of the first layer. The deposition of this second layer of silicon forms polysilicon on the polysilicon region (22) in the first layer and monocrystalline silicon on the monocrystalline silicon region (20) in the first layer. Silicon is formed. This silicon second
The layer (32) is deposited by selective epitaxial techniques such that some of the monocrystalline material also forms lateral overgrowth (29) over some of the elements (30) and (
An exposed region (31) is left on the surface of the silicon nitride layer (24) of 30). An oxide layer (42) is formed on the second layer (32) by high pressure thermal oxidation. Open hole (2
9) The portion of thermal oxide covering the wall narrows the opening and reduces the width of the exposed area of the silicon nitride layer (24). after that,
The exposed area of the element (30) is removed through the narrowed aperture (44), exposing a portion of the single crystal area of the first layer of silicon.

The n-conductivity type region (54) is located in the exposed portion of the single crystal region (
50) to form the emitter of the transistor. A region of single crystal material (21
) essentially forms the base, and the mesa part (14) forms the collector of the transistor.

The emitter is formed by conventional techniques such as depositing a region of undoped polysilicon into an opening, implanting an n-type dopant, and annealing to diffuse the dopant into the single crystal region. a monocrystalline region ( adjacent to the essential base (21) and the insulating element (30)
20, 34) and the polycrystalline region (22, 36) become the external base region. Metal contacts are formed to contact the extrinsic base, collector and polysilicon emitter to complete the transistor.

As mentioned above, according to the invention, the window for forming the emitter region is formed by selective epitaxial growth of semiconductor material. Selective growth here refers to the fact that the silicon grows uniformly along the surface of the silicon, and that the silicon also overgrows some of the insulating elements. Selective epitaxial techniques are preferably used with growth conditions that result in equal growth rates in both the vertical and horizontal directions of the overgrown region. This overgrowth is the desired emitter.
The width of the stripe is controlled and stopped to form. A high pressure thermal oxide layer is deposited over the selective epitaxial layer to separate the polysilicon emitter from the extrinsic base region, but this oxide layer has the effect of further reducing the width of the emitter stripes. Forming the emitter window in this manner provides essential base and emitter self-alignment. Very good reproducibility is obtained by adjusting the dimensions of the emitter window by selective epitaxial growth and by realigning the window with thermal oxide spacers.

Because the external base is completely single crystal, it has low resistance and can be formed thinner than conventionally required for polysilicon external bases, reducing the depth of the emitter window and reducing emitter resistance. . Furthermore, the resistance of the polysilicon extrinsic base can be further reduced by forming a silicide. An oxide spacer separates the emitter and extrinsic base.

E. EXAMPLE Referring to FIG. 2, a transistor structure 10 includes a single crystal silicon substrate 12 having a mesa 14 surrounded by an isolation region (ROX) 16. The mesa portion is doped with a first conductivity type dopant. Although the illustrated embodiment relates to npn) transistors, it will be clear that the method of the invention can also be used to form pnp) transistors. Mesa 14 is typically lightly n-doped by conventional diffusion or implantation techniques. Region 16 is a commonly known buried oxide region. A non-selective epitaxial layer 18 of semiconductor material 'F4 (silicon) is grown on the substrate 12 by conventional epitaxial growth techniques. The silicon grows as a single crystal in a region 20 above the single crystal mesa 14 and as polysilicon in a region 22 above the buried oxide region 16. In the figure, the broken line indicates the boundary between the single crystal region and the polycrystal region. Layer 18 is typically p-doped to an extent of about 2×10 cm 2 ”. Doping of layer 18 can be done simultaneously with the epitaxial growth, or dopants can be implanted into the layer later. Layer 18 The typical thickness of
00 to 1000 people.

An insulating layer is then formed over layer 18 by depositing at least a layer of barrier layer (typically silicon nitride). In the exemplary embodiment shown in FIG.
A thermal oxide layer 26, typically silicon dioxide, is first deposited over layer 18, followed by a silicon nitride barrier layer 24.
is deposited on oxide layer 26. Oxide layer 26 typically has a thickness on the order of 40A and nitride layer 24 has a thickness on the order of 300A. The nitride layer can be deposited by low pressure chemical vapor deposition techniques (LPGVD).

As shown in factor 4, a resist 28 is placed on the nitride layer 24 on the mesa portion 14. The width of resist 28 defines the insulating elements of the final structure and must be greater than the width of the desired emitter stripes. Then use reactive ion etching to etch the nitride barrier layer,
The oxide layer 26 is exposed. We now selectively implant boron (B) very shallowly through the oxide layer 26 to heavily dope regions of the silicon layer 18 on either side of the nitride layer 24, typically on the order of 2×10190 m−3. It's okay. This additional doping reduces the resistance of those regions that become the extrinsic base regions of the transistors. Through the nitride element 24, the p+ region 21 becomes essentially the base region.

As shown in FIG. 5, the oxide layer 26 is then removed by a wet etch, such as dilute HF, and the resist 26 is removed.
8 is removed to clean the surface of the structure. Insulating element 30 is thus formed from the remaining portions of layers 24 and 36. Thereafter, selective epitaxy is used to grow a second layer 32 of heavily doped p-type silicon. This silicon is also selectively overgrown on a portion of the insulating element 30. The second layer 32 of silicon has a single crystal region 34 on the single crystal region 20 of 118 and (g) FFJ 18.
A polysilicon region 36 is grown on the polysilicon region 22 . Regions 34 and 36 are regions 34 and 36 of high concentration p of layer 18.
Together with the type region, it forms the external base of the transistor.

The growth of layer 3.2 initially grows to the thickness of the insulating element 30,
An overgrowth aperture 29 is then formed on the element 30, leaving an exposed portion 31 of the upper surface 33 on the element 30. In a preferred embodiment, selective epitaxial techniques provide uniform growth in the vertical and horizontal directions.

It is known that equal growth rates are achieved when the pattern formed by elements 30 is parallel to the (100) crystal axis. Furthermore, the growth rate in the (100) direction is (11
It is known that the growth rate in the 0) direction is much higher than that in the 0) direction. Thus, after reaching the upper surface 33 of the insulating element 30, the layer 32 grows laterally along the surface 33 by the same amount as it grows vertically above the surface 33. Thus, even if the lithographic pattern defined by the insulating element 30 is circular in shape, a rectangular emitter aperture can be provided. An example of a selective epitaxial technique that can be used is the article by Ginsberg et al., "Reduced pressure Low-temperature selective epitaxy using SiC+4” (Ginsber 8. et al.,
Lower TemperatureSelectiv
e Epitaxy Using 5iC14at R
Educated Pressure, Extended
Abstracts, Qth Conference
nceon Chemical Vapor Depo
location, Electro, Chemical
Society, Honolulu, Hawaii
, 1937, pp. 991.992).

The selective epitaxial layer 32 typically has a thickness of 1000 to
It is grown to a thickness of 3000^. Preferably, the growth temperature is maintained at or below 875°C. Techniques have now emerged in which epitaxial growth is performed at temperatures below 7.0°C.

For the practice of the invention, it is preferred that the growth temperature is kept as low as possible to avoid damage to the essential base formed under the insulating element 3o. Selective epitaxial growth of layer 32 is performed under growth conditions that can be easily controlled to provide apertures 29 with a desired width.

The width of the aperture 29 can be less than 0.5 microns;
It can also be made as small as 0°1 micron.

A thermal oxide layer 42 is deposited over selective epitaxial layer 32, as shown in FIG. Layer 42 separates the extrinsic base region from the subsequently formed polysilicon emitter. Furthermore, the width of the opening 29 in FIG.
Decreased by adhesion of 2. Preferably, layer 42 is formed by a high pressure, low temperature oxidation process. Layer 42 is element 3
It is in contact with a part of the exposed portion 31 of 0. This thermal oxidation is 7
Preferably, it is carried out at a temperature between 00°C and 800°C to prevent outward diffusion of the essential base region 21. During this thermal oxidation, the nitride layer 24 acts as an oxidation barrier and prevents oxidation of the essential base region 21. Thermal oxide layer 26
serves to relieve the strain that exists when nitride layer 24 is in direct contact with layer 18. Oxide layer 42 is typically grown to a thickness of 1000-2000 Å. Layer 42 forms a fairly narrow aperture 44, creating a narrower exposed area.

Thereafter, as shown in FIG.
6 is selectively etched, typically by a dry etch process, and a portion of the oxide layer 26 is removed by a wet etch process, thereby forming a trench 43 in the insulating element 30 and removing the monocrystalline essence. A region 50 adjacent the target base region 21 is exposed. The thermal oxide layer 42 within the aperture 44 is also slightly removed so that the layer 42 and the side edges of the insulating element 30 are aligned substantially coplanar.

As shown in FIG. 1, a conductive element of polysilicon is deposited within trench 43 and aperture 44 and in contact with region 50;
Extending over layer 42. The polysilicon region 52 is implanted with a dopant, typically arsenic, and heated to diffuse an n-type conductivity region 54 into the single crystal region 21 to form an emitter. Essential base area 21
A portion of this diffuses into the single crystal region 14 in approximately the same amount. A metal contact 56 is formed on element 52 as an emitter contact, and contacts 58 and 60 are deposited as base and contacts, respectively.

Note that the collector reach-through shown in broken lines, to which the collector contact 60 is connected, is formed by forming a trench in the epitaxial layer 36, 22 and the isolation region 16, and depositing heavily n-type doped silicon in the trench. Therefore, it can be formed using normal techniques.

As shown in FIG. 8, in an alternative embodiment, the isolation region 62 is formed after the formation of the emitter windows 43,44.

In FIG. 8, like elements are designated with the same numbers as in FIGS. 1-7. After defining the emitter window as described above, a trench 64 is formed and filled with a suitable isolation material.
A separation region 62 is formed. Since substrate 12 is initially provided with no isolation regions, layers 18 and 32 are completely monocrystalline. Isolation region 62 can be filled with any insulating material such as oxide or nitride or polysilicon. An emitter region is then formed using typical diffusion techniques.

According to the method of the invention, emitter region 54 and essential base region 21 are formed in self-alignment by using selective epitaxy to define emitter windows 43,44. Additionally, the vertical spacer provided by layer 42 between extrinsic base region 34 and emitter region 54 prevents tunneling between the high concentration, outdiffused emitter 54 and extrinsic base. Therefore, optical lithography is no longer required to define the emitter window. Optical lithography is only used to define the patterns that form the insulating elements on which selective epitaxial layers are grown. By selective epitaxy, 0.
Small emitter stripe widths are obtained, less than 5 microns and in the submicron range on the order of 0.1 micron. This width can be further reduced by depositing an insulating layer.

Therefore, there is no need to conventionally etch the polysilicon to implant the base and emitter.

Effects of the F0 Invention In accordance with the present invention, a bipolar emitter window is defined by the use of selective epitaxial growth of silicon.
A method of manufacturing a transistor is provided.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the final stage of a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 2-7 are cross-sectional views showing various steps according to the invention up to the final step of FIG. 1. FIG. 8 is a cross-sectional view of a bipolar transistor according to an alternative embodiment of the present invention at one stage of manufacture. 10...Structure, 12...Substrate, 14...
Mesa portion, 16... Isolation region, 18... Epitaxial layer, 20. 34... Single crystal region, 21...
・Essential base region, 22.36... polycrystalline region,
24... Barrier (nitride) layer, 26... Thermal oxide layer, 28... Resist, 30... Insulating element,
31... exposed portion of surface, 32... selective epitaxial layer, 33... surface of insulating element, 42...
- Thermal oxide layer, 43... trench, 44... opening, 46... exposed portion, 52... conductive polysilicon region, 54... emitter region, 56... ...Emitter contact, 58...Base contact, 60...Collector contact Applicant International Business Machines Corporation Agent Patent attorney Hitoshi Yamamoto (1 other person) Final part of the present invention Stage 1 Fig. 46-・Enjoying the exposed part 50-Sound β Fig. 7 21-・This gx head 28-L list only Fig. 4 12-Fig. 8

Claims (1)

[Claims] (a) providing a substrate of a semiconductor material of a first conductivity type, a portion of which becomes a collector region, and (b) providing a second semiconductor material, a portion of which becomes an essential base region, on the substrate; (c) forming an element of insulating material over a portion of the first layer so as to cover the region that will be the essential base region; d) depositing a second layer of semiconductor material of the second conductivity type over the first layer, and depositing a portion of the second layer laterally over a portion of the top surface of the element; (e) forming a layer of insulating material on the second layer to narrow the aperture; and (f) removing exposed areas of the element through the aperture. (g) forming an emitter region of the first conductivity type in the first layer through the opening;
Method of manufacturing transistors.