JPH0241214B2 - - Google Patents
Info
- Publication number
- JPH0241214B2 JPH0241214B2 JP7789384A JP7789384A JPH0241214B2 JP H0241214 B2 JPH0241214 B2 JP H0241214B2 JP 7789384 A JP7789384 A JP 7789384A JP 7789384 A JP7789384 A JP 7789384A JP H0241214 B2 JPH0241214 B2 JP H0241214B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- word
- code
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Dc Digital Transmission (AREA)
Description
〔発明の属する技術分野〕
本発明は、デイジタル通信に用いられる１ワー
ドｍビツトの符号を１ワードｎビツトの符号に変
換するmB−nB符号変換装置の受信符号誤り検出
回路に関する。
〔従来技術の説明〕
従来例誤り検出回路は、第２図に示すようにデ
イスパリテイ情報デコード回路２１、前ステート
記憶回路２３、ステート遷移比較回路２２および
誤り情報送出フリツプフロツプ２４、オアゲート
２５，２６の構成要素が必要であり、それぞれの
構成要素を部品として構成されるので、回路規模
が大きくなる欠点があつた。
ここで、5B−6B符号変換装置に用いられる従
来例符号誤り検出回路を図および表に基づいて説
明する。
第１図は、5B−6B符号変換装置にかかわるデ
イスパリテイ情報の遷移を示す状態遷移図で、符
号ｄはデイスパリテイ情報の値を、符号Ｘはデイ
スパリテイ情報が使用規則に該当しない状態を示
し、この図で符号１１，１２および１３の状態遷
移が行われるときに符号誤りがあるものとして検
定される。すなわち、図のステート１でデイスパ
リテイ「＋２」の符号が受信されたとき、また、
ステート２でデイスパリテイ「−２」の符号が受
信されたとき、さらに、符号変換装置を支配する
符号変換表の使用規則に該当しない符号が受信さ
れたときで、６ビツト符号は符号誤りを有するも
のとして検定される。
第２図は、従来例符号誤り検出回路の構成を示
すブロツク構成図で、入力端子２７および２８の
それぞれには、第１表に示す四種類のデイスパリ
テイ情報の内のいずれか一つのデイスパリテイ情
報に対応る二進符号を構成する「２」ビツトのビ
ツト信号のそれぞれが入力される。
[Technical Field to Which the Invention Pertains] The present invention relates to a received code error detection circuit for an mB-nB code converter that converts a code of m bits per word to a code of n bits per word used in digital communication. [Description of Prior Art] As shown in FIG. 2, the conventional error detection circuit includes a disparity information decoding circuit 21, a previous state storage circuit 23, a state transition comparison circuit 22, an error information sending flip-flop 24, and OR gates 25 and 26. Since multiple elements are required and each component is constructed as a component, it has the disadvantage of increasing the circuit scale. Here, a conventional code error detection circuit used in a 5B-6B code conversion device will be explained based on figures and tables. FIG. 1 is a state transition diagram showing the transition of disparity information related to the 5B-6B code conversion device, where the code d indicates the value of the disparity information, and the code X indicates a state in which the disparity information does not correspond to the usage rules. When the state transitions of codes 11, 12, and 13 occur, it is determined that there is a code error. That is, when the sign of disparity "+2" is received in state 1 in the figure,
When a code with a disparity of "-2" is received in state 2, and when a code that does not comply with the usage rules of the code conversion table that governs the code conversion device is received, and the 6-bit code has a code error. It is verified as. FIG. 2 is a block diagram showing the configuration of a conventional code error detection circuit. Each of the input terminals 27 and 28 is connected to one of the four types of disparity information shown in Table 1. Each of the "2" bit signals constituting the corresponding binary code is input.
本発明は、前述の欠点を除去するもので、簡単
な回路にて実現させたmB−nB符号変換装置の符
号誤り検出回路を提供することを目的とする。
〔発明の特徴〕
本発明は、複数個のデイスクリート部品に代
り、ROMを用いて回路構成したもので、ROM
回路を備え、このROM回路のアドレス入力に
は、入力する１ワードｍビツト（ｍは複数）の情
報信号を１ワードｎビツト（ｎはｍと異なる複
数）の情報信号に変換する符号変換装置にかかわ
る復号化回路から、現在時に入力する上記１ワー
ドｎビツトの情報信号にかかわるデイスパリテイ
情報と、このデイスパリテイ情報にかかわる情報
信号より１ワード分過去時の情報信号に基づいて
生成されたステート情報とを生成する回路が接続
され、上記ROM回路には、上記アドレス入力に
対応する上記現在時に入力する１ワードｎビツト
の情報信号にかかわるステート情報と、上記アド
レス入力に対応した上記現在時に入力する１ワー
ドｎビツトの情報信号にかかわる誤り情報とがあ
らかじめ書込まれたことを特徴とする。
〔実施例による説明〕
以下、本発明実施例回路を図に基づいて説明す
る。第３図は、この実施例回路の構成を示すブロ
ツク構成図である。
まず、この実施例回路の構成を第３図に基づい
て説明する。この実施例回路は、入力端子３３お
よび３４と、入力ラツチ回路３１と、ROM３２
と、出力端子３５とで構成され、入力端子３３は
入力ラツチ回路３１の第一の入力に接続され、入
力端子３４は入力ラツチ回路３１の第二の入力に
接続され、ROM３２の第二の出力は入力ラツチ
回路３１の第三の入力に接続され、入力ラツチ回
路３１の第一の出力はROM３２の第一の入力に
接続され、入力ラツチ回路３１の第二の出力は
ROM３２の第二の入力に接続され、入力ラツチ
回路３１の第三の出力はROM３２の第三の入力
に接続され、ROM３２の第一の出力は出力端子
３５に接続される。
次に、この実施例装置の動作を第３図および第
２表に基づいて説明する。ここで、第１表に示す
デイスパリテイ情報に対応する二進符号の一方を
信号A0とし、他方を信号A1とし、ROM３２の出
力信号のうち符号誤り情報の有無を示すバイナリ
信号を信号D0とし、ステート情報を示すバイナ
リ信号を信号D1とし、信号D0の値が「０」のと
きは誤りなし状態に、信号D0の値が「１」のと
きは誤りあり状態に、また、信号D1の値が「１」
のときはステート１に、信号D1の値が「０」の
ときはステート２にそれぞれ対応するものとす
る。また、信号A2は前ワードのステート情報D1
である。
ROM３２のアドレス信号として信号A0、信号
A1および信号A2の組合せ信号を与えられると、
信号D0および信号D1が出力される。この出力D1
は第２表に示すように前述の従来例装置で生成さ
れる出力と一致する。
The present invention eliminates the above-mentioned drawbacks, and aims to provide a code error detection circuit for an mB-nB code converter that is implemented using a simple circuit. [Features of the Invention] The present invention uses a ROM instead of a plurality of discrete components.
The address input of this ROM circuit is equipped with a code conversion device that converts the input information signal of 1 word m bits (m is plural) into the information signal of 1 word n bits (n is a plurality different from m). From the related decoding circuit, disparity information related to the above-mentioned 1 word n bits information signal input at the present time and state information generated based on an information signal at a time one word past the information signal related to this disparity information are obtained. A generating circuit is connected, and the ROM circuit contains state information related to a 1-word n-bit information signal input at the current time corresponding to the address input, and 1 word input at the current time corresponding to the address input. It is characterized in that error information regarding an n-bit information signal is written in advance. [Description by Example] Hereinafter, a circuit according to an example of the present invention will be described based on the drawings. FIG. 3 is a block configuration diagram showing the configuration of this embodiment circuit. First, the configuration of this embodiment circuit will be explained based on FIG. This embodiment circuit includes input terminals 33 and 34, an input latch circuit 31, and a ROM 32.
and an output terminal 35, the input terminal 33 is connected to the first input of the input latch circuit 31, the input terminal 34 is connected to the second input of the input latch circuit 31, and the second output of the ROM 32 is connected to the third input of the input latch circuit 31, the first output of the input latch circuit 31 is connected to the first input of the ROM 32, and the second output of the input latch circuit 31 is connected to the third input of the input latch circuit 31.
A third output of the input latch circuit 31 is connected to a third input of the ROM 32, and a first output of the ROM 32 is connected to an output terminal 35. Next, the operation of this embodiment device will be explained based on FIG. 3 and Table 2. Here, one of the binary codes corresponding to the disparity information shown in Table 1 is designated as signal A 0 , the other as signal A 1 , and the binary signal indicating the presence or absence of code error information among the output signals of the ROM 32 is designated as signal D 0. The binary signal indicating the state information is set as signal D1 , and when the value of signal D0 is "0", it is in an error-free state, and when the value of signal D0 is "1", it is in an error state, and The value of signal D 1 is "1"
When the value of signal D1 is "0", it corresponds to state 1, and when the value of signal D1 is "0", it corresponds to state 2. Also, signal A 2 is state information D 1 of the previous word.
It is. Signal A 0 as address signal of ROM32, signal
Given the combined signal of A 1 and signal A 2 ,
Signal D 0 and signal D 1 are output. This output D 1
As shown in Table 2, corresponds to the output generated by the conventional device described above.
本発明は、以上説明したように、デイスクリー
ト部品で構成される従来例装置に比較して、構造
が簡単であるので、装置のコストを低減する効果
がある。
As explained above, the present invention has a simpler structure than the conventional device composed of discrete parts, and therefore has the effect of reducing the cost of the device.
第１図は５ビツト−６ビツト符号変換装置にか
かわるデイスパリテイ情報の状態遷移図。第２図
は従来例回路の構成を示すブロツク構成図。第３
図は本発明実施例回路の構成を示すブロツク構成
図。
１……使用規則にない符号受信時の出力、２…
…デイスパリテイ「＋２」符号受信時の出力、３
……デイスパリテイ「−２」符号受信時の出力、
４……デイスパリテイ「０」符号受信時の出力、
２１……デイスパリテイ情報デコード回路、２２
……ステート遷移比較回路、２３……前ステート
記憶回路、２４……誤り符号送出フリツプフロツ
プ、２５，２６……オアゲート、２７，２８，３
３，３４……入力端子、２９，３５……出力端
子、３１……入力ラツチ回路、３２……ROM。
FIG. 1 is a state transition diagram of disparity information related to a 5-bit to 6-bit code conversion device. FIG. 2 is a block diagram showing the configuration of a conventional circuit. Third
The figure is a block configuration diagram showing the configuration of a circuit according to an embodiment of the present invention. 1...Output when receiving a code that is not in the usage rules, 2...
...Output when receiving disparity "+2" code, 3
...Output when receiving disparity "-2" code,
4...Output when receiving disparity "0" code,
21...disparity information decoding circuit, 22
... State transition comparison circuit, 23 ... Previous state storage circuit, 24 ... Error code sending flip-flop, 25, 26 ... OR gate, 27, 28, 3
3, 34...Input terminal, 29, 35...Output terminal, 31...Input latch circuit, 32...ROM.
Claims (1)
信号を１ワードｎビツト（ｎはｍと異なる複数）
の情報信号に変換する符号変換装置にかかわる復
号化回路から、現在時に入力する上記１ワードｎ
ビツトの情報信号にかかわるデイスパリテイ情報
と、 このデイスパリテイ情報にかかわる情報信号よ
り１ワード分過去時の情報信号に基づいて生成さ
れたステート情報とを生成する回路が接続され、 上記ROM回路には、 上記アドレス入力に対応する上記現在時に入力
する１ワードｎビツトの情報信号にかかわるステ
ート情報と、 上記アドレス入力に対応した上記現在時に入力
する１ワードｎビツトの情報信号にかかわる誤り
情報と があらかじめ書込まれたことを特徴とする符号誤
り検出回路。[Scope of Claims] 1. A ROM circuit is provided, and the address input of this ROM circuit is such that an information signal of 1 word and m bits (m is a plurality) is inputted as 1 word and n bits (n is a plurality different from m).
The above-mentioned one word n input at the current time from the decoding circuit related to the code conversion device that converts it into an information signal.
A circuit that generates disparity information related to a bit information signal and state information generated based on an information signal at a time one word past the information signal related to this disparity information is connected to the ROM circuit. State information related to the 1-word n-bit information signal input at the current time corresponding to the address input, and error information related to the 1-word n-bit information signal input at the above-mentioned current time corresponding to the address input are written in advance. A code error detection circuit characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7789384A JPS60220628A (en) | 1984-04-18 | 1984-04-18 | Code error detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7789384A JPS60220628A (en) | 1984-04-18 | 1984-04-18 | Code error detecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60220628A JPS60220628A (en) | 1985-11-05 |
| JPH0241214B2 true JPH0241214B2 (en) | 1990-09-17 |
Family
ID=13646754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7789384A Granted JPS60220628A (en) | 1984-04-18 | 1984-04-18 | Code error detecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60220628A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0253328A (en) * | 1988-08-18 | 1990-02-22 | Nec Corp | Coding circuit |
-
1984
- 1984-04-18 JP JP7789384A patent/JPS60220628A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60220628A (en) | 1985-11-05 |
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