JPH0241265B2 - - Google Patents
Info
- Publication number
- JPH0241265B2 JPH0241265B2 JP57023069A JP2306982A JPH0241265B2 JP H0241265 B2 JPH0241265 B2 JP H0241265B2 JP 57023069 A JP57023069 A JP 57023069A JP 2306982 A JP2306982 A JP 2306982A JP H0241265 B2 JPH0241265 B2 JP H0241265B2
- Authority
- JP
- Japan
- Prior art keywords
- harmonic
- harmonic voltage
- current
- load
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/40—Arrangements for reducing harmonics
Landscapes
- Supply And Distribution Of Alternating Current (AREA)
Description
【発明の詳細な説明】
本発明は高調波電圧歪抑制装置に関し、特に電
力系統に用いられる高調波電圧歪抑制装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a harmonic voltage distortion suppressing device, and particularly to a harmonic voltage distortion suppressing device used in a power system.
従来の高調波電圧歪抑制装置を第１図と共に説
明する。 A conventional harmonic voltage distortion suppressing device will be explained with reference to FIG.
上位電源系統１０から供給される負荷電流によ
り負荷１２を駆動する際に、前記負荷電流に含ま
れる高調波分ILhを検出し、この高調波分を打消
すような補償電流IRhを流して高調波を抑制する
高調波電圧歪抑制装置１４を図示されない電源ト
ランスの近傍に配置し、負荷に発生した高調波分
の影響が他の系統に現われないようにしていた。
しかしながら、このような従来の高調波電圧歪抑
制方法によれば、電源側に高調波分Ishが含まれ
ている時には、負荷に対する高調波の影響を取り
除くことができなかつた。 When driving the load 12 with a load current supplied from the upper power supply system 10, a harmonic component I Lh included in the load current is detected, and a compensation current I Rh is passed to cancel this harmonic component. A harmonic voltage distortion suppressor 14 that suppresses harmonics is placed near a power transformer (not shown) to prevent the effects of harmonics generated in the load from appearing on other systems.
However, according to such a conventional harmonic voltage distortion suppression method, when the harmonic component I sh is included on the power supply side, it is not possible to eliminate the influence of the harmonic on the load.
本発明は上記の点に鑑みてなされたもので、負
荷に含まれる高調波分のみならず電源電圧に含ま
れる高調波分も保償することを簡単な回路構成で
可能にした高調波電圧歪抑制装置を提供すること
を目的とし、この目的を達成するために本発明で
は電源系統に含まれる高調波電圧を検出し、この
高調波電圧に対応した電流値と負荷に含まれる電
流値とをつき合せこの偏差出力を零にするような
補償電流を供給する供給手段を設けたことを特徴
としている。 The present invention has been made in view of the above points, and is a harmonic voltage distortion that makes it possible to guarantee not only the harmonics contained in the load but also the harmonics contained in the power supply voltage with a simple circuit configuration. An object of the present invention is to provide a suppression device, and to achieve this object, the present invention detects a harmonic voltage included in a power supply system, and detects a current value corresponding to this harmonic voltage and a current value included in a load. The present invention is characterized in that it is provided with a supply means for supplying a compensation current that makes this deviation output zero.
以下本発明の一実施例を添付された図面と共に
説明する。 An embodiment of the present invention will be described below with reference to the attached drawings.
第２図は本発明に係る高調波電圧歪抑制装置の
基本構成図であり第１図と同一符号は同一物を示
している。 FIG. 2 is a basic configuration diagram of a harmonic voltage distortion suppressing device according to the present invention, and the same reference numerals as in FIG. 1 indicate the same parts.
上位電源系統１０の例えばＡ点に高調波電圧
eshが存在するとき、その影響が下位の系統に接
続された負荷１２に影響を与えないように、また
負荷の非直線性に由来する高調波電流の影響が上
位の系統に現われないようにする為に第２図に示
されるように高調波電圧歪抑制装置１４を接続す
る。この場合高調波電圧歪抑制装置１４から補償
電流IRhをＢ点での高調波電圧Vhが零になるよう
に流す。また検出点ＡとＢに電源トランスまたは
系統の回路定数から決定される等価的なインピー
ダンス（Zs）１６が介挿されている。 For example, harmonic voltage at point A of the upper power supply system 10
e sh exists, so that its influence does not affect the load 12 connected to the lower system, and so that the influence of harmonic currents originating from load nonlinearity does not appear on the upper system. In order to do this, a harmonic voltage distortion suppressor 14 is connected as shown in FIG. In this case, the compensation current I Rh is caused to flow from the harmonic voltage distortion suppressing device 14 so that the harmonic voltage V h at point B becomes zero. Further, an equivalent impedance (Z s ) 16 determined from the circuit constants of the power transformer or the system is inserted at the detection points A and B.
上記の様に構成することにより、負荷電流高調
波ILhを検出して次式で示されるように補償電流
IRhを流すことにより、点Ｂでの高調波電圧Vhを
零にすることができる。 By configuring as above, the load current harmonic I Lh is detected and the compensation current is calculated as shown in the following equation.
By flowing I Rh , the harmonic voltage V h at point B can be made zero.
IRh＝ILh−esh／Zs ………(1) (1)式のように補償電流を流すことによつて、 Ish＝ILh−IRh＝esh／Ze ………(2) となり、 Vh＝esh−ZsIsh＝esh−esh＝０ ………(3) となるので、Vhは零となる。 I Rh = I Lh −e sh /Z s ………(1) By flowing the compensation current as shown in equation (1), I sh = I Lh −I Rh = e sh /Z e ……… (2) and V h = e sh −Z s I sh = e sh −e sh = 0 (3) Therefore, V h becomes zero.
第３図は第２図の基本構成に基づく本発明の一
実施例を示すブロツク図である。第１図、第２図
と同一符号は同一物を示す。１８は電源トランス
で例えば１次側の電圧ｅ＝60KVを２次側の電圧
Ｖ＝6KVに変換しており、PTはこの電源トラン
ス１８の１次側の電圧を検出するための変成器、
２０はこの変成器１８により検出された電圧信号
から基本波を取除いて高調波電圧eshを得るバン
ド・リジエクトフイルタ、２２は積分器で高調波
電圧eshを積分して１／Ｌ∫eshdtを求める。ここでＬ
は電源トランス１８の漏れインピーダンスであ
る。CTは負荷電流ILを検知するための変流器で、
２４はこの負荷電流ILに含まれる基本波を取除い
て高調波電流Ishを求めるバンド・リジエクト・
フイルタ、２６はつき合せ回路で高調波電流ILh
と積分された高調波電圧１／Ｌ∫eshdtとをつき合わせ
るために設けられている。２８は制御回路、３０
はゲート回路で、３２はPWMインバータで
GTO32g及び直流リアクトルＬから構成され、ゲ
ート回路３０からのゲート信号によりGTO32gを
スイツチングさせて任意の電流波出力を得る。３
４は搬送波除去フイルタで、PWMインバータ３
２の出力からPWM周波数の電流を取除いて保償
電流IRhを得るために設けられている。 FIG. 3 is a block diagram showing an embodiment of the present invention based on the basic configuration of FIG. 2. The same reference numerals as in FIGS. 1 and 2 indicate the same parts. 18 is a power transformer which converts, for example, the primary side voltage e=60KV to the secondary side voltage V=6KV, and PT is a transformer for detecting the voltage on the primary side of this power transformer 18;
20 is a band reject filter that removes the fundamental wave from the voltage signal detected by this transformer 18 to obtain a harmonic voltage e sh , and 22 is an integrator that integrates the harmonic voltage e sh to obtain 1/L∫ Find e shdt . Here, L is the leakage impedance of the power transformer 18. CT is a current transformer for detecting the load current I L.
24 is a band reject circuit that removes the fundamental wave contained in this load current I L to obtain the harmonic current I sh .
Filter, 26 is a matching circuit and harmonic current I Lh
This is provided to match the integrated harmonic voltage 1/L∫e shdt . 28 is a control circuit, 30
is a gate circuit, and 32 is a PWM inverter.
It is composed of a GTO 32g and a DC reactor L, and the GTO 32g is switched by a gate signal from a gate circuit 30 to obtain an arbitrary current wave output. 3
4 is a carrier removal filter, and PWM inverter 3
This is provided to remove the PWM frequency current from the output of 2 to obtain the guaranteed current I Rh .
本発明の一実施例は上記のように構成されてい
るため第２図の基本構成図に示されるように高調
波電圧Vhを零にするように保償電流IRh＝ILh−
esh／Zsを流して、負荷に原因する高調波のみならず
電源に原因する高調波分を十分に抑制できる。 Since one embodiment of the present invention is configured as described above, the guarantee current I Rh =I Lh − is set so that the harmonic voltage V h becomes zero as shown in the basic configuration diagram of FIG.
By flowing e sh /Z s , it is possible to sufficiently suppress not only the harmonics caused by the load but also the harmonics caused by the power supply.
従つて、負荷の非線形に依つて生ずる高調波電
流の影響が他の系統に現われない。また他の系統
が発生する高調波電圧の影響が負荷に現われな
い。 Therefore, the influence of harmonic current caused by load nonlinearity does not appear on other systems. Furthermore, the load is not affected by harmonic voltages generated by other systems.
以上説明してきたように本発明に係る高調波電
圧歪抑制装置は、電源系統に含まれる高調波電圧
を検出し、この高調波電圧に対応した電流値と前
記負荷に含まれる電流値とをつき合せ該偏差出力
を零にするような補償電流を供給する供給手段を
設けたので、負荷に原因する高調波分のみなら
ず、電源側から混入する他の系統に原因する高調
波分も十分抑制できる。 As explained above, the harmonic voltage distortion suppressing device according to the present invention detects the harmonic voltage included in the power supply system, and compares the current value corresponding to this harmonic voltage with the current value included in the load. Since a supply means is provided to supply a compensation current that reduces the deviation output to zero, not only harmonics caused by the load but also harmonics caused by other systems mixed in from the power supply side are sufficiently suppressed. can.
第１図は従来の高調波電圧歪抑制装置の概略構
成を示すブロツク図、第２図は本発明に係る高調
波電圧歪抑制装置の基本構成を示すブロツク図、
第３図は第２図に示される基本構成に基づく本発
明の一実施例のブロツク図である。
１０……上位電源系統、１２……負荷、１４…
…高調波電圧歪抑制装置、１８……電源トラン
ス、２０，２４……バンドリジエクトフイルタ、
２２……積分器、２６……つき合せ回路、２８…
…制御回路、３０……ゲート回路、３２……
PWMインバータ、３４……搬送波除去フイル
タ。
FIG. 1 is a block diagram showing a schematic configuration of a conventional harmonic voltage distortion suppressing device, and FIG. 2 is a block diagram showing a basic configuration of a harmonic voltage distortion suppressing device according to the present invention.
FIG. 3 is a block diagram of an embodiment of the present invention based on the basic configuration shown in FIG. 10... Upper power supply system, 12... Load, 14...
...Harmonic voltage distortion suppressor, 18...Power transformer, 20, 24...Band redirect filter,
22... Integrator, 26... Matching circuit, 28...
...Control circuit, 30...Gate circuit, 32...
PWM inverter, 34...carrier removal filter.
Claims (1)
をインピーダンスZsを介して接続し、下位系統側
に補償電流IRhを流す高調波抑制装置を設けると
ともに、該高調波抑制装置に上位系統の高調波電
圧eshと下位系統の負荷電流高調波ILhを検出して
入力し、この高調波抑制装置に下位系統の高調波
電圧が零となるような補償電流IRh（IRh＝ILh−
esh／Zs）を流すようにしたことを特徴とする高
調波電圧歪抑制装置。 ２ 前記高調波抑制装置は、前記検出した高調波
電圧と負荷電流高調波に応じて作動するスイツチ
ング素子を含むPWMインバータ回路と、該
PWMインバータ回路の出力からPWM周波数の
電流を取除いて補償電流を得るためのフイルタと
からなることを特徴とする特許請求の範囲第１項
記載の高調波電圧歪抑制装置。[Claims] 1. A higher-order system and a lower-order system to which a load is connected are connected via an impedance Z s , and a harmonic suppression device is provided to flow a compensation current I Rh into the lower-order system, and The harmonic voltage e sh of the upper system and the load current harmonic I Lh of the lower system are detected and input to the wave suppression device, and the harmonic suppression device is supplied with a compensation current I that makes the harmonic voltage of the lower system zero. Rh (I Rh = I Lh −
A harmonic voltage distortion suppressing device characterized in that a harmonic voltage distortion suppressing device is configured to flow a voltage (e sh /Z s ). 2. The harmonic suppression device includes a PWM inverter circuit including a switching element that operates according to the detected harmonic voltage and load current harmonic;
2. The harmonic voltage distortion suppressing device according to claim 1, further comprising a filter for removing a PWM frequency current from the output of the PWM inverter circuit to obtain a compensation current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57023069A JPS58141630A (en) | 1982-02-16 | 1982-02-16 | Harmonic wave voltage distortion suppression controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57023069A JPS58141630A (en) | 1982-02-16 | 1982-02-16 | Harmonic wave voltage distortion suppression controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58141630A JPS58141630A (en) | 1983-08-23 |
| JPH0241265B2 true JPH0241265B2 (en) | 1990-09-17 |
Family
ID=12100109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57023069A Granted JPS58141630A (en) | 1982-02-16 | 1982-02-16 | Harmonic wave voltage distortion suppression controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58141630A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5610040A (en) * | 1979-06-30 | 1981-02-02 | Tokyo Shibaura Electric Co | Power regulator |
-
1982
- 1982-02-16 JP JP57023069A patent/JPS58141630A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58141630A (en) | 1983-08-23 |
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