JPH0241758B2 - - Google Patents

Description

[Detailed description of the invention]

(Field of the Invention) The present invention controls the timbre or volume based on performance volume data according to the type of musical instrument, and generates richer rhythmic sounds by bringing the instrument sound characteristics in response to the strength of the performance closer to the actual ones. This invention relates to an automatic rhythm performance device. (Background of the Invention) A conventional automatic rhythm performance device has a pattern memory that stores rhythm pattern data and corresponding volume data such as accents or percussion instrument sounds, and automatically plays percussion instrument sounds according to rhythm selection. What occurs is known. By the way, in such devices, regardless of the type of instrument, the volume of multiple musical instrument sounds is uniformly controlled simply by inputted volume data, and the rhythm sound generated depends on the strength and weakness of the performance for each instrument. Compared to actual musical instrument sounds, which have different pronunciation volumes and tones, the sounds were poor. (Object of the Invention) In view of the above-mentioned problems with the conventional type, the present invention is based on the concept of correcting the tone volume for each instrument (sound source) based on common level data indicating the strength and weakness of the performance in an automatic rhythm performance device. The aim is to obtain richer rhythmic sounds that are closer to actual musical instrument sounds. [Structure of the Invention] In order to achieve this object, an automatic rhythm performance device according to the present invention provides sound generation timing data for each rhythm sound and a level control mode having a plurality of levels that are commonly set for a plurality of types of the rhythm sounds. a pattern memory storing rhythm pattern data including common level data representing a desired stage of the sound generation timing data; and a pattern memory storing rhythm pattern data including common level data representing a desired stage of the sound generation timing data; and a level storage means for storing correction data for each of the rhythm sounds corresponding to the common level data, and the rhythm sound and readout generation means read out data from the level storage means. The present invention is characterized in that the musical tone parameters of the rhythm tones to be generated are corrected and controlled based on the corrected data. Volume or timbre is typical of musical sound parameters of rhythm sounds that are corrected and controlled based on correction data. (Description of Embodiments) FIG. 1 shows the overall configuration of an electronic musical instrument equipped with an automatic rhythm performance device according to an embodiment of the present invention. In the figure, the keyboard 10 is an upper keyboard UK (not shown);
It is equipped with a lower keyboard LK, a pedal keyboard PK, etc., and generates key information according to the keys pressed by the performer. The panel 12 includes a musical tone selection operator 14 and a rhythm operator 16, and generates operator information such as musical tone selection and rhythm type selection. The rhythm operator 16 includes, for example, rhythm selection switches 18 and 18 for selecting the type of rhythm such as march and waltz, as shown in FIG.
-1, 18-2, . . . , a start/stop switch 20 for controlling the start and stop of the rhythm, a total volume 22 for adjusting the rhythm volume, a tempo setter 24 for setting the rhythm tempo, and the like. In addition, total volume 22 and tempo setter 2
Reference numeral 4 is composed of a multi-stage digital switch or a combination of a variable resistor and an A/D converter, and generates digital data of the volume and tempo according to the set position. The keyboard 10 and panel 12 are connected to a bus line 34 consisting of an address bus ADB and a data bus DB via a key switch interface 30 and a panel interface 32, respectively, and this bus line 34 is connected to a central processing unit (CPU). ) 36 are connected. The CPU 36 is composed of a microprocessor having a program counter PC, an A register A, an X register , takes in the generated key information and operator information, and controls the overall operation of the electronic musical instrument shown in FIG. 1, such as by generating various control data regarding keyboard sounds and rhythm sounds based on this information. The bus line 34 further includes a program memory 38, a working memory 40, a rhythm pattern memory 42, and a pattern start address memory 4.
4 and each interface for sending control data generated by the CPU 36 are connected. The program memory 38 is a read-on memory ROM in which a control program for the CPU 36 is stored. The working memory 40 is composed of a random access memory RAM, and a part thereof is provided with a working area for temporarily storing various data generated when the CPU 36 executes a control program. This working area is composed of registers, flags, etc. as shown in Table 1.

[Table] In the following explanation, the contents of each register, etc. and these registers, etc. are indicated by the same symbol. For example, both the beat number register and the contents of the beat number register are expressed in HKPE. Tempo data register TEMPO, volume data register TOTLEV and rhythm type register
RHYPTN stores operator information for the tempo setter 24, total volume 22, and rhythm selection switch 18 of the rhythm operator 16, respectively. The rhythm pattern memory 42 is comprised of a ROM, and as shown in FIG. 3a, rhythm patterns for each rhythm type, such as march and waltz, are stored. Each of these rhythm patterns
As shown in the enlarged view of Figure b, the instrument group number IGN stored at the first address, event data EVT at each timing within a beat stored at each subsequent address, and beat end data BE (16
It consists of "OD" (hereinafter referred to as $OD) data in decimal notation) and return data RTN ($OF). Here, the musical instrument group is a musical instrument group formed by extracting eight types of musical instrument sounds for generating rhythm sounds such as marches and waltzes, each corresponding to the number of sound source formation channels in the rhythm sound generation circuit 60, which will be described later. The instruments that form each group are assigned to each sound source forming channel. In this embodiment, 0 is used to generate rhythm sounds for march and tango, 1 is used for waltz and ballad, and so on.
There are eight instrument groups corresponding to instrument group numbers IGN of ~7. For example, if the value of instrument group number IGN is 1, channel 0 is the top cymbal for each channel represented by channel numbers 0 to 7. Eight types of instruments are assigned to generate the rhythm sounds of waltzes and ballads: TCY, channel 1 is a high pitch HH, channel 5 is a snare drum brush roll SDB, and so on. By introducing the concept of musical instrument groups, this electronic musical instrument can generate autorhythms consisting of up to eight types of instrument sounds for each rhythm type. Incidentally, in conventional autorhythm performance devices, the number of sound source forming channels for all types of rhythm sounds is eight, for example, and the number of instruments used for one rhythm sound is usually less than the number of sound source forming channels. However, according to this embodiment, it is also easy to form rhythm sounds using, for example, eight desired types of musical instrument sounds for each rhythm type, and any number of musical instrument sounds for all rhythm types. This electronic musical instrument has 1 beat, or 1/12 of a beat.
The rhythm pattern memory 42 contains event data EVT that includes the musical tone elements of the musical tone to be generated as data, and the number of beats at which the event occurs and the 12 rhythms. Stored in order of intra-beat timing. This event data EVT is shown in Figure 3c.
As shown in the figure, using 2 bytes of memory where 1 byte is 8 bits, the lower 4 bits (4th to 1st bits) of the 1st byte contain the in-beat timing HTIM when the event occurs, and the 7th to 5th bits contain the sound source. The formation channel number CHN, the upper 4 bits (8th to 5th bits) of the 2nd byte contain pitch control data PIT of the instrument sound generated at the timing within that beat, and the 3rd byte.
~1 bit stores common level data LEV indicating whether the strength of the musical instrument performance, that is, the level of the musical instrument sound generated at each timing, is from fortissimo ff to pianissimo pp on the musical score. The beat end data BE indicates the boundary between beats, and the return data RTN indicates the end of the rhythm pattern. Also, these beat end data BE and return data RTN are the previous event data EVT.
Indicates that there is no event within a beat after the intra-beat timing shown in . The pattern start address memory 44 stores the rhythm pattern start address of each rhythm sound in the rhythm pattern memory 42, and is a conversion ROM that outputs the start address of the corresponding rhythm pattern memory when the content RHYPTN of the rhythm type register is input. The keyboard sound forming circuit 48 inputs data related to keyboard sounds from the CPU 36 via the keyboard sound interface 50, forms keyboard sound data in a plurality of (for example, 10) time-division channels, and time-divisions these data. Outputs multiplexed keyboard sound signals. This keyboard sound signal is acoustically mixed with data for all channels together with a rhythm sound signal RTS, which will be described later, in a D/A converter 52 and converted into an analog musical sound signal. pronounced as The rhythm interface 58 receives pitch control data PIT and common level data that the CPU 36 reads out from the rhythm pattern memory 42 and outputs.
The event data EVT such as LEV and the sound command signal NKON indicating that the event data EVT has been read out can be temporarily stored, and the stored data can be stored in response to a command from the CPU 36 as shown in FIG. The data is converted into bit serial data OPC and transferred to the rhythm sound generation circuit 60. Note that the most significant bit of this data OPC is always “1” as the available signal Av.
When a transfer of data OPC occurs in the interrupt processing of the CPU 36, continuous input data of “0” changes to “1”, so even if all bits of data OPC are “0”, it is not possible to determine whether or not data is transferred. can. The rhythm interface 58 also includes a tempo counter that operates according to tempo data set in the tempo setter 22, and interrupts data transfer processing to the CPU 36 when a rhythm start signal is input from the CPU 36 and every beat thereafter. The tempo of the automatic rhythm performance in this electronic appliance is set by generating an interrupt signal RINT to cause the automatic rhythm performance to be performed. The rhythm sound generation circuit 60 receives OPC and TLV input from the CPU 36 via the rhythm interface 58 and panel data interface 62.
Based on data related to rhythm sounds such as PAN and PAN, musical instrument sound signals are generated for each of eight time-division channels, and these musical instrument sound signals are time-division multiplexed to output a rhythm sound signal RTS. Note that this rhythm sound generation circuit 60 includes a musical tone characteristic control circuit that controls musical tone characteristics such as volume or timbre based on common level data LEV for each type of musical instrument. This rhythm sound signal RTS is D/
The signal is converted into sound via the A converter 52, the amplifier 54, and the speaker 56. The panel data interface 62 is a CPU
36 is the total volume 2 of the rhythm controller 16
The volume data TOTLEV (or data obtained by logarithmically converting this data) read from the rhythm pattern memory 42 and the instrument group number IGN read from the rhythm pattern memory 42 by the CPU 36 are converted into serial data TLV and PAN as shown in FIG. The signal is sent to the generation circuit 60. (Explanation of the operation of the electronic musical instrument shown in FIG. 1) Next, the operation of the electronic musical instrument shown in FIG. 1 will be explained with reference to the flowcharts shown in FIGS. 5 to 9. Referring to FIG. 5, when the power is turned on to this electronic musical instrument,
The CPU 36 starts operating according to the control program stored in the program memory 38 (step 100). In step 101, the entire circuit is initialized by clearing the registers, flags, etc. included in the CPU 36, working memory 40, rhythm interface 58, etc., and in step 102, changes are made by operating the controls on the keyboard 10 and panel 12. Detects a hot controller and its controller information. This detection includes, for example, the control information for each control and the registers TEMPO, TOTLEV,
If the exclusive OR with the previous control information stored in RHYPTN or the like is not 0, it can be detected as a change in control information, that is, an event has occurred. In this step 102, the operation information is also detected when the start/stop switch 24 is pressed to the start or stop side.
Also, total volume 22 or tempo setter 2
The operator information No. 4 represents, for example, the positions of these volumes as digital data of 16 steps from 0 to 15, and this data is stored as it is in the total volume register TOTLEV and the autorhythm tempo register TEMPO. In step 103, it is determined whether or not an event was detected in step 102, and if there is no event, the process returns to step 102 to further detect an event.
If an event is detected, processing is performed in accordance with the type of event detected in subsequent steps. The event detected in step 102 is the keyboard 10
If the musical tone is changed by pressing or releasing a key or pressing the musical tone selection operator 14, the process advances to step 110. In step 110, each key data or tone selection data is processed and output to the key tone interface 50. The key tone interface 50 further sends these data to the keyboard tone forming circuit 48. The above event starts/stop switch 2
If the rhythm starts with 0, step 120
Rhythm run flag in working memory 40
After setting RHYRUN, synchronize the rhythm tempo in step 121. When the event at step 102 is a rhythm stop by the start/stop switch 20, the pattern change flag PCHNGF and rhythm run flag shown in Table 1 are set at step 130.
Clear rhythm-related registers and flags such as RHYRUN. When the event at step 102 is a tempo change by the tempo setter 24, the step
140, the tempo data TEMPO is loaded into the rhythm interface 58. In the rhythm interface 58, this tempo data determines the pitch of one beat, that is, the tempo at which the CPU 36 reads out the rhythm pattern by interrupt processing INTRPT200, which will be described later. When the event in step 102 is a change in rhythm volume by the total volume 22,
At step 150, the volume data TOTLEV is output to the panel data interface 62. The panel data interface 62 uses this volume data.
TOTLEV is converted into a serial volume control signal TLV and output to the rhythm sound generation circuit 60. If the event in step 102 is a change in rhythm type RHYPTN due to the rhythm selection switch 26 being pressed, rhythm set processing RHYSET is performed.
160 (FIG. 6). In other words, in step 161, the beat number in the beat number register is set to timing by referring to the contents of the in-measure timing counter TIMING.
If TIMING is 0-11, set it to 1, if it is 12-23, set it to 2,
If it is 24-35, set it to 3, and if it is 36-47, set it to 4. This is to ensure that the rhythm after the change continues at the same timing as before the change, so at step 165, the same number of beats,
Pattern pointer RHPNT is placed at the address where rhythm pattern data of the same beat timing is stored.
Used when setting. At step 162, the rhythm run flag RHYRUN is checked again, and if the rhythm is progressing, the beat end flag is set at step 163.
Clear RHHEND. This is the beat end flag
This is because if RHHEND remains set, reading of event data will be skipped if there is event data after the rhythm time change timing after the change (see step 401). Even in the rhythm after the change, if there is no event data after the timing of the change, the beat end flag RHHEND is set when setting the rhythm pointer RHPNT.
If it is determined in step 162 that the rhythm is stopped, the beat end flag RHHEND has already been cleared in step 130 during rhythm stop processing, so step 165 is skipped and the process proceeds to step 166. In step 164, the contents of the rhythm type register are
The head pattern address memory 44 is addressed with RHYPTN to read the head address of the selected rhythm type and stored in the rhythm pattern head address register RHYROM in the working memory 40. In step 165, rhythm pattern memory 4
2 is sequentially read from the first address at the address indicated by the sum of the first address RHYROM and the content RHPNT of the pattern pointer, and the number of read beat end data BE and intra-beat timing HTIM are read out sequentially from the first address.
, beat count HKPE and intra-bar timing
Compare pattern pointer with TIMING
Set RHPNT. This set allows the start address RHYROM and the contents of the pattern pointer to be
The address indicated by the sum with PHPNT is one where the number of end data BE is 1 less than the value of beat number HKPE, and the intra-beat timing HTIM is the intra-measure timing.
It will now show the first address that is equal to or greater than TIMING. At step 166, the musical instrument group number IGN stored at the leading address of the rhythm pattern memory 42 is read out and output to the panel data interface 62. The panel data interface 62 converts the musical instrument group number IGN into a serial signal PAN and sends it to the rhythm sound generation circuit 60. In step 167, it is determined whether the rhythm type RHYPTN is 3 beats or 4 beats.If it is 3 beats, step 168 is in effect, and if it is 4 beats, in step 169, the maximum timing register TMPMAX is set to the maximum number of timings within one measure. 35 and 47 are memorized. After detecting an event in step 102, after completing the processing in steps 110 to 169 for each type of event, the process returns to step 102 to detect a new event. As mentioned above, in the electronic musical instrument shown in Figure 1,
An interrupt is sent from the rhythm interface 58 to the CPU 36 when the start/stop switch 20 is turned to the start position and when the tempo counter included in the rhythm interface 58 counts 1/12 of a beat, that is, 1 beat, according to the set tempo. The signal RINT is sent out. Therefore CPU36
is the 7th beat at the start of the rhythm and every subsequent beat.
The interrupt process INTRPT200 shown in the figure is executed. First, in step 201, each register, program counter, etc. are saved so that the original state can be restored after the interrupt processing is completed, and then rhythm sound generation data output processing RHIRQ 210 shown in FIG. 8 is executed. Referring to FIG. 8, in step 211, the rhythm run flag RHYRUN is checked to determine whether or not a rhythm is in progress. If this judgment is "no", that is, the rhythm has stopped, there is no need to output the rhythm sound data, so restore each register saved in step 260 (Figure 7) and immediately cancel the interrupt. Return to original routine. If the rhythm is in progress at step 211, a data output subroutine RHYCNV400 (FIG. 9) is executed. Referring to FIG. 9, the beat end flag RHHEND is checked in step 401, and if it is the beat end, there is no event data at the intra-beat timing TMPCNT until the beat goes up, so the original routine (see FIG. 8) is continued. ). If it is not the beat end, the content of the rhythm pointer RHPNT is set in the Y register in step 402, and then in step 403.
and 404 to start rhythm pattern address
The rhythm pattern memory 42 is addressed by the sum of RHYROM and the content Y of the Y register (that is, the content RHPNT of the rhythm pointer), and the channel number CHN and intra-beat timing data HTIM of the first byte of the event data EVT shown in FIG.
is read and stored in the A register and the X register. Next, in step 405, the contents of the A register and $OF
The logical sum is calculated and only the lower 4 bits of the intra-beat timing data HTIM are left in the contents of the A register, and in step 406 it is determined whether or not this intra-beat timing data HTIM matches the timing indicated by the tempo counter TMPCNT. . If these timings match in step 406, this data is valid for the current timing TMPCNT to be processed, so the contents of the Y register as a pointer are incremented in step 407, and the event data EVT is incremented in step 408. The pitch control data PIT and common level data LEV of the second byte are read and stored in the A register. A at step 409
The pitch control data PIT and common level data LEV stored in the register and the channel number CHN stored in the X register are output to the rhythm interface 62. In step 410, the next event data is
In order to read the EVT, the contents of the Y register as a rhythm pattern memory pointer are further incremented. In steps 411 to 414, the steps 403 to 406 are repeated, and in steps 407 to 414, the intrabeat timing data that is the same as the current intrabeat timing TMPCNT is
Read all event data with HTIM. If there is no event data having the same intra-beat timing in step 406 or 414, proceed to step 415, and determine whether the timing data left in the A register in step 405 or 413 is greater than or equal to $OD, that is, whether it is the end of the beat or return. do. In-beat timing is always $OO~$OB
The content A of the A register becomes greater than $OD when the beat end data BE ($OD) or the return data RTN ($OF) is read. Therefore, if the above judgment shows that A register≧$OD, then in step 416, it is judged whether or not to return. If it is a return ($OF), clear the Y register at step 417, and if it is a beat end ($OD), clear the Y register at step 417.
Skip 417 and proceed to step 48. step
418 sets the beat end flag RHHEND,
In step 419, the contents of the Y register are incremented, and in step 420, the contents Y of the Y register are set in the rhythm pointer RHPNT, and the process returns to the original routine (step 240 in FIG. 8). When the return data RTN is detected by the processing in steps 417, 419 and 420 described above, the rhythm pointer RHPNT is set to 1, and when the beat end data BE is detected, the rhythm pointer RHPNT is set to the beat end data in step 419. This indicates the address next to the address where BE was stored. If it is determined at step 415 that it is not a beat end or return, the process advances to step 420, where the rhythm pointer is
After the address at which the intra-beat timing that does not match the timing TMPCNT is read is stored in RHPNT, step 240 of the routine in FIG.
Return to Referring to FIG. 8, in step 240, a data transfer command is sent to the rhythm interface 58. Then, the rhythm interface 58 sends the 10-bit serial data OPC, which includes the pitch control data PIT and the common level data LEV, inputted and stored in step 409, to the rhythm sound generation circuit 60. In step 241, the intra-beat timing counter
TMPCNT is stepped, and in step 242 it is determined whether the beat has exceeded. If it is determined in step 242 that the beat has exceeded, then in step 243 the in-measure timing counter TIMING is incremented. When the beat is over, there is a possibility that the measure is over, so
Next, in step 244, it is determined whether the overbeat in step 243 is over the measure or not based on whether the content TIMING of the in-measure timing counter has reached the maximum timing TMPMAX. If the bar is over,
In step 245, the beat end flag RHHEND is reset, and in step 246, the intra-bar timing counter TIMING and the intra-beat timing counter are reset.
After resetting TMPCNT, follow the steps in Figure 7.
Return to 260. If the beat is over, but not over the bar, the beat end flag RHHEND is reset in step 247, the within-beat timing counter TEMPCNC is reset in step 248, and then the process returns to step 260 in FIG. If the judgment in step 242 is that the beat is not over, the within-beat timing counter TIMING is executed in step 249.
After incrementing , step 260 in Figure 7
Return to Referring to FIG. 7, step 211 of rhythm sound generation data output processing RHIRQ210 (FIG. 8),
After returning from steps 246, 248, and 249, in step 260, the program counter, each register, etc. that were saved for this interrupt processing INTRPT are restored, and the state before the interrupt is returned. Next, the detailed operation of the rhythm interface 58 will be described with reference to FIG. This interface 58 includes a decoder 70, a tempo register 72,
It includes a rhythm sound source data register 74, a channel register 76, a function register 78, etc., and is driven by timing signals φ, ChT, etc. from a timing signal generator (not shown). When the address signal that the CPU 36 (FIG. 1) sends to the address bus is one of the tempo register 72, rhythm sound source data register 74, channel register 76, and function register 78, the decoder 70 responds to that address signal. Load signals are sent to each register 72 to 78 accordingly.
Send RHYDEC1 to 4. Therefore, the data sent by the CPU 36 via the data bus DB is
6 is provided and stored in the register addressed. The CPU 36 (Figure 1) uses the tempo setter 24
(Figure 2) is operated, this tempo setter 2
In addition to importing the tempo data TEMPO from 4, the tempo register 7 of the rhythm interface 58
2 and sends tempo data TEMPO. The decoder 70 supplies the decode output RHYDEC1 to the load terminal of the tempo register 72 based on the address data specifying the tempo register 72 sent to the address bus ADB, and therefore,
The tempo register 72 stores the data being sent to the data bus DB at this time, that is, the tempo data.
Remember TEMPO. This tempo data is the tempo
It is supplied to the ROM80. ROM80 is data
TEMPO as counter 82 preset data PSD
is converted into and supplied to the counter 82. The counter 82 receives preset data when the load terminal LD, that is, the output of the OR circuit 84 is "1".
After the PSD is preset, the clock signal φ of a constant frequency output from the clock generation circuit 86 is counted, and when an overflow occurs, "1" is output to the carrier output terminal Co. This output is OR
It is input to a first input terminal of circuit 84, and counter 82 will be preset each time it overflows. That is, when the overflow value is N and the preset value is M, this counter 82 divides the frequency of the clock signal φ by 1/(NM) to set the tempo set in the tempo setter 24 (FIG. 2). generates the output of Note that this counter 82 may be one that presets the clock signal φ, down-counts it, outputs "1" to the terminal Co when the count value is 0, and divides the frequency of the clock signal φ by 1/M. A well-known variable frequency division type counter may also be used. The output of the OR circuit 84 is further sent to the CPU 36 as an interrupt signal RINT.
The CPU 36 starts an interrupt processing operation to be described later at the same time as the counter 82 is preset. Further, the output of the clock generation circuit 86 is supplied to the first input terminal of another OR circuit 88. Since the output of the OR circuit 88 is connected to the reset terminal of the clock generating circuit 86, the clock generating circuit 86 is reset immediately after generating an output, and therefore generates a short pulse width clock signal φ. As mentioned above, when the CPU 36 (FIG. 1) detects that the start/stop switch 20 (FIG. 2) is pressed to the start side, it addresses the function register 78 and sets the data bus DB.
Sends a start command ($01) to Then, the decoder 70 sends the decoded output RHYDEC4 to the function register 7 based on the address data.
8 load terminal. Therefore, the function register 78 contains a start command ($01).
is loaded and the register 78 is set to “1” for a short time.
It is automatically cleared after sending the pulse as the start signal START = “1”. This start signal START="1" is supplied to the second input terminals of OR circuits 84 and 88, respectively. Therefore, the OR circuit 84
At the same time as presetting, an interrupt signal is sent to the CPU 36.
RINT is supplied, and OR circuit 88 resets clock generation circuit 86. Therefore, these counter 82, clock generation circuit 86 and CPU 36
Their rhythm tempos are synchronized. After the automatic rhythm performance starts, the CPU36 (Figure 1)
The event data EVT read from the rhythm pattern memory 42 (FIG. 1) by 3-bit common level data LEV and 4-bit pitch control data PIT is supplied to the rhythm sound source data register 74 as 7-bit data. and the channel number CHN is stored in the channel register 76. The channel counter 90 repeatedly counts the channel timing signal ChT from 0 to 7, and the comparator 92 compares the output of the channel counter 90 with the channel number CHN output from the channel register 74, and determines a match when they match. The signal EQ is supplied to the first input terminal of the AND circuit 94. Flip-flop 96 is channel register 7
It is set by the load signal RHYDEC3 of 6 and reset by the output CHEQ="1" of the AND circuit 94.
After being loaded, the signal “1” is applied to the second input terminal of the AND circuit 94 until the signal CHEQ="1" is generated.
otherwise, "0" is supplied. Therefore, the AND circuit 94 outputs the channel matching signal CHEQ="1" as the AND of the output EQ of the comparator 92 and the set output Q of the flip-flop 96 at the channel timing only once after loading the channel number CHN. Output as a differential waveform of the leading edge of signal ChT. This signal CHEQ="1" is supplied to the selector 98 as a signal SB for selecting input B.
Therefore, the 8-stage 7-bit shift register 100 is supplied with 3-bit common level data LEV and 4-bit pitch control data PIT from the rhythm sound source data register 74. The shift register 100 takes in these data in response to the timing signal ChT and sequentially shifts them. In addition, the signal CHEQ is set to the sound generation command signal NKON=“1” and the 8-stage 1-bit shift register 102
is supplied via the OR circuit 104 and taken in according to the timing signal ChT. Note that the shift registers 100, 102 and the channel counter 90 are all operated synchronously by the same channel timing signal ChT, and as a result, the shift registers 100, 10
2 includes data LEV and PIT and signal
NKON="1" is written to the stage corresponding to the channel number CHN stored in the channel register 76. While the signal CHEQ is “0”, the selector 98 has
A signal SA for selecting input A is supplied via inverter 106. Therefore, the output of the shift register 100 is fed back to the input side via the selector 98, and the data LEV and PIT written to the shift register 100 are stored cyclically.
Similarly, the signal NKON="1" written in the shift register 102 is also stored cyclically via the AND circuit 108 and the OR circuit 104. As described above, the CPU 36 (Fig. 1) reads the event data EVT from the rhythm pattern memory 42 (Fig. 1), then addresses the function register 78 and issues a transfer command ($20) to the data bus DB. Send out. Then, the decoder 70 decodes output based on the address data.
RHYDEC4 is applied to the load terminal of function register 78, so that function register 78 is loaded with the transfer command ($20). The register 78 is a shift register 100, 10.
All the data and signals for 8 channels stored in 2 are converted to serial data OPC, and the time transfer signal TRANS = "1" for about 8 channel timing signals ChT is output, and the rest is automatically clear. Signal TRANS="1" indicates P/S converter 110
is supplied to the transfer terminal S of. P/S converter 110
, its parallel data input terminals P1 to P9
The data and signals stored in the shift registers 100 and 102 for each of the eight channels are sequentially input to each channel in synchronization with the channel timing signal ChT, and the load terminal LD
The channel timing signal ChT is input to. Then, when the function register 78 generates the transfer signal TRANS="1", this P/
The S converter 110 receives the channel timing signal.
Data from P1 to P9 is captured for each channel during the period when ChT is "1", and the captured data is converted into serial data at the timing of the clock signal φ during the period when the channel timing signal ChT is "0".
It is sent to the rhythm generation circuit 60 as OPC. By repeating this operation eight times, data for all eight channels is sent out. The transfer signal TRANS="1" is also supplied as a signal "0" to the second input terminal of the AND circuit 108 via the inverter 112. For this reason,
The circulation path including the shift register 102 is cut off,
All stages of the shift register 102 are cleared. (Explanation of operation of rhythm sound generation circuit 60) FIG. 11 shows the rhythm sound generation circuit 60 (FIG. 1)
1 is a schematic block diagram for understanding the function of the
Next, the operation of the rhythm sound generation circuit 60 will be described with reference to FIG. This circuit 60 includes a rhythm control circuit 130, basic pitch, tone, and envelope data.
ROM132, sound source circuit 134, tone control circuit 1
36 and a volume control circuit 138, and operates by receiving timing signals φ, _φAB, etc. as shown in FIG. 12 from a timing signal generator (not shown). However, in FIG. 11, the timing signal φ is omitted. When the rhythm set processing is performed as described above, the rhythm control circuit 130 is supplied with the rhythm sound control signal PAN including the 3-bit musical instrument group number signal IGN from the panel data interface 62. The S/P conversion circuit 140 receives this signal.
It converts IGN into a parallel signal, adds a load signal LD, and supplies it to the musical instrument group number register 142. Therefore, the register 142 receives the instrument group number signal in response to the load signal LD.
IGN is stored and supplied to the instrument number ROM 144. The ROM 144 stores instrument name data GS corresponding to eight instruments for each instrument group.
These data are sent to the channel counter 146 that counts the 3-bit instrument group number signal IGN from the register 142 and the timing signal φ _AB .
The 3-bit count output of
The data is read from the ROM 144. For example, the value of the instrument group number signal IGN is 1.
If the rhythm type of waltz or ballad is specified, 5-bit data indicating the instrument name and top cymbal is read from the ROM 144 when the count value of the counter 146 (channel number CHN) is 0. Reading is from counter 1
As the count value of 46 changes from 1, 2, 3, . . . 7, the same process is performed for the other seven musical instrument names. Then, as the counter 146 repeats the counting operation for 8 channels (8 instruments),
Data reading from the ROM 144 is also repeated. The instrument name data GS read from this ROM 144 is the channel number of the register 148.
It is written in the stage corresponding to CHN and sent out in synchronization with the channel number CHN counted by the counter 146. When serial data OPC for eight instruments including the sound generation command signal NKON is supplied from the rhythm interface 58 (FIG. 10) to the rhythm control circuit 130, this data OPC is converted to S/P in the S/P conversion/latch circuit 150. P-converted and temporarily stored. The 3-bit common level data LEV and pitch control data PIT stored in this S/P conversion/latch circuit 150 are transmitted to the rhythm interface 5.
In response to the synchronization signal and timing signal φ _AB sent from 8 together with the data OPC, the signals are written to the stages corresponding to each channel number CHN of the register 152, and are sent out for each channel in synchronization with the counting operation of the counter 146. In addition, the sound generation command signal NKON is output when the data OPC is S/
After being stored in the P conversion/latch circuit 150, the counter 146 first records the corresponding channel number.
Sent from circuit 150 when CHN is counted. The ROM 132 stores pitch designation data PIT ₀ , tone designation data CLD, and envelope value data ENV for each instrument name. These data are sent to the ROM 132 using the 5-bit instrument name data GS from the register 148 as an address signal. It is now read out from The sound source circuit 134 generates a sine wave, triangular wave, or square wave of a frequency corresponding to the pitch, which is obtained by adding the 4-bit pitch control data PIT from the _register 152 to the 14-bit pitch specification data PIT 0 from the ROM 132 and slightly modifying the pitch control data PIT. Or generate data of a relatively simple sound source waveform such as a sawtooth wave. In the timbre control circuit 136, the timbre correction data generation circuit 154 outputs timbre correction data based on the 3-bit common level data LEV from the register 152 and the 5-bit instrument name data GS from the register 148. The timbre addition circuit 156 converts the timbre designation data CLD from the ROM 132 into the timbre correction data generation circuit 1.
The sound source waveform data from the sound source circuit 134 is subjected to, for example, FM modulation using the data corrected with the timbre correction data from 4 to change the frequency distribution of the percussion instrument sound to be generated. In the volume control circuit 138, the envelope generator constant correction ROM 158 has register 1
Volume correction data is output using instrument name data GS from register 158 and common level data LEV from register 152 as address signals. The envelope generator 160 receives the sound generation command signal NKON from the S/P conversion/latch circuit 150.
is cleared when input, and ROM1
Envelope constant ENV from 32 to ROM158
An envelope value is calculated based on the modified data according to the modified data from. The volume designation circuit 162 is, for example, the timbre addition circuit 1.
An envelope is added to the sound source waveform by multiplying the sound source waveform data from 56 with timbre added, the envelope data from the generator 160, and the volume control signal TLV stored in the S/P conversion/latch circuit 163. This also determines the volume of the percussion instrument sound. Note that the timbre correction data generation circuit 154 and envelope generator constant correction ROM 15
8 is a characteristic selected for each instrument among the multiple common level data LEV vs. timbre/volume correction amount ADJ characteristics as shown in FIG. 13 (for example, a characteristic like A or B in the graph in the same figure). It is designed to generate correction or correction data according to the following. As described above, in this rhythm sound generation circuit 60, the volume level is corrected for each musical instrument based on the common level data LEV, and the timbre is also corrected based on the common level data LEV. FIG. 14 shows a more specific circuit example of the rhythm sound generation circuit 60. Next, the detailed operation of this rhythm sound generation circuit 60 will be explained. (Operation description of a specific example of the rhythm sound generation circuit 60) The rhythm sound generation circuit 60 in FIG.
With an FM sound source, the basic formula is E(t) = A(t) sin {ωct + S・I(t) sinωmt} ...(1) However, E(t): Instrument sound waveform data (sample data) A(t): Amplitude coefficient ωc: Carrier wave Each frequency S: Feedback coefficient I(t): Modulation index ωm: Modulation wave The calculation represented by each frequency is performed six times based on the operation sequence set for each sound source type (instrument name). , various FM modulation waveforms are obtained by appropriately selecting and substituting the previous calculation results, constants, etc. as S·I(t) sinωmt and ωmt in the above equation. In this embodiment, six calculations are performed on the instantaneous value of one percussion instrument sound. For example, when creating a snare drum shot sound, snare drum brush roll sound, etc., E ₀ (t) = A ₄ (t) sin［ω ₄ t＋A ₃ (t）sin{ω ₃ t＋
A ₂ (t) sin (ω ₂ t + A ₁ ^* (t) sinω ₁ t)}] + A ₆ (t) sin (ω ₆ t + A
₅ (t) sinω ₅ t)…(2) Also, when forming claves and castanet sounds, E ₀ (t)=A ₆ (t) sin [ω ₆ t+A ₁ ^* (t) sinω ₁ t± A
₃ (t) sin {ω ₃ t + A ₂ (t) sin ω ₂ t} + A ₅ (t) sin {ω ₅ t + A ₄ (t
)sinω ₄ t}]…(3) However, A ₁ ^* (t)sinω ₁ t is a formula such as self-feedback (that is, since the previous calculation result is used, the calculation equivalent to infinite nesting can be performed). The calculations shown are performed to obtain FM modulated waveforms corresponding to various percussion instrument sound waveforms. This circuit 60 includes a rhythm control circuit 170, an arithmetic control ROM 172, an angle data calculation section 174, an amplitude coefficient calculation section 176, and an FM calculation section 178, and generates a timing signal (not shown) as in the explanatory diagram of FIG. It operates by receiving timing signals φ, _φAB, etc. as shown in FIG. 12 from the device. However, in FIG. 14, these timing signals are omitted. Note that in this rhythm sound generation circuit 60, the channel counter 180 in the rhythm control circuit 170
Eight sound source forming channels are created for _each time slot that is sequentially separated by the width of one period of the timing signal φ (hereinafter referred to as 1 bit time), corresponding to the count value (channel number CHN) that occurs at the timing of the timing signal φ AB. It is now being formed in a time-divided manner. In addition, the operation counter 182 counts the carrier output _C0 generated by the counter 180, and calculates a word number with a width of 8 bit time (hereinafter referred to as 1 word time) in which 8 channel numbers CHN from 0 to 7 are generated. Generate WDN. The rhythm sound generation circuit 60 generates a word number for each sound source forming channel corresponding to the channel number CHN.
Perform 6 calculations corresponding to WDN0 to 5, and
One waveform data is generated every word time (48 bit time, hereinafter referred to as one processing time). When the rhythm set processing is performed as described above, the rhythm control circuit 170 is supplied with the rhythm sound control signal PAN including the 3-bit musical instrument group number signal IGN from the panel data interface 62. This signal IGN is the S/P conversion circuit 1
After being converted into a parallel signal at 84, the register 18
6, and the instrument number is stored in register 186.
It is supplied to the ROM 188. The ROM 188 is addressed by the 3-bit instrument group number signal IGN from the register 186 and the 3-bit count output (channel number) of the channel counter 180 that counts the timing signal φ _AB , and is used to control the eight instruments for each instrument group. Corresponding instrument name data GS for each channel number 0
-7 are sequentially output. From the rhythm interface 58 (Figure 10), serial data for 8 instruments including sound generation instructions
When OPC is supplied to the rhythm control circuit 170,
This data OPC is S/P conversion/latch circuit 19
S/P conversion is performed at 0 and temporarily stored. Here, for the sake of simplicity, let us assume that the serial data OPC for these eight instruments includes sound generation instructions only for the snare drum brush roll SDB (channel number 5) of the aforementioned instrument group number 1.・The latch circuit 190 outputs a sound generation command signal at the timing of channel number 5.
NKON="1" is sent and channel number 0
~4 and 6~7 timings signal NKON
"0" is sent in both cases. This signal NKON is connected to selector 192 and 1
94 as a signal SA for selecting input A. Therefore, the 8-stage/5-bit shift register 196 receives 5-bit instrument name data GS from the ROM 188, and the 8-stage/7-bit shift register 198 receives 7-bit pitch data from the S/P conversion/latch circuit 190. Level control data is provided respectively. shift register 19
6 and 198 each take in the supplied data to the stage corresponding to channel number 5 in accordance with the timing signal φ _AB and sequentially shift it. After the selectors 192 and 194 supply data to the shift registers 196 and 198, respectively, the signal NKON="0" causes the selectors 192 and 194 to become in a state where they select input B, respectively.
The contents of 98 are selectors 192 and 19, respectively.
4 is stored cyclically. A 5-bit instrument name designation signal GS corresponding to each channel number sent out in a time-division manner from the shift register 196 is supplied to the arithmetic control ROM 172. The ROM 172 stores the count output (word number) of the operation counter 182 for each instrument name.
WDN) It stores six pitch specification data PIT ₀ corresponding to 0 to 5, envelope generator constant data EG, average data AVE, connection control data GC1 to GC7, and level adjust data LVAD. The data is stored in the ROM 1 using the 5-bit instrument name designation signal GS from the shift register 196 and the word number WDN from the counter 182 as address signals.
72. For example, when a signal GS representing a 5-bit snare drum brush roll SDB corresponding to channel number 5 is input from the shift register 196, the FM calculation section 178 calculates and outputs the snare drum brush roll waveform from the ROM 172 each time. Data required for PIT ₀ , EG, AVE, CG
1 to 7 and LVAD are sequentially read out according to the word number WDN counted by the counter 182. The 14-bit pitch designation data PIT ₀ from the ROM 172 is used as the 4-bit pitch control data from the shift register 198 in the adder circuit 200.
PIT has been added and some corrections have been made. For this reason, the adder 200 supplies pitch designation data, which takes into account the pitch of each note, to the phase data ROM 202 as an address signal. The ROM 202 converts this pitch designation data into angular frequency data ω. The accumulator 204 is (number of channels)×
(Number of words) = 48 arithmetic circuits included, each channel number CHN, word number for each arithmetic circuit
The angle data ωt for each WDN is calculated, and the rhythm control circuit 170 outputs the signal NKON=
When "1" is sent, the initial value π/2 is set to the six arithmetic circuits corresponding to channel number 5,
Thereafter, each time the counter 180 counts channel number 5, the word number counted by the counter 182 at that time among these six arithmetic circuits is
Angular frequency ω and signal NKON in a circuit compatible with WDN
The angle data ωt as a product of the elapsed time t after the occurrence of =“1” is calculated and supplied to the FM calculation unit 178. The amplitude coefficient calculation unit 176 obtains the amplitude coefficient (or modulation index) A(t) at each time point such as attack, decay, and release of the instrument sound to be calculated by the FM calculation unit 178 from the ROM 172 for each word for each instrument name. Generated based on envelope generator constant data EG supplied to EG. As mentioned above, the rhythm control circuit 170 receives the signal
When NKON="1" is sent, the state control circuit 20
6 is a 48-stage 2-bit shift register 20
At 8, data 01 indicating the attack state is transmitted six times at one bit time per word time, corresponding to the six steps of the corresponding channel. Therefore, the shift register 208 takes in the state data ADR=01 into the six stages corresponding to channel number 5 in accordance with the timing signal φ _AB , and
Shift sequentially. This status data ADR is supplied to selector 210. The selector 210 receives three words of rate data RATE and level data from the arithmetic control ROM 172, each indicating the slope and final level of the three states Attack A, Dekes D, and Release R.
Envelope data EG consisting of LEV ₀ is supplied, and data RATE and LEV ₀ for attack are output in accordance with state data ADR=01 supplied from the shift register 208 to the selection input terminal. Comparator 212 outputs data from selector 210.
Comparing LEV ₀ (A) and the output data (B) of the 48 stage/6 bit shift register 214, A>
Level “1” when B, level “0” when A<B
It generates a comparison signal of , and also generates an equal value signal EQ when A=B. The shift register 214 delays the output of the arithmetic circuit 216 by the same time as calculating one waveform data E(t), that is, 6 word times (1 processing time), and outputs the output of the comparator 212. The rate data RATE output from the selector 210 is sequentially added (comparison signal = "1") or subtracted (comparison signal = "0") to the output of the shift register 214 according to whether the comparison signal to be output is "1" or "0". do.
Therefore, each stage of the shift register 214 has rate data for each instrument name and word number.
The accumulated value of RATE is temporarily stored. Since A>B in the attack state, attack data is sequentially supplied from the ROM 172 to each of the 8 stages corresponding to the channel number 5 of the shift register 214 and to the 6 stages corresponding to the word number WDN. will be added. When the output (B) of the shift register 214 becomes equal to the output LEV ₀ (A) of the selector 210, the comparator 212 sends an equal value signal EQ="1" to the state control circuit 206. Therefore, the circuit 206 increments the contents of the six stages corresponding to channel number 5 of the shift register 208 and changes the data to ADR=10 indicating the next decay state. Therefore, the selector 210 sends out decay rate data and decay level data, and since A<B this time, the comparator 212 sends out a comparison signal "0".
The arithmetic circuit 216 reduces the decay rate data from the output of the shift register 214 and sends it to the shift register 214 . Next, shift register 214
The output data value (B) of selector 210 decreases.
When the decay level data value (A) outputted by The shift register 208 increments the contents of ADR=
Generate 11. Hereinafter, in the same manner, the selector 21
0 sends out release rate data and release level data, and based on the output "0" of the comparator 212, the arithmetic circuit 216 reduces the output of the shift register 214 to release rate data, and the output of the shift register 214 reduces the release rate data. When it becomes equal to the level data, the comparator 212 generates an equal value signal EQ, and the contents of the shift register 208 are further incremented to write data ADR=00 indicating a musical tone stop state. Calculated by the calculation circuit 216 as described above,
The data written in each stage of the shift register 214 is sent to the adder circuit 2 every 48 bit times.
Sent on 18th. The dynamic level characteristic ROM 220 stores amplitude coefficient (volume) or modulation coefficient (timbre) correction data corresponding to the common level data LEV for each instrument type and each of the six word numbers WDN. and level adjustment data for each calculation step
By using the common level data LEV from the LVAD and the shift register 198 as an address input, correction data ADJ based on characteristics set for each musical instrument among a plurality of types of correction characteristics as shown in FIG. 13 are read out. This correction data
ADJ is supplied to adder circuit 218. The S/P conversion/latch circuit 222 performs S/P conversion on the volume control signal TLV from the panel data interface 62 (FIG. 1), temporarily stores it, and supplies the volume control signal TLV to the addition circuit 218. It's getting old. The adder circuit 218 adds the envelope data from the shift register 214, the volume/timbre correction data ADJ from the ROM 220, and the volume control signal TLV from the S/P conversion/latch circuit 222, thereby achieving a common level. DataLEV
It becomes possible to adjust the relationship between the volume and the instrument volume for each type of instrument. Further, in this adder circuit 222, total volume control by the volume 22 is also performed. The amplitude coefficient A(t) for each musical instrument and each word number from this adding circuit 222 is FM
The signal is supplied to the calculation unit 178. The FM calculation unit 178 calculates the angle data ωt output from the angle data calculation unit 174 and the amplitude coefficient A(t) output from the amplitude coefficient calculation unit 176 according to the calculation formula specified by the connection control signals CG1 to CG7 output from the ROM 172. The musical instrument sound waveform data (sample value) E(t) is calculated using The addition circuit 228 is
Angle data calculation unit 1 with two input terminals A and B
Angle data ωt input from 74 to A terminal and feedback data G fed back from selector 230 to B terminal
(t). The sine table 232 converts the output ωt+G(t) of the adder circuit 228 into sin{ωt+G
(t)} (logarithmic value). The adder circuit 234 adds sin {ωt+G(t)} and the amplitude coefficient A(t), each input as a logarithm value, and performs logarithm-antilog conversion.
The ROM 236 converts the output of the adder circuit 234 into an antilog number and outputs calculation data E(t)=A(t) sin {ωt+G(t)} (4). The delay circuit 238 delays the output of the ROM 236, that is, the operation data E(t) by one word time in order to use it for the next operation. Gate circuits 240, 242, adder circuit 244, and delay circuit 246 constitute a dynamic memory, and when gates 240 and 242 are off, the memory contents are cleared, and when only gate 242 is on, the memory is retained as is. Gates 240 and 242
When both are on, gate 2 is added to the memory contents.
New calculation data E(t) input via 40
Add and store. Furthermore, when only the gate 240 is on, the stored content is new calculation data E(t).
Updated by. Gate 248, delay circuit 250, addition circuit 25
2 and the shifter 254 constitute a feedback circuit, and when the selector 230 selects the output F of this feedback circuit as the feedback input to the B terminal of the adder circuit 228, the FM calculation section 178 calculates infinite nesting due to self-feedback. Operates as an arithmetic circuit. The delay circuit 250 is composed of a 48-stage 10-bit shift register and outputs the calculated data with a delay of one processing time. The adder circuit 252 and the shifter 254 average the calculated data one processing time before and the calculated data at each instant to prevent hunting during self-feedback. In addition, the shifter 254 is connected to the arithmetic control ROM 172.
Based on the average data AVE output by , a shift other than one digit is also performed, and the self-feedback amount, that is, the feedback coefficient S of the calculation formula is specified. The storage unit 256 is an arithmetic control ROM1.
74 generates the gate control signal GC7 of "1" level, the calculation data E(t) is taken in, and the calculation is input from word number 0 and channel number 0 to word number 5 and channel number 7 within one processing time each. Add data for each channel. Note that the above delay circuits 238, 246, 250
The number of delay bits in addition circuits 228, 23
This is assuming that there is no time delay in the 4th grade, and in reality there is a delay in the adding circuit, etc.
The delay time is adjusted by reducing the number of delay bits. Figures 15a and 15b illustrate the calculations of equations (2) and (3), respectively. In the same figure, OP
indicates that the signature table 236 is read out and the calculation is performed, and the numbering indicates the word number on which the calculation is performed. X indicates computation by self-feedback, and + indicates addition of computed data. [Example 1] As mentioned above, when the snare drum brush roll SDB sound generation command signal NKON is input to the rhythm sound generation circuit 60, this SDB sound is generated according to equation (2).
Synthesized by FM calculation. In addition, channel 0~
Since A(t) of channels 4 and 6 to 7 is 0, and therefore the waveform data E(t) is also 0, only the time slot with channel number CHN=5 will be described below. Also, word number
The phase data ω, amplitude coefficient A(t) and calculation data E(t) at calculation step n=WDN+1 corresponding to WDN are ωn, An(t) and
Let it be expressed as En(t). In the first step, the ROM 172 generates connection control signals GC3 and GC6 of level "1" and feeds back the output F of the shifter 252 to the B terminal of the adder circuit 228. Therefore, the FM calculation section 178 is the adder circuit 2.
28, sign table 232, addition circuit 234,
A real-time closed loop reaching the adder 232 via the ROM 236, the adder circuit 252, the shifter 254, and the selector 230 is configured, and self-feedback provides E ₁ (t)=A ₁ ^* (t) sinω ₁ t=A ₁ ( t) sin(ω ₁ t＋A
′ ₁ sin (ω ₁ t+A″ ₁ sin (ω ₁ t+…)…) …(5) An operation equivalent to infinite nesting is performed. In this closed loop, the adder circuit 252 and shifter 254 perform the first step Hunting of the FM calculation section 178 during self-feedback is obtained by obtaining the average value of each instantaneous calculation data and the calculation data one processing time before, and feeding back data whose level has been adjusted by the shifter 254. Next, in the second step, the connection control signal GC
4 is set to "1" and the output Q of the delay circuit 238, that is, the operation data E ₁ (t) of one word time ago, is fed back to the B terminal of the adder circuit 228. Therefore, E ₂ (t) = A ₂ (t) sin {ω ₂ t + A ₁ ^* (t) sinω ₁ t} by substituting G(t)=E ₁ (t) in equation (4)...(6) is obtained. Similarly, in the third step, the connection control signal is
Set only GC4 to “1” and return G(t)=E ₂ (t), E ₃ (t)=A ₃ (t) sin {ω ₃ t+A ₂ (t) sin(ω ₂ t+
A ₁ ^* (t) sinω ₁ t)}...(7) is obtained, and in the fourth step, the connection control signal GC4 is similarly set to "1" and G(t)=E ₃ (t) is returned, and E ₄ (t)=A ₄ (t) sin[ω ₄ t+A ₃ (t) sin{ω ₃ t+
A ₂ (t) sin (ω ₂ t + A ₁ ^* (t) sinω ₁ (t))}] …(8) is obtained, and the connection control signal GC7 is set to “1” to convert this calculation data E ₄ (t) Accumulator 2
56. In the fifth step, the connection control signals GC1 to
Set all 7 to “0”. Therefore, the feedback data G(t)
= 0, and the calculation data E ₅ (t) is expressed as G(t) in equation (4).
=0 was assigned. E ₅ (t)=A ₅ sinω ₅ t (9) is obtained. In the sixth step, the connection control signal GC4 is set to "1" and G(t)=E ₅ (t) is returned to E ₆ (t)=A ₆ (t) sin(ω ₆ t +A ₅ (t) sinω ₅ t) ...(10), set the connection control signal GC7 to "1", input this calculated data E ₆ (t) to the accumulator 256, and input the calculated data E ₄ stored in the fourth step. (t) and added value E ₄ (t) + E ₆
(t), that is, the calculation data E ₀ (t) of equation (2) is calculated. This data E ₀ (t) is supplied to the D/A converter 52 (FIG. 1) as a rhythm sound signal RTS. The above is the waveform data calculation and volume control operation for one note at the first sound generation timing.
If multiple sound command signals are generated at the same time, or if one
Even if one or more sound production command signals are generated while a plurality of sounds are being generated, waveform data calculation and volume control operations for the plurality of sounds (up to eight sounds) are performed in the same manner. In this case, each arithmetic unit and ROM
etc. are shared in a time-division manner for each time slot corresponding to each channel number. [Example 2] Next, the case of realizing equation (3) will be explained. In the first step, as in the first step of Example 1, the connection control signal GC6 is set to "1" to obtain E ₁ (t) = A ₁ ^* (t) sinwit (11), and the connection control signal GC1 is set to "1". 1'' and stores the calculated data E ₁ (t) in a dynamic memory consisting of an adder circuit 244, a delay circuit 246, and a gate circuit 242. In the second and third steps, the fifth
Similarly to the sixth step, E ₃ (t) = A ₃ (t) sin (ω ₃ t + A ₂ (t) ω ₂ t (12) is obtained, and in this third step, the connection control signal GC1 is also obtained. Then, GC2 is set to "1" and the calculation data E ₃ (t) obtained in the third step is further added to the calculation data E ₁ (t) stored in the dynamic memory. In order to store the stored calculation data in the dynamic memory, the connection control signal GC2 is set to 1" in the second step. In the fourth and fifth steps, the procedures of the second and third steps are repeated. Then, obtain the calculation data E ₅ (t) = A ₅ (t) sin (ω ₅ t + A ₄ (t) sinω ₄ t) ...(13) and add this calculation data E ₅ (t) to the above dynamic memory. In the sixth step, the connection control signal GC5 is set to "1" and the output M of the dynamic memory is fed back to the B terminal of the adder circuit 228. Therefore, in equation (4), G(t)=E ₁ ( Calculated data by substituting t) + E ₃ (t) + E ₅ (t) E ₆ (t) = sin[ω ₆ t + A ₁ ^* (t) sinω ₁ t±A ₃ (t) s
in {ω ₃ t +A ₂ (t) sinω ₂ t} + A ₅ (t) sin {ω ₅ t + A ₄ (t
) sinω ₄ t}]...(14) In other words, equation (3) is obtained. In this sixth step, the connection control signal GC7 is further set to "1", and the above calculation data E ₆ (t) is passed through the accumulator 256 as the rhythm sound signal RTS to the D/A converter 52 (first (Figure). Note that in this rhythm sound generation circuit 60, the tone color and volume control operations are performed in a unified manner, and cannot necessarily be clearly distinguished as shown in the explanatory diagram of FIG. It may be considered that the sixth step is a volume control operation, the fourth and sixth steps of Example 1 are volume and timbre control operations, and the other steps of Examples 1 and 2 are timbre control operations. In this embodiment, only the instrument name is read from the ROM 188, but in addition, balance data BAL indicating whether the instrument is noise-based or drum-based, and a speaker that distinguishes whether the instrument's sounding speaker is the center or left. Channel data CHA etc. can also be read out. The balance data BAL is used, for example, to set the balance between noise-based instruments and drum-based instruments by adding a balance volume to the panel 12 and combining it with noise-based volume data or drum-based volume data from the balance volume. . As described above, according to the present invention, musical sound parameters such as the volume and timbre of rhythm sounds (instrumental sounds) are corrected and controlled based on common level data, and the amount of correction of these musical sound parameters is adjusted for each rhythm sound (each instrument sound). Since it is set to , it is not necessary to have detailed volume data and timbre data for each rhythm sound, and the amount of memory for pattern storage is small, resulting in extremely high memory efficiency. In addition, it is possible to finely control each type of rhythm sound source, making it possible to make changes in musical sound characteristics such as volume and timbre due to the strength of the performance closer to those of an actual musical instrument performance, making it possible to create richer rhythm sounds. can occur.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electronic musical instrument equipped with an automatic rhythm playing device according to one embodiment of the present invention, and FIG.
The figure shows the arrangement of rhythm controls on the panel of the musical instrument shown in FIG. 1, FIG. 3 shows the format of data stored in the rhythm pattern memory of the electronic musical instrument shown in FIG. 1, and FIG. FIG. 5 is a flow chart for explaining the operation of the electronic musical instrument shown in FIG. 1; FIG. 6 is a flow chart showing a subroutine for rhythm set processing; FIG. 7 is a flowchart showing interrupt processing;
FIG. 8 is a flowchart showing a subroutine of rhythm sound generation data output processing, and FIG. 9 is a flowchart showing a subroutine of data output processing.
10 is a detailed block diagram of the rhythm interface in FIG. 1, FIG. 11 is a block diagram for explaining the operation of the rhythm sound generation circuit in FIG. 1, and FIG. 12 is a detailed block diagram of the rhythm interface in FIG. A diagram showing a time chart of a timing signal for operating a rhythm sound generation circuit, FIG. 13 is a graph representing common level data versus timbre/volume correction characteristics in this invention, and FIG. A more specific block diagram of the sound generation circuit, Figure 15, shows the FM in the circuit of Figure 14.
FIG. 2 is a calculation processing chart of the calculation unit. 36...CPU, 42...Rhythm pattern memory,
60... Rhythm sound generation circuit, 130... Rhythm control circuit, 132... Basic pitch/tone/envelope data ROM, 134... Sound source circuit, 136... Tone control circuit, 138... Volume control circuit, 154... Tone correction data generation circuit, 156 ...Envelope generator constant correction ROM, 170...Rhythm control circuit, 172...Arithmetic control ROM, 174...Angle data calculation section, 176...Amplitude coefficient calculation section, 178...
FM calculation section, 220...Dynamic level characteristics
ROM.

Claims (1)

[Scope of Claims] 1. Sound generation timing data for each of a plurality of types of rhythm tones, and common level data representing a desired level among a plurality of level control modes commonly set for the plurality of types of rhythm tones. a pattern memory storing rhythm pattern data including; a rhythm sound reading generation means for reading out the pattern memory at a predetermined tempo according to the sound generation timing data and generating a plurality of rhythm sounds based on the rhythm pattern data; level storage means for storing correction data for each of the rhythm sounds corresponding to the common level data; An automatic rhythm performance device characterized by correcting and controlling musical sound parameters of rhythm sounds. 2. The automatic rhythm performance device according to claim 1, wherein the musical sound parameter of the rhythm sound that is corrected and controlled by the correction data is volume or timbre.