JPH0242732A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To form, with good reproducibility, a bipolar transistor having an emitter of a prescribed impurity concentration by a method wherein a selective epitaxial silicon layer doped at a high concentration is used as the emitter. CONSTITUTION:An epitaxial silicon layer 8 doped with, e.g., an n-type impurity is formed on a silicon substrate 1 which is exposed inside an opening corresponding to an emitter region. The n-type epitaxial silicon layer 8 forms a p-n junction to a p-type base region 2, and constitutes an emitter. Then, a wiring part 9 composed of, e.g., an aluminum thin film connected to the epitaxial silicon layer 8 is formed. That is to say, a base layer thickness can be controlled by an implantation condition of an impurity for a base and a heat-treatment condition for activation; it can be maintained at a prescribed value with good reproducibility irrespective of an emitter area.

Description

[Detailed Description of the Invention] [Summary] Regarding a bipolar transistor having a fine base and emitter or an integrated circuit thereof, the present invention aims to reproducibly (make it possible to form) a bipolar transistor having a fine emitter with a predetermined impurity concentration.

a base region formed on a semiconductor substrate; an insulating layer formed on the semiconductor substrate and having an opening corresponding to a predetermined region in the base region; and an impurity at a predetermined concentration on the semiconductor substrate exposed in the opening. The structure includes an emitter made of a semiconductor layer epitaxially grown including:

[Industrial application field]

The present invention relates to a bipolar transistor having a fine base and emitter or an integrated circuit thereof, and particularly to the structure and method of forming the emitter.

[Conventional technology]

2. Description of the Related Art As semiconductor devices become faster, elements such as transistors are being miniaturized. For example, in increasing the speed of a bipolar transistor, the speed can be increased by reducing carrier transit time and base-collector junction capacitance. For this purpose, the base layer is made thin. Along with the so-called shallow base, there is a need to reduce the area of the base and emitter regions.

Along with the above-mentioned shallow base formation, it becomes difficult to form an emitter by thermally diffusing or ion-implanting impurities at a predetermined concentration directly into the base layer. A method to solve this problem is to form a polycrystalline silicon layer in the emitter formation region, ion-implant impurities to a predetermined depth of this polycrystalline silicon layer, and then implant the impurities into the emitter region by thermal diffusion. has been done.

[Problem to be solved by the invention]

FIGS. 3(a) and 3(bl) are sectional views of essential parts for explaining the above method. 2 is formed on the silicon substrate 1.

A glabellar insulating layer 3 having an opening corresponding to the base region 2 is formed, and a base extraction electrode 4 made of polycrystalline silicon and connected to the base region 2 through the opening is formed on the first interlayer insulating layer 3. There is. Furthermore, a second interlayer insulating layer 5 covering the base extraction electrode 4 is formed.
An opening corresponding to the emitter region 6 is provided in the interlayer insulating layer 5 . Then, it was connected to the base region 2 through this opening. Emitter/vine electrode 7 made of polycrystalline silicon
is provided.

The emitter region 6 is formed by implanting ions 9, for example, arsenic ions (As), which have been ion-implanted into the emitter electrode 7 to a predetermined depth, into the silicon substrate 1 by thermal diffusion.The depth and impurity concentration of the emitter region 6 are .

Since it can be controlled with good reproducibility using the ion implantation conditions and heat treatment conditions for thermal diffusion, it is suitable for manufacturing high-speed bipolar transistors.

However, as the area of the emitter region is reduced as shown in FIG. 3(b), the polycrystalline silicon layers on the side walls of the opening come into contact with each other, and the inside of the opening is filled with polycrystalline silicon. Figure 3(a)
If an attempt is made to thermally diffuse impurities ion-implanted into the silicon substrate 1 under the same conditions as shown in FIG. It is not possible to form a base layer 2 of such thickness.

On the other hand, under the heat treatment conditions suitable for the emitter region shown in FIG. 3(a), the diffusion shown in FIG. 3(b) is insufficient and the impurity concentration and thickness of the emitter layer 6 are insufficient.

Moreover, there is a problem in that the base region 2 has a thickness greater than a predetermined thickness.

When forming the polycrystalline silicon layer constituting the emitter electrode 7, there is a method of doping a predetermined impurity and then thermally diffusing it. Since it is difficult to control the thickness and the reproducibility is insufficient, it cannot be used to form the emitter layer of a fine bipolar transistor.

The present invention makes it possible to form an emitter layer with a predetermined impurity concentration and thickness regardless of the area of the bipolar transistor,
As a result, it is an object of the present invention to make it possible to control the thickness of the base layer to a predetermined value.

[Means to solve the problem]

The above purpose is to form a base region on a semiconductor substrate.

an insulating layer formed on the semiconductor substrate and having an opening corresponding to a predetermined region in the base region; and a semiconductor layer epitaxially grown on the semiconductor substrate exposed in the opening and containing impurities at a predetermined concentration. A bipolar transistor according to the present invention, characterized in that it includes an emitter, and a step of forming an insulating layer over the entire surface of a semiconductor substrate on which a base region is formed, and forming an opening corresponding to a predetermined region in the base region. a step of forming the insulating layer; and a step of selectively epitaxially growing a semiconductor layer containing impurities at a predetermined concentration and forming an emitter on the semiconductor substrate exposed in the opening using a low pressure vapor phase growth method. This is achieved by a method for manufacturing a bipolar transistor according to the present invention, which is characterized in that it includes the following steps.

[For production]

An insulating layer is formed on a silicon substrate, an opening corresponding to the emitter region is provided in this insulating layer, and a silicon layer doped with impurities at a predetermined concentration is selectively epitaxially grown on the silicon substrate exposed in this opening. , this epitaxially grown layer is used as an emitter. in this way,
The emitter layer is composed of an epitaxial layer grown separately from the base layer, and the control factor for the base layer thickness is separated from the conditions for forming the emitter layer. As a result, the base layer.

It becomes possible to maintain a constant layer thickness regardless of the area of the emitter region. Furthermore, according to the emitter structure of the present invention,
The difference in level between the emitter layer and the top surface of the surrounding insulating layer becomes smaller.
Emitter electrode coverage is improved. This means that
This is advantageous when the emitter is miniaturized.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In the following drawings, the same parts as in the previously shown drawings are designated by the same reference numerals.

FIGS. 1A and 1B are cross-sectional views of essential parts showing the structure of the emitter portion of a bipolar transistor according to the present invention, which is shown at a predetermined position on a silicon substrate 1.

For example, the base region 2 is formed by implanting p-type impurities to a predetermined depth. The depth of the base region 2, that is, the base layer thickness may be the same in both FIG. 1 (al and (bl).

Similar to the conventional structure shown in FIG. 3, an interlayer insulator N3 made of, for example, SiO+ is formed in the silicon substrate 1, and an opening corresponding to the base region 2 is provided.

A base extraction electrode 4 connected to the base region 2 through this opening is formed. A second interlayer insulating layer 5 is formed to cover the base extraction electrode 4, and an opening corresponding to the emitter region is provided in the first interlayer insulating layer 5.

In the present invention, an epitaxial silicon layer 8 doped with, for example, an n-type impurity is formed on the silicon substrate 1 exposed in the opening corresponding to the emitter region. The n-type epitaxial silicon layer 8 forms a pn junction with the p-type base region 2 and constitutes an emitter. A wiring 9 made of, for example, an aluminum thin film is formed connected to the epitaxial silicon layer 8. Incidentally, in the conventional structure shown in FIG. 3, two wirings (not shown) are formed as well. In addition.

The thickness of the epitaxial silicon layer 8 in FIGS. 1(a) and 1(b) is substantially the same.

In the present invention, the emitter layer is composed of an epitaxial silicon layer 8 separate from the base layer 2, and there is no need to consider variations in the base layer thickness due to impurity diffusion to form the emitter, as in the conventional case. That is, the base layer thickness can be controlled by base impurity implantation conditions and activation heat treatment conditions, and is maintained at a predetermined value with good reproducibility regardless of the emitter area. Also.

The impurity concentration of the emitter layer depends on the doping conditions during growth of the epitaxial silicon layer 8.

It can be controlled to a predetermined value regardless of the emitter area. moreover,
The difference in level between the epitaxial silicon layer 8 and the top surface of the interlayer insulating layer 5 is reduced by the thickness of the epitaxial silicon layer 8, and the coverage of the wiring 9 connected to the emitter with a small area is improved, thereby preventing contact failure, disconnection, etc. Obstacles are reduced.

FIG. 2 is a sectional view of a main part showing an embodiment of the manufacturing process according to the present invention.

Referring to FIG. 2(a), 9, for example, an n-type silicon substrate l.
9. For example, by using the well-known CVD (chemical vapor deposition) method, an interlayer insulating layer 3 made of SiO□ with a thickness of about 3000 layers is formed, and this is selectively etched to form openings 31 and 32 corresponding to the base region 2. will be established. Openings 31 and 32
The shape and dimensions of are determined depending on the transistor formed in each base region 2.

Then, using the interlayer insulating layer 3 as a mask, ions, such as boron ions (B'), are implanted into the silicon substrate l exposed in the openings 31 and 32.

Next, a polycrystalline silicon layer 4' having a thickness of about 3,000 layers is deposited on the entire surface of the silicon substrate 1 using, for example, a CVD method. A polycrystalline silicon layer of approximately the same thickness is also formed on the side walls of interlayer insulating layer 3 around openings 31 and 32. To this polycrystalline silicon layer 4', ion implantation of ions such as B is performed to increase the conductivity. Then, as shown in FIG. 2(b), the polycrystalline silicon layer 4' within the openings 31 and 32 is selectively etched using the well-known etching technique.

A part of the base region 2 is exposed. Thereafter, the silicon substrate 1 is subjected to heat treatment in a hydrogen (H2) gas atmosphere to activate the ion-implanted boron impurity. In this way, a space extraction electrode consisting of the p-type base layer 2 and the polycrystalline silicon layer 4' is formed. opening 3
The thickness of the base layer 2 in each of 1 and 32 is:
substantially the same.

Next, as shown in FIG. 2C, a glabellar insulator N5 of about 3000 mm thick and made of 1, for example, 5 iOz is formed on the entire surface of the silicon substrate 1 using a well-known CVD technique.

Interlayer insulating layer 5 having the same thickness is also formed on the sidewalls around openings 31 and 32. Then, using a well-known lithography technique, interlayer insulating layer 5 within openings 31 and 32 is selectively etched to expose a portion of base region 2. This exposed surface is determined to be equal to the emitter area of the bipolar transistors formed in openings 31 and 32, respectively.

After the above, a silicon single crystal layer is epitaxially grown on the silicon substrate 1 exposed in the openings 31 and 32. An example of a method of selectively epitaxially growing a silicon layer only on one exposed silicon substrate without growing silicon on the glabellar insulating layer 5 around the openings 31 and 32 has already been disclosed by the present inventors and others. There is. (Unexamined Japanese Patent Publication No. 6
2-159421, July 15, 1988) In summary, a silicon substrate 1 having the structure shown in FIG. 2(C)
is grown in an insulating vapor phase under reduced pressure using 5id16 (disilane) as a silicon raw material gas, and when the growth temperature reaches 900°C or higher, selective growth occurs only on the silicon substrate 1, and an insulating film made of Sing, etc. Neither monocrystalline silicon nor polycrystalline silicon is produced in layer 5. Examples of the above selective epitaxial growth conditions are as follows.

Raw material gas: Si2H6, flow rate: 3SCCM
Carrier gas: H2, flow rate: IOsccM Doping gas: 10 ppm P[1,” + If.

Flow rate: 11005 CC Total pressure: 3 Torr Growth temperature = 950°C Note) Under the above conditions, as shown in Figure 2(d), the opening 3
An n-type epitaxial silicon layer 8 is grown to a thickness of about 2000 nm within the regions 1 and 32. Phosphorus (P) in epitaxial silicon layer 8? The M degree is 1xlO" atoms/d. Therefore, the epitaxial silicon 8 is 8x
It has a specific resistance of lO-'Ω·cm. This n-type epitaxial 9937 layer 8 forms a junction with the p-type base layer 2,
Can be used as an emitter.

After that, aluminum (At) is applied to the entire surface of the silicon substrate 1.
A thin film is deposited and patterned into a predetermined shape, and wiring 9 as shown in FIG. 1 is formed in each opening 31 and 32. In this way.

A bipolar transistor is formed having the n-type silicon substrate 1 as the collector and the n-type epitaxial layer 8 as the emitter.

According to the present invention, since the highly doped selective epitaxial silicon layer 8 is used as an emitter, emitter impurities are ion-implanted into the emitter electrode 7 as in the conventional structure shown in FIG.

There is no need to diffuse this into the base layer 2, and as a result,
The emitter layer thickness, and therefore the base layer thickness, do not vary depending on the emitter area. Furthermore, since the epitaxial silicon layer 8 is formed in the openings 31 and 32 in a self-lined manner, there is an advantage that the process corresponding to the patterning of the polycrystalline silicon layer for forming the emitter electrode 7 in the above conventional structure is omitted. be.

〔Effect of the invention〕

According to the present invention, bipolar transistors having emitters of different areas can be formed on the same substrate in a common process, which has the effect of increasing the degree of freedom in the structure and manufacturing process of semiconductor devices using bipolar transistors. . Furthermore, the coverage of the metal wiring layer with respect to the small area emitter is improved, which has the effect of improving the reliability of the device.

Furthermore, there is an effect that the process related to emitter formation can be simplified.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are sectional views of main parts showing the structure of an emitter portion of a bipolar transistor according to the present invention. FIG. 2 is a sectional view of a main part showing an embodiment of the process of the manufacturing method according to the present invention. 3A and 3B are cross-sectional views of main parts showing the structure of a conventional bipolar transistor. In the figures, 1 is a silicon substrate. 2 is a base region. 3 is an interlayer insulating layer. 4 is a base extraction electrode. 4' is a polycrystalline silicon layer. 5 is an insulating layer between the eyebrows. 6 is an emitter region. 7 is an emitter electrode. 8 is an epitaxial silicon layer. 9 is a wiring. 31 and 32 are openings. 1. Do you have a ball?

Claims (2)

[Claims] (1) A base region formed on a semiconductor substrate, an insulating layer formed on the semiconductor substrate and having an opening corresponding to a predetermined region within the base region, and a predetermined region on the semiconductor substrate exposed within the opening. A bipolar transistor characterized by having an emitter made of a semiconductor layer epitaxially grown containing a high concentration of impurities. (2) forming an insulating layer over the entire surface of the semiconductor substrate on which the base region is formed; forming an opening in the insulating layer corresponding to a predetermined region in the base region; and exposing the insulating layer in the opening. A method for manufacturing a bipolar transistor, comprising the step of selectively epitaxially growing a semiconductor layer containing impurities at a predetermined concentration and forming an emitter on the semiconductor substrate using a low pressure vapor phase growth method.