JPH0242838A - Duplexing line switching system - Google Patents

Duplexing line switching system

Info

Publication number
JPH0242838A
JPH0242838A JP19388588A JP19388588A JPH0242838A JP H0242838 A JPH0242838 A JP H0242838A JP 19388588 A JP19388588 A JP 19388588A JP 19388588 A JP19388588 A JP 19388588A JP H0242838 A JPH0242838 A JP H0242838A
Authority
JP
Japan
Prior art keywords
pattern
circuit
data
route
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19388588A
Other languages
Japanese (ja)
Inventor
Seiichi Yamamoto
山本 成一
Tadashi Kamogawa
鴨川 忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP19388588A priority Critical patent/JPH0242838A/en
Publication of JPH0242838A publication Critical patent/JPH0242838A/en
Pending legal-status Critical Current

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To easily execute error detection processing and to eliminate the limitation of a communication speed by adding a prescribed pattern to data in a transmitting side and executing line switching in a receiving side according to the presence and absence of an error in the pattern. CONSTITUTION:In the transmitting side, a pattern data (n)-bit, which has a prescribed pattern sequence to be generated in a pattern generating circuit 2, is added to a transmitting data (m)-bit by a pattern inserting circuit 3 and sent to routes A and B with (m+n)-bit constitution. In the receiving side, the prescribed pattern sequence is detected from respective receiving data, which come from the routes A and B, by a pattern detecting circuit 4 and the receiving data of the (m)-bit corresponding to transmitting data are separated by a separating circuit 5 in correspondence to a detected result and sent to a selecting circuit 6. For example, when a trouble is generated in the route A and the error is detected in the prescribed pattern by the circuit 4 while the receiving data of the route A are received, connection is switched so that the receiving data of the route B can be selected and outputted by the circuit 6. Thus, the error detection processing is easily executed and the limitation is not given to the communication speed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は二重化回線切替方式に関し、特にデータ伝送に
おいて信頼性確保のために回線を二重化した場合の二重
化回線切替方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a duplex line switching system, and more particularly to a duplex line switching system when lines are duplexed to ensure reliability in data transmission.

〔従来の技術〕[Conventional technology]

従来のこの種の二重化回線切替方式では、選択している
方の回線から到来する受信データ列に誤りを検知した時
に、もう一方の回線の方へ切替えている。
In this type of conventional duplex line switching system, when an error is detected in the received data stream coming from the selected line, the line is switched to the other line.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の二重化回線切替方式は、選択受信してい
るデータ列の内用を解析して誤りを検出するのに処理時
間を要し、誤り検出の処理速度により通信速度に制約を
受けるという欠点がある。
The disadvantage of the conventional duplex line switching method described above is that it takes processing time to analyze the internal use of the selectively received data string and detect errors, and the communication speed is limited by the processing speed of error detection. There is.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の二重化回線切替方式は、送信側に予め定めたパ
ターンをもつデータを発生するパターン発生回路と該パ
ターン発生回路の発生データ及び送信データを多重化す
るパターン挿入回路とを備え、受信側に前記パターンデ
ータを検出するパターン検出回路を二系統と受信データ
列から前記パターンデータを除いて受信データを出力す
る分離回路を二系統と、前記パターン検出回路での誤り
検出結果に応答して前記二系統の受信データのうちの一
方を選択する選択回路とを備えている。
The duplex line switching system of the present invention includes a pattern generation circuit that generates data having a predetermined pattern on the transmission side and a pattern insertion circuit that multiplexes the data generated by the pattern generation circuit and the transmission data. two systems of pattern detection circuits for detecting the pattern data; two systems of separation circuits for removing the pattern data from the received data string and outputting the received data; and a selection circuit that selects one of the received data of the system.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)及び(b)は本発明の一実施例を示すブロ
ック図である。図中の参照番号1は同図(b)に示す送
受信回路を具備した伝送装置、2はパターン発生回路、
3はパターン挿入回路、4はパターン検出回路、5は分
離回路、6は選択回路を示す。伝送装置1は方路A及び
方路Bの二重化回線を介してデータ信号を授受し合う。
FIGS. 1(a) and 1(b) are block diagrams showing one embodiment of the present invention. Reference number 1 in the figure is a transmission device equipped with the transmitting and receiving circuit shown in the figure (b), 2 is a pattern generation circuit,
3 is a pattern insertion circuit, 4 is a pattern detection circuit, 5 is a separation circuit, and 6 is a selection circuit. The transmission device 1 sends and receives data signals to and from each other via route A and route B duplex lines.

伝送装置1における送信゛は、同一回路からの出力信号
を両方路に送出して行なわれ、また受信は、回路を方路
ごとに設けておき、誤りの生じていない方の回路の出力
信号を選択し出力させて行なわれる。
Transmission in the transmission device 1 is performed by sending the output signal from the same circuit to both routes, and reception is performed by providing a circuit for each route and transmitting the output signal of the circuit in which no error has occurred. This is done by selecting and outputting.

すなわち、同図(b)において、送信側では送信データ
mビットに対しパターン発生回路2で発生した所定のパ
ターン系列をもつパターンデータnビットをパターン挿
入回路3で付加して、(m十n)ビット構成で方路A及
び方路Bに送出する。
That is, in FIG. 2B, on the transmitting side, the pattern insertion circuit 3 adds n bits of pattern data having a predetermined pattern sequence generated by the pattern generation circuit 2 to the m bits of the transmission data, so that (m + n) It is sent to route A and route B in bit configuration.

受信側では、方路A及びBから到来する各受信データか
らパターン検出回路4で上述の所定パターン系列を検出
し、この検出結果に応じて分離回路5で上述の送信デー
タに相当するmビットの受信データを分離して選択回路
6へ送る。方路A及びBからの受信データが共に正常で
、例えば方路Aの受信データを選択回路6で選択し受信
データを得ている途中で、方路Aに障害が発生した場合
、方路Aの側のパターン検出回路4で所定パターン中の
誤りを検出すると、この検出結果に応じて3M択回路6
は方路Bの受信データを選択し出力するように、接続を
切替える。
On the receiving side, a pattern detection circuit 4 detects the above-mentioned predetermined pattern sequence from each received data arriving from routes A and B, and a separation circuit 5 detects the m-bits corresponding to the above-mentioned transmission data according to the detection result. The received data is separated and sent to the selection circuit 6. If the received data from routes A and B are both normal and, for example, a failure occurs in route A while the selection circuit 6 selects the received data from route A and obtains the received data, then route A When the pattern detection circuit 4 on the side detects an error in the predetermined pattern, the 3M selection circuit 6 detects an error in the predetermined pattern.
switches the connection so that the received data of route B is selected and output.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、送信側でデータに所定の
パターンを付加し、受信側でそのパターンの誤りの有無
により回線切替を行なうことにより、従来の方式に比べ
誤り検出処理が簡単になり通信速度に制約を与えずに済
むという効果がある。
As explained above, the present invention simplifies error detection processing compared to conventional methods by adding a predetermined pattern to data on the transmitting side and switching lines depending on whether or not there is an error in the pattern on the receiving side. This has the effect that there is no need to impose restrictions on communication speed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a>及び(b)は本発明の一実施例を示すブロ
ック図である。 1・・・伝送装置、2・・・パターン発生回路、3・・
・パターン挿入回路、4・・・パターン検出回路、5・
・・分離回路、6・・・選択回路。
1 (a> and (b) are block diagrams showing an embodiment of the present invention. 1... Transmission device, 2... Pattern generation circuit, 3...
・Pattern insertion circuit, 4...Pattern detection circuit, 5.
... Separation circuit, 6... Selection circuit.

Claims (1)

【特許請求の範囲】[Claims] 送信側に予め定めたパターンをもつデータを発生するパ
ターン発生回路と該パターン発生回路の発生データ及び
送信データを多重化するパターン挿入回路とを備え、受
信側に前記パターンデータを検出するパターン検出回路
を二系統と受信データ列から前記パターンデータを除い
て受信データを出力する分離回路を二系統と、前記パタ
ーン検出回路での誤り検出結果に応答して前記二系統の
受信データのうちの一方を選択する選択回路とを備えて
いる二重化回線切替方式。
A pattern detection circuit that includes a pattern generation circuit that generates data having a predetermined pattern on the transmission side and a pattern insertion circuit that multiplexes the data generated by the pattern generation circuit and the transmission data, and that detects the pattern data on the reception side. two systems, two separation circuits that remove the pattern data from the received data string and output the received data, and one of the two systems of received data in response to the error detection result in the pattern detection circuit. A duplex line switching system equipped with a selection circuit for selection.
JP19388588A 1988-08-02 1988-08-02 Duplexing line switching system Pending JPH0242838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19388588A JPH0242838A (en) 1988-08-02 1988-08-02 Duplexing line switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19388588A JPH0242838A (en) 1988-08-02 1988-08-02 Duplexing line switching system

Publications (1)

Publication Number Publication Date
JPH0242838A true JPH0242838A (en) 1990-02-13

Family

ID=16315354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19388588A Pending JPH0242838A (en) 1988-08-02 1988-08-02 Duplexing line switching system

Country Status (1)

Country Link
JP (1) JPH0242838A (en)

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