JPH0242884A - TV signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a television signal not to generate a flicker from a television signal to adopt a jump scanning by alternately switching first and second buffer storage circuit outputs in a scanning line unit and converting them to linear successive signals. CONSTITUTION:In order to drive first and second buffer storage circuits 213 and 215 and a switch circuit 224, a horizontal synchronizing signal 227 is separated from a television signal 201 by a synchronizing signal separating circuit 226. By using it, a clock signal 229 synchronizing to the horizontal synchronizing signal is generated by a clock generating circuit 228, and a write is controlled. A read is executed at a speed two-fold that of the clock signal. A synchronizing signal 231 having the period of the half of the horizontal synchronizing signal is generated from the horizontal synchronizing signal separated by a multiplier 230, and the switch circuit 224 is controlled. Thus, for the circuit 224, a television signal 225 can be obtained in which one field is made into new one frame, which does not execute the jump scanning and which is converted.

Description

[Detailed description of the invention] [Field of application of the invention]

The present invention relates to a television signal processing circuit, and more particularly, to a signal processing circuit suitable for converting a television signal into a television signal that provides better image quality without causing eye fatigue.

[Background of the invention]

Current standard television systems employ interlaced scanning to reduce the required frequency band. As a result, flickering appears in parts of the screen that change rapidly vertically. The reason why flickering occurs will be explained using FIG. 1st
In the figure, the scanning line group 1 of the first field is sequentially scanned, then the scanning line group 2 of the second field located in the middle of the scanning line group 1 is sequentially scanned, and the scanning line group 1 of the first field is sequentially scanned. is scanned, and so on. Therefore, if one screen changes suddenly in the vertical direction, for example from black at the top to white at the bottom, as shown in Figure 1, the change from black to white in the first field 3 and the location of the change from black to white in the second field 4 are shifted by one scanning line interval. Therefore, the location of the change in black and white moves up and down with the frame period, and this causes a flicker to appear in the portions of the screen where there is a sudden vertical change. The above flickering does not bother you much on a normal screen, but it becomes very noticeable on a screen where many horizontal lines are arranged regularly or where near-horizontal lines are concentrated at one point. It also causes eye fatigue when viewing television images for a long time. [Object of the Invention] Therefore, an object of the present invention is to realize, with a simple circuit, television signal processing for obtaining a flickering-free television signal from a television signal employing interlaced scanning. SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a first semiconductor random that has a storage capacity of half the pixels of at least one scanning line of a first television signal and is capable of independent writing speed and reading speed. an access memory integrated circuit; a second semiconductor random access memory integrated circuit having a storage capacity of half the pixels of at least one scanning line of a second television signal and capable of independent write speed and read speed; 2
The integrated circuit output signal is provided with a switch that alternately switches the output of the integrated circuit on a scanning line basis and converts it into a line sequential signal. In the following embodiments, the case where interlace is 2:1, which is commonly used at present, will be explained.
(n) an integer greater than or equal to 2): The case of 1 can also be realized. [Embodiment j of the invention] Fig. 2 shows a part that converts a line-sequentially scanned image signal, which is the output of an imaging device on the transmitting side, into a 2:1 interlaced television signal in the television signal processing system according to the present invention. FIG. Three primary color signals 101,1 from an imaging if that does not perform interlaced scanning, that is, sequentially scans the frame from top to bottom.
02 and 103 are a luminance signal 105 and two color signals 10 by a generally known matrix circuit 104.
6 and 107. Signals 105, 106 and 107 are supplied to a buffer memory circuit 10 having a capacity for one field.
8° 109 and 110, respectively. Buffer memory circuits 108, 109 and 110 output every other scanning line by a timing signal 113 generated from a timing generation circuit 112 in response to a synchronization signal 111.
14, 115, and 116 and converted into a signal subjected to interlaced scanning. Outputs 115 and 116 corresponding to the two color signals are applied to a commonly known modulation circuit 117 and converted into a carrier color signal 118. The output 114 corresponding to the luminance signal and the carrier color signal 118 are sent to an adder circuit 119.
are added to form a composite color television signal 120. That is, 525 sequentially scanned signals every 1/30 second are recorded in the buffer memory circuit, 108° 109.110, and every other scanning line is read out, so 262.5 signals are stored in 1760 seconds. During the next 1000 seconds, the remaining 262.5 lines are read out and converted into signals for one field. By repeating this process, an interlaced signal similar to a normal television signal is obtained. In FIG. 2, even if the order of the matrix circuit 104 and the 1-field buffer memory circuits 108, 109, and 110 is reversed, the prescribed operation will still occur; however, the band of the three a-buffer memory circuits must be made the same as that of the luminance signal. The circuit scale becomes larger. FIG. 3 shows a color television signal generated by the conversion circuit shown in FIG. 2 which is subjected to interlaced scanning, after being separated into a luminance signal and a chrominance signal by a known luminance two-color signal separation circuit. 1 is a drawing showing an embodiment of a conversion circuit of the present invention for converting a scanning signal into a scanning signal; In FIG. 3, an input signal 201 is converted into a signal 204 delayed by one field and a signal 205 delayed by two fields by two one-field delay circuits 202 and 203. Input signal 201 and signal 204 delayed by one field
are two inputs of the switch circuit 206, and one
The field-delayed signal 204 and the two-field delayed signal 205 become two inputs to the switch circuit 207 . Switch circuits 206 and 207 receive vertical synchronization signal 208
If the one-field delayed signal is present in the first field, the input signal 201 and the one-field delayed signal 204 are connected to outputs 209 and 210, respectively. Also. When the 1-field delayed signal 204 is present in the second field, the 1-field delayed signal 204 and the 2-field delayed signal 205 are output to outputs 209 and 210, respectively. Therefore, the signals of the second field and the first field of the same frame always appear at the outputs 209 and 210. Outputs 209 and 210 are output to scan line buffer memory circuits 213 and 2.
15 and a switch circuit 224, the signal is converted into a signal without interlaced scanning. The signal conversion operation of the receiving section will be explained using the signal conversion circuit shown in FIG. 4 and the waveform diagram shown in FIG. 5. FIG. 4 shows the switch 206.20 of FIG. 2 for convenience of explanation.
This shows the case where switch 7 is in the upper position. (Things that are the same as those in Figure 2 are given the same numbers). As mentioned above, the signals 209 and 210 are generated from the second field and the first field in the same frame, respectively, and depending on the relationship between the number of scanning lines and the field period, these are separated by 180 degrees as shown in Figure 4. There is a phase difference so that adjacent scanning lines exist at the same time. The buffer memory circuits 213 and 21.5 are both memory circuits that have a memory capacity of half the pixel of a -scanning line and can make the write speed and read speed independent, and are semiconductor random access memory integrated circuits, magnetic core random access memory circuits, etc. It consists of storage devices, etc. The reason why the storage capacity is 0.5 scanning lines is
This is because it is sufficient to sequentially read the remaining parts after reading the data. Therefore, if a storage capacity for one scanning line is provided, there is no need to write after reading, and the control circuits for the buffer storage circuits 213 and 215 can be simplified. In order to drive these buffer memory circuits 213, 215 and switch circuit 224, a horizontal synchronizing signal 227 is separated from the television signal 201 by a synchronizing signal separation circuit 226, and using it, a clock generating circuit 228 synchronizes with the horizontal synchronizing signal. A clock signal 229 is generated to control writing. Also, reading is performed at twice the speed of the above clock signal. Also, from the horizontal synchronization signal separated by the multiplier 230,
A synchronization signal 231 having a period half that of the horizontal synchronization signal is generated to control the switch circuit 224. Therefore, the television signals 201 and 204 are read into the 0.5 scanning line grid storage circuits 213 and 215, respectively, up to the center of the scanning line, and the waveforms 213' and 215' shown in FIG. ), 215
' (solid line), read at double speed and use the switch circuit 224 to alternately switch and output the outputs 213' and 215' at half the horizontal cycle, as shown in the waveform 225. , a converted television signal 22 without interlaced scanning in which one field is one new frame.
5 is obtained. Although the present invention has been described above with reference to examples, the present invention is not limited to the above-mentioned examples.
The present invention also includes application to only the luminance component of a television signal or the low frequency part of the luminance component. or,
Although the embodiments have been described with respect to 2:1 interlaced television signals, they generally apply to n:1 interlaced cases as well. In this case, in the conversion circuit on the transmitting side, (n
-1) fields are required, and 2(n-1) field delay circuits are required on the receiving side. Furthermore, although the detailed explanation of the present invention has been made without distinguishing between analog processing and digital processing, when performing processing that involves digital processing and sampling, an AD conversion circuit, a DA conversion circuit, and a filtering circuit are required. . However, how to use these circuits is common knowledge for engineers in the related fields, so explanations are omitted. Effects of the Invention) The present invention can simplify a signal conversion circuit that converts the output of a progressive scanning imaging device into an interlaced signal and reproduces the transmitted signal as a progressive scanning television signal in a receiving section.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating conventional interlaced scanning, FIG. 2 is a circuit configuration diagram of the transmitting side in the television signal processing system according to the present invention, and FIG. 3 is an embodiment of the signal conversion circuit of the present invention on the receiving side. FIG. 4 is a block diagram of the signal conversion circuit shown in FIG. 3, and FIG. 5 is a waveform diagram showing the operation of FIG. 3. 104...Matrix circuit, 108.109,110...Buffer memory circuit, 112.
・・Timing generation circuit, 117 ・・Modulation circuit, 20
2.203...Field delay circuit. 213.215...Buffer memory circuit. Figure No. 7ρ4

Claims (1)

[Claims] 1. A first semiconductor random access memory integrated circuit having a storage capacity of half a pixel of at least one scanning line of a first television signal and capable of independent writing speed and reading speed; and at least one scanning line of a second television signal. a second semiconductor random access memory integrated circuit having a storage capacity of half the pixels of a line and capable of independent write speed and read speed;
A television signal processing circuit comprising a switch that alternately switches the outputs of the first and second integrated circuits in units of scanning lines and converts them into line sequential signals.