JPH0243074U - - Google Patents

Info

Publication number
JPH0243074U
JPH0243074U JP12198088U JP12198088U JPH0243074U JP H0243074 U JPH0243074 U JP H0243074U JP 12198088 U JP12198088 U JP 12198088U JP 12198088 U JP12198088 U JP 12198088U JP H0243074 U JPH0243074 U JP H0243074U
Authority
JP
Japan
Prior art keywords
video signal
scanning method
scan
combining
converting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12198088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12198088U priority Critical patent/JPH0243074U/ja
Publication of JPH0243074U publication Critical patent/JPH0243074U/ja
Pending legal-status Critical Current

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  • Studio Circuits (AREA)
  • Television Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の映像合成装置の1実施例のブ
ロツク図、第2図は第1図の走査変換回路のブロ
ツク図、第3図は第2図のメモリコントローラの
詳細なブロツク図、第4図a,bは第1図の映像
機器のインタレース走査方式の映像信号の垂直、
水平方向の有効画面期間の説明図、第5図a,b
は第1図のコンピユータのノンインタレース走査
方式の映像信号の垂直、水平方向の有効画面期間
の説明図、第6図は第2図の各メモリのメモリマ
ツプ、第7図は従来の映像合成装置のブロツク図
、第8図は第7図の走査変換回路のブロツク図で
ある。 1……NTSC映像機器、2……コンピユータ
、9……走査変換回路、10……スイツチヤ、1
1……オアゲート。
FIG. 1 is a block diagram of one embodiment of the video synthesis device of the present invention, FIG. 2 is a block diagram of the scan conversion circuit of FIG. 1, and FIG. 3 is a detailed block diagram of the memory controller of FIG. Figures 4a and b are vertical diagrams of the interlaced scanning video signal of the video equipment shown in Figure 1.
Explanatory diagram of the effective screen period in the horizontal direction, Figure 5 a, b
is an explanatory diagram of the effective screen period in the vertical and horizontal directions of the video signal of the non-interlace scanning method of the computer in Figure 1, Figure 6 is the memory map of each memory in Figure 2, and Figure 7 is the conventional video synthesis device. FIG. 8 is a block diagram of the scan conversion circuit of FIG. 1...NTSC video equipment, 2...Computer, 9...Scan conversion circuit, 10...Switcher, 1
1...Orgate.

Claims (1)

【実用新案登録請求の範囲】 インタレース走査方式の第1映像信号をノンイ
ンタレース走査方式の高解像度の映像信号に走査
変換する走査変換手段と、 前記変換手段から出力された変換映像信号と前
記ノンインタレース走査方式の第2映像信号とを
合成して前記ノンインタレース走査方式の合成画
面の映像信号を出力する合成手段と を備えたことを特徴とする映像合成装置。
[Claims for Utility Model Registration] Scan converting means for scan-converting a first video signal in an interlaced scanning method into a high-resolution video signal in a non-interlaced scanning method; a converted video signal output from the converting means; A video synthesizing device comprising: combining means for combining a second video signal in a non-interlace scanning method and outputting a video signal of a composite screen in the non-interlace scanning method.
JP12198088U 1988-09-16 1988-09-16 Pending JPH0243074U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12198088U JPH0243074U (en) 1988-09-16 1988-09-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12198088U JPH0243074U (en) 1988-09-16 1988-09-16

Publications (1)

Publication Number Publication Date
JPH0243074U true JPH0243074U (en) 1990-03-26

Family

ID=31369487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12198088U Pending JPH0243074U (en) 1988-09-16 1988-09-16

Country Status (1)

Country Link
JP (1) JPH0243074U (en)

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