JPH0243731A - Vapor growth device for semiconductor - Google Patents

Vapor growth device for semiconductor

Info

Publication number
JPH0243731A
JPH0243731A JP19422388A JP19422388A JPH0243731A JP H0243731 A JPH0243731 A JP H0243731A JP 19422388 A JP19422388 A JP 19422388A JP 19422388 A JP19422388 A JP 19422388A JP H0243731 A JPH0243731 A JP H0243731A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
processed
susceptor
film
holder pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19422388A
Other languages
Japanese (ja)
Inventor
Kazuhiro Imafuku
今福 一博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19422388A priority Critical patent/JPH0243731A/en
Publication of JPH0243731A publication Critical patent/JPH0243731A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To contrive the improvement of the discharge efficiency of plasma, the increase of the growth rate and the improvement of film thickness uniformity of a chemical vapor phase growth film by a method wherein the side surface of a semiconductor substrate is brought into contact to a conductive film which is formed on a holder pin, which is formed on a susceptor, and shows a high conductivity. CONSTITUTION:Reaction gas is filled, a pair of parallel-plate electrodes 12 are arranged in the interior of a reaction container 1 communicated with an evacuator and a film is deposited on each semiconductor substrate 7 to be treated which is fixed on a susceptor 8, which is connected to at least one of the electrodes 12 and consists of a conductive substance, through each holder pin 14 which is formed on the susceptor 8. In such a vapor growth device for semiconductor, the side surface 15 of said substrate 7 is brought into contact to other conductive film 17 which is formed on said holder pin 14 and shows a high conductivity. For example, a gradient 16 to conform to that of the side surface 15 of a semiconductor substrate 7 to be treated is formed on the periphery of a holder pin 14, which is mounted on a susceptor 8 made of carbon and is similarly made of carbon, and moreover, Al or an Al alloy is deposited on the surface of the holder pin by a deposition method or a sputtering method to form a film 17.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体用気相酸゛長装置に係わり、特にプラ
ズマcVD(Chemical Vapour Dep
osition) 装置における半導体基板用サセプタ
(Suceptor)の形状と材質に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a vapor phase acid deposition apparatus for semiconductors, and particularly relates to a plasma cVD (Chemical Vapor Depth
position) Regarding the shape and material of a susceptor for a semiconductor substrate in an apparatus.

(従来の技術) 半導体素子の発達は、製造装置の開発におうところが大
きく、低温で絶縁物層などを半導体基板に堆積できる化
学気相成長装置特にプラズマCVD装置もその一つにあ
げられ、この概要を第4図により説明する。
(Prior art) The development of semiconductor devices has largely depended on the development of manufacturing equipment, and one example of this is chemical vapor deposition equipment, especially plasma CVD equipment, which can deposit insulating layers on semiconductor substrates at low temperatures. The outline will be explained with reference to FIG.

この図には、横型の装置が示されているがこれに限定さ
れないことを先ず付記する。
First, it should be noted that although this figure shows a horizontal type device, the present invention is not limited thereto.

準備された反応容器50の一端51には、ガスキャビネ
ット52を、他端53には、ルーツブロワ54及びロー
タリポンプ55などの減圧装置を気密に接続すると共に
排気口(図示せず)とする。一方、この反応容器50の
外側には、ヒータ56と、これに接続する温度コントロ
ーラ57を設置して内部温度を350〜400°C程度
に制御可能にし、更に、この内部に設ける平行平板電極
58の少なくとも一方には、被処理半導体基板59・・
・が設けられるサセプタ60を電気的に接続することに
より、反応容器50内に被処理半導体塞板59・・・を
配置する。
A gas cabinet 52 is connected to one end 51 of the prepared reaction vessel 50, and a pressure reducing device such as a Roots blower 54 and a rotary pump 55 is connected to the other end 53 in an airtight manner and used as an exhaust port (not shown). On the other hand, a heater 56 and a temperature controller 57 connected to the heater 56 are installed on the outside of the reaction vessel 50 so that the internal temperature can be controlled to about 350 to 400°C. At least one of the semiconductor substrates to be processed 59...
By electrically connecting the susceptor 60 provided with the semiconductors to be processed 59 . . .

この平行平板電極58は、第5図に示した高周波発撮器
65から導き出したRFフィードスル61により高周波
電力を印加して反応容器50内にプラズマを発生するが
、これに先立って導入した反応カスは、このプラズマを
利用する化学反応で生ずる所定の被膜を被処理半導体基
板59・・・に堆積する。
This parallel plate electrode 58 generates plasma in the reaction vessel 50 by applying high frequency power by an RF feedthrough 61 derived from a high frequency oscillator 65 shown in FIG. The dregs deposit a predetermined film on the semiconductor substrates 59 to be processed, which are generated by a chemical reaction using this plasma.

この化学反応を起すには、ルーツブロワ54ならびにロ
ータリポンプ55の稼動により反応容器50内の圧力を
1O−3Torr程度に排気し、更に、ガスキャビネッ
ト52からS ! H4,N1−13.N20などのガ
スを導入しながら行う。
To cause this chemical reaction, the roots blower 54 and rotary pump 55 are operated to exhaust the pressure inside the reaction vessel 50 to about 10-3 Torr, and then S! H4, N1-13. This is done while introducing a gas such as N20.

ところで、カーボンで作られたサセプタ60に被処理半
導体基板59を取付けるには、第6図、第7図及び第8
図に示すようにホルダーピン62を利用する。一方、反
応容器50には、一端51に反応ガス導入口が、他端5
3に減圧装置に連通した排気口が形成されるのは、上記
の通りで、導入する反応カスには、排気口に向かう流路
ができる。
By the way, in order to attach the semiconductor substrate 59 to be processed to the susceptor 60 made of carbon, the steps shown in FIGS.
A holder pin 62 is used as shown in the figure. On the other hand, the reaction vessel 50 has a reaction gas inlet at one end 51 and a reaction gas inlet at the other end 51.
As mentioned above, the exhaust port communicating with the pressure reducing device is formed in 3, and a flow path toward the exhaust port is created for the reaction scum to be introduced.

サセプタ60には、被処理半導体基板59を配置する平
坦面63が形成されており、これを流路に平行になるよ
うに反応容器50内に立てるので、被処理半導体基板5
9表面も流路に沿って配置されることになるのは図示の
通りである。この場合、被処理半導体基板59はサセプ
タ60下方に設置した一対のホルダーピン62.62に
より押えられて固定されるのは、第6図に示す通りであ
る。このようにして固定された被処理半導体基板5つの
断面図を、第4図をA−へ線で切断した第5図に示した
The susceptor 60 has a flat surface 63 on which the semiconductor substrate 59 to be processed is placed, and since this is erected in the reaction vessel 50 parallel to the flow path, the semiconductor substrate 59 to be processed can be placed on the susceptor 60.
As shown in the figure, 9 surfaces are also arranged along the flow path. In this case, the semiconductor substrate 59 to be processed is pressed and fixed by a pair of holder pins 62, 62 installed below the susceptor 60, as shown in FIG. A cross-sectional view of the five semiconductor substrates to be processed fixed in this way is shown in FIG. 5, which is obtained by cutting FIG. 4 along the line A-.

第4図では、流路に沿って被処理半導体基板59の表面
が配置された状態が示されており、第5図には反応容器
50内に配置するサセプタ60の配列状態が明らかにさ
れている。
4 shows the surface of the semiconductor substrate 59 to be processed arranged along the flow path, and FIG. 5 shows the arrangement of the susceptors 60 arranged in the reaction vessel 50. There is.

即ら、反応容器10に設置するサセプタ6()には、上
記の方法で5ON1で50枚、4吋で100枚の被処理
半導体基板が第5図に明らかなように列状に配置され、
しかも、反応カスの流路に沿ってその表向を配置させて
、所定の化学気相成長処理が施される。
That is, in the susceptor 6 () installed in the reaction vessel 10, 50 5ON1 and 100 4-inch semiconductor substrates to be processed are arranged in a row as shown in FIG. 5 using the above method.
In addition, a predetermined chemical vapor deposition treatment is performed with the surface thereof placed along the flow path of the reaction scum.

ところで、被処理半導体基板59の側面64には、素子
の耐圧を向上するためにベベル而を形成しているので傾
斜しているのに対して、保持すべきホルダーピン62は
垂直な面で構成されているので、両面間には隙間ができ
ている。
Incidentally, the side surface 64 of the semiconductor substrate 59 to be processed is sloped because a bevel is formed to improve the withstand voltage of the device, whereas the holder pin 62 to be held is configured with a vertical surface. Because of this, there is a gap between both sides.

更に、被処理半導体基板60の製造工程中に付着する絶
縁物層もしくはPEP(Photo Engrabin
gprocess)工程に使用するレジスト膜などが側
面64には、どうしても付着する。
Further, an insulating layer or PEP (Photo Engraving) that adheres during the manufacturing process of the semiconductor substrate 60 to be processed is added.
A resist film used in the (gprocess) process inevitably adheres to the side surface 64.

一方、集積度の向上に伴ってダスト対策が注目されてい
る最近では、PEP工程で塗布されるレジス]・層が剥
離することにより後工程への影響を避けるため、通称周
辺カットと呼称する清浄化手法が盛んに取入れられてい
る。即ち、PUP工程のレジスト塗イ5工程後、被処理
半導体基板の裏面や側面に回り込んだレジストに、シン
ナを吹付けて除去するバックリンス工程である。しかし
、この]二程でも処理半導体基板の裏面に(=J着した
レジス]・を完全に剥離することはなかなか難しく、ま
た、剥離の程度を夫々一定にするのも困難であった。
On the other hand, recently, dust countermeasures have been attracting attention as the degree of integration has improved, and in order to avoid the effect on subsequent processes due to peeling of the resist layer coated in the PEP process, cleaning methods are being widely adopted. That is, after the resist coating step 5 of the PUP step, there is a back-rinsing step in which thinner is sprayed to remove the resist that has wrapped around the back and side surfaces of the semiconductor substrate to be processed. However, it is quite difficult to completely peel off the (=J deposited resist) on the back surface of the processed semiconductor substrate even in just two steps, and it is also difficult to make the degree of peeling constant.

このバックリンス工程を未実施の被処理半導体基板の断
面図を第7図に、実施したそれの断面図を第8図に示し
た。
FIG. 7 shows a cross-sectional view of a semiconductor substrate to be processed that has not undergone this back-rinsing step, and FIG. 8 shows a cross-sectional view of the semiconductor substrate that has undergone this back-rinsing step.

(発明が解決しようとする課題) 被処理半導体基板には、半導体素子に必要な各種の絶縁
物層が被覆されるが、プラズマ窒化膜などを化学気相成
長装置を利用して減圧CVD法により生成する際には、
サセプタに載置した。被処理半導体基板の裏面や、側面
に設置するへベル而なとにこのプラズマ窒化膜が回り込
んで被着するのが通例で必り、更に、PEP 工程に不
可欠なレジスト摸ヤ、配線工程で被覆されるAl1また
は1合金ら被処理半導体基板の側面にやはり被着する。
(Problem to be Solved by the Invention) A semiconductor substrate to be processed is coated with various insulating layers necessary for semiconductor elements. When generating,
It was placed on a susceptor. This plasma nitride film usually wraps around and adheres to the backside and side surfaces of the semiconductor substrate to be processed. The Al 1 or 1 alloy to be coated also adheres to the side surfaces of the semiconductor substrate to be processed.

一方、サセプタは導電性に優れた炭素で作られており、
ホルダーピンも炭素製である。
On the other hand, the susceptor is made of carbon, which has excellent conductivity.
The holder pin is also made of carbon.

しかも、多数の被処理半導体基板にプラズマCVDまた
は化学気相成長処理を同時に施すと、その裏面に回り込
む割合いが一定せず、更に、側面に被着する吊も同様に
一定しない。更に、バックリンス工程を施しても裏面に
回り込んだものは、完全には剥離Vず、その上、剥離の
程度も一定にならないために、多数の被処理半導体基板
側々にH3ける膜厚均一性及び成長速度に差が生じてい
た。
Moreover, when a large number of semiconductor substrates are subjected to plasma CVD or chemical vapor deposition at the same time, the rate at which the film wraps around the back surface of the substrates is not constant, and the amount of hanging material attached to the side surfaces is also not constant. Furthermore, even if a back-rinsing process is performed, the material that has gone around to the back side will not be completely peeled off, and the degree of peeling will not be constant, so the film thickness will vary by H3 on each side of many semiconductor substrates to be processed. Differences occurred in uniformity and growth rate.

即ら、被処理半導体基板の裏面に絶縁物層が、側面にA
l1またはへ1合金が被着していたとすると、電気的な
抵抗が非常に低いリレブタに、比較的に電気的な抵抗が
高い被処理半導体基板か載置されていることになる。
That is, an insulating layer is formed on the back surface of the semiconductor substrate to be processed, and an A layer is formed on the side surface of the semiconductor substrate to be processed.
If the l1 or hel alloy is deposited, a semiconductor substrate to be processed having a relatively high electrical resistance is placed on a relevator having a very low electrical resistance.

このために、プラズマの放電効率が悪化すると共に、均
一でない裏面絶縁物層の影響を受けて成長速度の低下及
び面内股厚均−性が悪くなる状態を(Gいていた。
For this reason, the plasma discharge efficiency deteriorates, and the growth rate decreases and the in-plane crotch thickness uniformity deteriorates due to the influence of the non-uniform backside insulating layer.

この膜厚均一性とは、いわゆるオリフラを形成した半導
体基板の対称的な周辺部4箇所即ち5mm離れた位置と
、それらの中心部分を含めた5箇所の膜厚を測定する。
This film thickness uniformity is determined by measuring the film thickness at five locations including four symmetrical peripheral parts of the semiconductor substrate, that is, positions 5 mm apart, and the central part thereof, on which a so-called orientation flat is formed.

そして、(5点測定の最高値)−(5点測定の最低1直
)/(2x5点測定値の平均値)・面内膜17ハラツキ
(±%)として、面内股厚均−性の評価基準とした。
Then, evaluate the in-plane crotch thickness uniformity as (highest value of 5-point measurement) - (minimum 1 shift of 5-point measurement) / (2x average value of 5-point measurement) · In-plane membrane 17 unevenness (±%) It was used as a standard.

本発明はこのような事情により成されたもので、特に、
プラズマの放電効率の向上と、化学気相成長被膜の成長
速度及び膜厚均一性を改善覆ることを目的とする。
The present invention was made under these circumstances, and in particular,
The purpose is to improve the plasma discharge efficiency and the growth rate and film thickness uniformity of chemical vapor deposition films.

[発明の構成] (課題を解決するための手段) 本発明は、反応ガスが充填され、減圧装置に連通した反
応容器内に一対の平行平板電極を配置し、その少なくと
も一方に接続する導電性物質からなるリーセプタに形成
するホルダピンを介して固定する被処理半導体基板に被
膜を堆積する半導体用気相成長装置において、前記ホル
ダピンに形成され、より高い導電性を示す他の導電性被
膜に前記半導体基板の側面を接触する点に特徴がある。
[Structure of the Invention] (Means for Solving the Problems) The present invention provides a pair of parallel plate electrodes arranged in a reaction vessel filled with a reaction gas and communicated with a pressure reducing device, and a conductive electrode connected to at least one of the parallel plate electrodes. In a semiconductor vapor phase growth apparatus in which a film is deposited on a semiconductor substrate to be processed that is fixed via a holder pin formed on a receptor made of a substance, the semiconductor is deposited on another conductive film that is formed on the holder pin and exhibits higher conductivity. The feature is that it makes contact with the side of the board.

(作 用) 被処理半導体基板を載置する炭素製のtナセプタには、
同材質のホルダピンを設置しており、これを導電性の高
い材質即らiまたはへ1合金で形成するのは、母材との
差が膜圧均一性やプラズマの放電効率などに悪影響を与
えるために採用できない。
(Function) The carbon t-naceptor on which the semiconductor substrate to be processed is placed has
The holder pins are made of the same material, and if they are made of a highly conductive material, i.e., i or he-1 alloy, the difference with the base material will adversely affect film thickness uniformity and plasma discharge efficiency. Therefore, it cannot be adopted.

このような背県のもとで、本発明では、ホールドピンに
八1やへ1合金などの他の導電性被膜を被覆することに
より、高周波電圧の印加状態を被処理半導体基板の側面
と裏面が同一の4に態としたものである。
Under these circumstances, in the present invention, by coating the hold pin with another conductive film such as 81 or 1 alloy, the application state of high frequency voltage can be adjusted to the side and back surfaces of the semiconductor substrate to be processed. are in the same 4th form.

即ち、バックリンス工程の有無にかかわらず、サセプタ
を構成する炭素に導電性の高い他の導電性被膜を接触さ
せ、更に、半導体基板の材料である例えばケイ素を接触
させて、上記のように高周波電圧の印加状態を同一にし
たものである。
That is, regardless of the presence or absence of a back-rinsing process, another highly conductive film is brought into contact with the carbon constituting the susceptor, and furthermore, silicon, which is the material of the semiconductor substrate, is brought into contact with the high-frequency The voltage application conditions are the same.

この他の導電性被膜用の材料としては、lやA42合金
より高導電性を保有する一、Noなどの高融点金属も利
用できることを付記する。
It should be noted that as other materials for the conductive film, high melting point metals such as 1 and No, which have higher conductivity than 1 and A42 alloy, can also be used.

(実施例) 第1図乃至第3図により本発明に係わる一実施例を説明
する。
(Embodiment) An embodiment of the present invention will be described with reference to FIGS. 1 to 3.

即ら、第1図に示す反応容器1は、その内部に反応カス
を導入し、更に、圧力を1O−3Torr程度に減圧し
て使用するので、気密に形成するのは当然であり、また
、反応ガスの導入し気密状態が保持できるような構造を
反応容器1の一端2に形成する。更に、他端3には導入
した反応ガスを排出する排気口(図示せず)を設置する
ので、ここに向かう反応ガスの流路が形成される。
That is, since the reaction vessel 1 shown in FIG. 1 is used with the reaction scum introduced therein and the pressure reduced to about 10-3 Torr, it is natural that it should be formed airtight. A structure is formed at one end 2 of the reaction vessel 1 so that a reaction gas can be introduced and an airtight state can be maintained. Furthermore, since an exhaust port (not shown) for discharging the introduced reaction gas is installed at the other end 3, a flow path for the reaction gas directed thereto is formed.

この反応カスは、カスキャビネット4からS!t−14
,Nl−13,N20などを導入して使用し、(1!2
 Da 3は、ルーツブロワ5やロータリポンプ6間を
気密な状態で連結して、反応容器1内の圧力を10″3
丁Orr程度として化学気相成長を配置する被処理半導
体基板6・・・表面に施す。
This reaction dregs is sent from dregs cabinet 4 to S! t-14
, Nl-13, N20, etc. are introduced and used (1!2
Da 3 connects the Roots blower 5 and rotary pump 6 in an airtight state to reduce the pressure inside the reaction vessel 1 to 10"3.
Chemical vapor deposition is performed on the surface of the semiconductor substrate 6 to be processed, with a thickness of approximately 100 nm.

この被処理半導体基板7・・・を反応容器1内に配置す
るには、炭素製のサセプタ8を利用するが、これには第
2図に明らかなように設置した平坦面8に設は被処理半
導体基板6の裏面を載置する。
In order to place the semiconductor substrates 7 to be processed in the reaction vessel 1, a carbon susceptor 8 is used, and as shown in FIG. The back side of the semiconductor substrate 6 to be processed is placed.

このサセプタ7を反応容器1に設置するには、この平坦
面9が反応ガスの流路に沿うように設ける方法によって
いるので、被処理半導体基板7の被処理表面も同様に反
応ガスの流路と平行に配置されて、減圧下におけるプラ
ズマを利用する化学気相成長に備える。
The susceptor 7 is installed in the reaction vessel 1 by a method in which the flat surface 9 is provided along the flow path of the reaction gas. and is arranged in parallel to the substrate to prepare for chemical vapor deposition using plasma under reduced pressure.

このプラズマ反応を起こすために、反応容器1の外側に
は、ヒータ10及びこれに接続する温度コントローラ1
1設置して、内部温度を350〜400’C位に制御可
能にし、この内部に平行平板電極12を設ける。
In order to cause this plasma reaction, a heater 10 and a temperature controller 1 connected to the heater 10 are installed on the outside of the reaction vessel 1.
1 is installed so that the internal temperature can be controlled to about 350 to 400'C, and a parallel plate electrode 12 is provided inside this.

この平行平板電極12の少なくとも一方に、サセプタ8
を電気的に接続して、被処理半導体基板7・・・に化学
気相成長を実施する。更に、平行平板電極12は、図示
しない高周波発振器から導き出したRFフィードスル1
3によって、高周波電力を印加して反応容器1内にプラ
ズマを形成する。
A susceptor 8 is attached to at least one of the parallel plate electrodes 12.
are electrically connected to perform chemical vapor deposition on the semiconductor substrate 7 to be processed. Furthermore, the parallel plate electrode 12 is connected to an RF feedthrough 1 derived from a high frequency oscillator (not shown).
3, high frequency power is applied to form plasma in the reaction vessel 1.

このように、反応容器1に設置する被処理半導体基板7
・・・は、サセプタ8の平坦面9に設置するが、その固
定には、従来技術と同様に平坦面9の下方に設置する2
個のホルダーピン14,14(第2図)を利用する。こ
れの頂部には、被処理半導体基板7用の押えが形成され
ている。更に、被処理半導体基板7・・・の側面15に
は、正、負゛シシクは両者の混合型のベベル即ら勾配を
形成して耐圧を上げており、また、バックリンス工程に
よりPUP工程により裏面に回り込んだレジスト層を除
去するのは従来技術と同様である。更に、勾配が形成さ
れる被処理半導体基板7・・・の側面15には、半導体
素子に不可欠な配線+A利AflまたはAl1−3i−
CuやAfl−CuなどのAJ2合金が被覆する場合と
、バックリンス工程によりレジスト層も除去され、この
配線材料も付着していない時もある。ところで、サセプ
タ7に取付けるホルダーピン14.14の周りには、被
処理半導体基板7の側面15の勾配に合う勾装置6を形
成し、更に、その表面には、半導体素子の配線層に適用
するAl1もしくは1合金を蒸着法ヤスバッタリング法
により堆積して被膜17を形成する。
In this way, the semiconductor substrate 7 to be processed placed in the reaction container 1
... are installed on the flat surface 9 of the susceptor 8, but in order to fix them, the 2
holder pins 14, 14 (FIG. 2) are used. A holder for the semiconductor substrate 7 to be processed is formed on the top of this. Further, on the side surface 15 of the semiconductor substrate 7 to be processed, a bevel or gradient of a mixed type of positive and negative pressure is formed to increase the withstand voltage. The process of removing the resist layer that has wrapped around the back surface is the same as in the prior art. Further, on the side surface 15 of the semiconductor substrate 7 to be processed where the slope is formed, wiring +Afl or Al1-3i- which is essential for the semiconductor element is provided.
In some cases, the AJ2 alloy such as Cu or Afl-Cu is coated, and in other cases, the resist layer is also removed by the back-rinsing process and this wiring material is not attached. Incidentally, a gradient device 6 is formed around the holder pin 14.14 attached to the susceptor 7 to match the gradient of the side surface 15 of the semiconductor substrate 7 to be processed. A coating 17 is formed by depositing Al1 or Al1 alloy by a vapor deposition method or a Yasbuttering method.

堆積する金属は、サセプタ8を構成M−る炭素にり導電
性に優れる月利であるAl2もしくはAβ5i−C1l
b L/ < L;J、AE −CIJ ’jト17)
AN Q金カ好適シ、更に、上記のようにW、Noなと
の高融点金属し利用することができ、被処理半導体基板
7とポルグーピン14夫々に勾装置5.16を形成した
状態を第2図の断面図に示した。
The metal to be deposited is Al2 or Aβ5i-C1l, which has excellent conductivity due to carbon constituting the susceptor 8.
b L/ <L; J, AE −CIJ 'j 17)
ANQ Gold is preferable, and as mentioned above, high melting point metals such as W and No can also be used. This is shown in the cross-sectional view of Figure 2.

この第2図に明らかなように、本発明に係わる化学気相
成長装置即ら気相成長装置では特殊な(1°4造を備え
たサセプタを利用しており、側面にベベル面が設置され
た被処理半導体基板に化学気相成長層を確実にしかも安
定して堆積することかできる。
As is clear from FIG. 2, the chemical vapor deposition apparatus according to the present invention, that is, the vapor phase growth apparatus, uses a susceptor with a special (1°4 structure), and a beveled surface is installed on the side surface. A chemical vapor deposition layer can be reliably and stably deposited on a semiconductor substrate to be processed.

これは、サセプタ8を構成する炭素より導電性に優れた
仙の導電性被膜17をホルダーピン14に形成したので
、被処理半導体基板7用に付着した絶縁物層の有無に係
わらず、確実なプラズマの形成、従って安定した化学気
相成長層の堆積ができるようになった。
This is because the holder pin 14 is coated with a highly conductive film 17 that has higher conductivity than the carbon that makes up the susceptor 8, so it can be used reliably regardless of the presence or absence of an insulating layer attached to the semiconductor substrate 7 to be processed. The formation of a plasma and thus the deposition of a stable chemical vapor deposition layer became possible.

[発明の効果1 ザヒブタに固定され、バックリンス工程を実施しない被
処理半導体基板をイ、バックリンス工程を実施した被処
理半導体基板を口、上記のようにバックリンス工程を実
施し更に、上記のように本発明に係わるサセプタとホル
ダーピンを利用した被処理半導体基板をハとして、成長
速度と、面内牧厚均−性を第3図に示した。
[Effect of the invention 1] A semiconductor substrate to be processed that is fixed to the Zahibbuta and not subjected to the back-rinsing process, a semiconductor substrate to be processed that has been subjected to the back-rinsing process, and a semiconductor substrate to be processed that has been fixed to the Zahibuta, and a semiconductor substrate to be processed that has been subjected to the back-rinsing process. FIG. 3 shows the growth rate and in-plane thickness uniformity of a semiconductor substrate to be processed using the susceptor and holder pin according to the present invention.

この図から明らかなように、イは成長速度が300人/
min、面内膜厚均−性も±3.5%とまずまずなのに
対して、口では、成長速度が250人/minに低下し
、面内膜厚均−性も平均±15%と大幅に悪化している
As is clear from this figure, Lee has a growth rate of 300 people/
In contrast, in the mouth, the growth rate decreased to 250 people/min, and the in-plane film thickness uniformity significantly increased to an average of ±15%. It's getting worse.

それに対してハは、成長速度はイとほぼ同じにうに30
0人/minまで上昇し、面内膜厚均−性も±4%とイ
と同等の結果が1qられた。
On the other hand, sea urchin ha has a growth rate almost the same as sea urchin 30.
The rate increased to 0 people/min, and the in-plane film thickness uniformity was ±4%, which is the same result as A.

このように、バックリンス工程により周辺カットを実施
した被処理半導体基板でも、本発明に係わる気相成長装
置を利用すると、成長速度を下げず、生産性を損なわず
に、その上膜厚均一性8悪化することなく例えば窒化ケ
イ素膜を生成することができし、勿論他の膜として2酸
化ケイ素なども生成できる。
In this way, even for semiconductor substrates to be processed whose periphery has been cut by a back-rinsing process, by using the vapor phase growth apparatus according to the present invention, it is possible to improve film thickness uniformity without reducing the growth rate or impairing productivity. For example, a silicon nitride film can be produced without deterioration of the quality of the product, and of course other films such as silicon dioxide can also be produced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は、本発明の一実施例を説明する図で
、第1図は、反応容器の概略を示づ断面図、第2図は、
その要部を示す断面図、第3図は、その特性を明らかに
した図、第4図は、従来の反応容器の概要を示す断面図
、第5図は、第4図を八−へ線で切断した図、第6図と
第7図は被処理半導体基板を取付けたサセプタの断面図
である。 1・・・反応容器 被処理半導体基板 8・・・サセプタ 14:ホルダーピン 15・・・被処理半導体基板の側面 17・・・伯の導電性被膜
1 to 3 are diagrams for explaining one embodiment of the present invention. FIG. 1 is a cross-sectional view showing an outline of a reaction vessel, and FIG.
FIG. 3 is a cross-sectional view showing the main parts of the reaction vessel, FIG. 3 is a diagram clarifying its characteristics, FIG. 6 and 7 are cross-sectional views of a susceptor to which a semiconductor substrate to be processed is attached. 1... Reaction container semiconductor substrate to be processed 8... Susceptor 14: Holder pin 15... Side surface 17 of semiconductor substrate to be processed... Conductive coating

Claims (1)

【特許請求の範囲】[Claims] 反応ガスが充填され、減圧装置に連通した反応容器内に
一対の平行平板電極を配置し、その少なくとも一方に接
続する導電性物質からなるサセプタに形成するホルダー
ピンを介して固定する被処理半導体基板に被膜を堆積す
る半導体用気相成長装置において、前記ホルダーピンに
形成され、より高い導電性を示す他の導電性被膜に前記
半導体基板の側面を接触させることを特徴とする半導体
用気相成長装置
A semiconductor substrate to be processed, in which a pair of parallel plate electrodes are arranged in a reaction vessel filled with a reaction gas and communicated with a pressure reducing device, and fixed via a holder pin formed on a susceptor made of a conductive material connected to at least one of the parallel plate electrodes. In a semiconductor vapor phase growth apparatus for depositing a film on a semiconductor substrate, the side surface of the semiconductor substrate is brought into contact with another conductive film that is formed on the holder pin and exhibits higher conductivity. Device
JP19422388A 1988-08-03 1988-08-03 Vapor growth device for semiconductor Pending JPH0243731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19422388A JPH0243731A (en) 1988-08-03 1988-08-03 Vapor growth device for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19422388A JPH0243731A (en) 1988-08-03 1988-08-03 Vapor growth device for semiconductor

Publications (1)

Publication Number Publication Date
JPH0243731A true JPH0243731A (en) 1990-02-14

Family

ID=16321008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19422388A Pending JPH0243731A (en) 1988-08-03 1988-08-03 Vapor growth device for semiconductor

Country Status (1)

Country Link
JP (1) JPH0243731A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6719849B2 (en) * 2000-05-22 2004-04-13 Tokyo Electron Limited Single-substrate-processing apparatus for semiconductor process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6719849B2 (en) * 2000-05-22 2004-04-13 Tokyo Electron Limited Single-substrate-processing apparatus for semiconductor process

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