JPH0243765A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To effectively decrease a side gate effect in a limited element isolation region by a method wherein a buffer layer of a non-doped compound semiconductor is formed on a substrate of a semi-insulating compound semiconductor through a molecular beam epitaxial growth method or the like as the substrate is kept low in temperature so as to decrease a side gate effect. CONSTITUTION:A buffer layer 2 of a non-doped compound semiconductor is formed on a substrate 1 of a semi-insulating compound semiconductor through a molecular beam epitaxial growth keeping the substrate 1 low in temperature so as to decrease a side gate effect. Next, the substrate temperature is made to decrease gradually or by stages to a specified value and then an intermediate layer 12 of a compound semiconductor and an active layer 3 of a compound semiconductor are grown on the buffer layer 2 through a molecular beam epitaxial growth. Thereafter, an element isolating region 6 is formed so as to reach to as halfway point inside the interlaminar layer 12 penetrating the active layer 3. For instance, when a HEMT element is manufactured, the semi-insulating GaAs substrate 1 is placed in a molecular beam epitaxial growth device, a substrate temperature is set to about 200 deg.C, and the buffer layer 2 of non-doped GaAs is epitaxially grown as thick as about 500Angstrom through an MBE method.

Description

[Detailed description of the invention] [Summary] Using a compound semiconductor layer grown by molecular beam epitaxial growth,
Regarding a method for manufacturing a semiconductor device with an element isolation region, the purpose of the present invention is to provide a method for manufacturing a semiconductor device that can effectively reduce the side gate effect in a limited element isolation region. A compound semiconductor buff layer is grown by molecular beam epitaxial growth at a low substrate temperature to reduce the side gate effect, and the substrate temperature is raised to a predetermined temperature continuously or by film, and a compound semiconductor intermediate layer and a compound semiconductor are grown on the buffer layer. The method is configured to include a step of growing a semiconductor active layer by molecular beam epitaxial growth, and a step of forming an element isolation region that penetrates the active layer and reaches halfway into the intermediate layer below.

[Industrial Application Field] The present invention relates to a method for manufacturing a compound semiconductor device using a compound semiconductor, and particularly to a method for manufacturing a compound semiconductor device using a compound semiconductor layer grown by molecular beam epitaxial growth and having an element isolation region.

In recent years, with the demand for faster computers, compound semiconductors with faster operating speeds have been grown using molecular beam epitaxial growth (MBE).
Many integrated circuits such as MESFETs and HEMTs using semiconductor structures are being produced, and in order to increase the speed and reduce production costs of these integrated circuits, it is necessary to increase integration by limiting the area of separated Wi and regions. It becomes.

A non-doped i (int
rinsic (intrinsic) type GaAs layer 32. n-type AO, 3G
An S layer 33 and an n-type GaAs layer 34 are successively stacked on aO,7. Thereafter, an element isolation region 36 reaching halfway through the i-type GaAS layer 32 is formed by chemical etching or inactivation 0+ ion implantation, and electrodes 37, 38, and 39 are formed. The source electrode 37 and the train electrode 38 are made of AuGe.
After recess etching the n-type GaAs layer 34, the gate electrode 39 is made of Schottky metal, for example,
Formed by depositing 1.

“Prior Art” Conventional compound semiconductor devices using molecular beam epitaxially grown compound semiconductors include M E 5FET, H
There are EMT, etc. Below, as an example, GaAs and AlGaA
HEMT using s will be explained with reference to FIG. Two transistors Tri and T with the same configuration are sandwiched between the isolation region.
r2 is formed.

[Problems to be Solved by the Invention] According to the above-mentioned conventional technology, element isolation was not perfect, and mutual interference between semiconductor elements separated by the element isolation region was likely to occur. Therefore, in order to avoid interference between elements, element division iI
? It was necessary to set the width of the region to several micrometers to several tens of micrometers.

In other words, a phenomenon called side gate effect was observed due to imperfection in element isolation. This phenomenon is a phenomenon in which the two transistors Tri and Tr2 separated by the element isolation region 36 interfere with each other.

For example, when the source voltage of the first transistor Tri in FIG. The measurement results of this limit price change are shown in FIG.

In FIG. 6, the horizontal axis represents the voltage applied to the source current of the second transistor Tr2 in volts, and the vertical axis represents the open chain of the first transistor Tr2 in volts. That is, as the absolute value of the source voltage of the second transistor Tr2, which represents a change in the value on the vertical axis or a change in the open chain which is originally desired to be constant, increases from 0 to IV. , it can be seen that the voltage across the first transistor Tri changes significantly. This phenomenon becomes even more pronounced as the width of the element isolation region becomes narrower. This is called the side gate effect because the bias of the adjacent (side) element acts as if it were a gate voltage.

Therefore, when integrating such devices, it is necessary to widen the width of the device isolation region 36 so that the side gate effect does not occur or is reduced to the extent that it does not affect the side gate effect. For example, when -3V is applied to the second transistor Tr2, the first and second transistors Tri, Tr
The element separation width between the two is required to be several tens of μm.

One of the causes of the side gate effect is considered to be the interface between the substrate 31 and the non-doped compound semiconductor layer 32 (I
EEE, Electron Device Let
ters, vol, EDL-8°No, 6. p28
0 (1987)).

Therefore, in order to isolate the interface, as shown in FIG. 7, the element isolation region 36 is formed to penetrate the non-doped compound semiconductor layer 32 and reach into the substrate 31, thereby reducing the side gate effect. Conceivable. However, the depth from the surface to the substrate 31 is usually about 1 μm. If element isolation of this depth is performed by etching, the remaining step will cause a break in the wiring metal, making it impossible to obtain reliability.Therefore, it may be possible to perform element isolation by using ion implantation in step 1. , the lick of the ion's lateral spread,
For example, a wide element isolation region width of about 3 μm is required.

As described above, according to the prior art, it has not been possible to achieve a good element separation M by limiting the element isolation region.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can effectively reduce the side gate effect using a limited element isolation region.

An element isolation region 6 is provided that penetrates the dynamic layer 4 and reaches at least partway through the intermediate compound semiconductor layer 12.

In addition, on the semi-insulating compound semiconductor substrate 1, a non-doped compound semiconductor buffer layer 2 is grown by molecular beam epitaxial growth at a low substrate temperature to reduce the side gate effect, and the substrate temperature is raised continuously or stepwise. Then, a compound semiconductor intermediate layer 12 and a compound semiconductor active layer 4 are grown by molecular beam epitaxial growth. An isolation region 6 is formed that penetrates the active layer 4 and reaches at least halfway through the intermediate compound semiconductor layer 12 .

[Means for Solving the Problems] As shown in FIG. 1, a buffer layer 2 of a non-doped compound semiconductor is grown by molecular beam epitaxial growth on a semi-insulating compound semiconductor substrate 1 at a low substrate temperature that reduces the side gate effect. Thereon, an intermediate layer 12 of a compound semiconductor and an active layer 4 of a compound semiconductor are formed by molecular beam epitaxial growth by increasing the substrate temperature continuously or stepwise to a predetermined temperature. Function [Function] A non-doped compound semiconductor layer grown by molecular beam epitaxial growth at a low substrate temperature has a high resistance to carrier movement under a high electric field.
It is considered to have an excellent shielding effect. This can reduce side gate effects.

In a semiconductor device having such a non-doped compound semiconductor layer, it is not necessary for the element isolation region to reach the substrate; it is sufficient to provide an element isolation effect that penetrates the active layer and reaches halfway to the intermediate layer below. Separation effect can be obtained.

[Example] Figures 2 (A), (B), and (C) illustrate several steps in the manufacturing process of a HEMT device according to an example of the present invention.

A semi-insulating GaAs substrate 21 was placed in a molecular beam epitaxial growth (MBE) apparatus, the substrate temperature was set at approximately 200°C, and a non-doped GaAs substrate 21 was grown as shown in FIG.
The buffer layer 22a is epitaxially grown using the MBE method using about 500 people.

As will be explained further below, a land-1 semiconductor buffer layer grown at such a low substrate temperature can reduce side gate effects. The thickness of this buffer layer 22a is 200 mm in order to prevent a good side gate effect.
It is desirable that it be at least Å.

The low substrate temperature is a temperature of at most 400°C, preferably about 300°C or less, more preferably about 200°C or less. However, the temperature is not lower than 150°C.

The side gate effect is caused by the movement of carriers under a high electric field.
This can be explained by considering that the potential changes due to accumulation in some kind of trap on the substrate under the element or at the interface between the substrate and the MBE layer.

MBE epitaxial growth layers grown at low substrate temperatures are believed to introduce many defects. It is believed that deep-level carrier traps are formed along with such crystal defects. A semiconductor layer containing a large number of such deep unit carrier traps is considered to have an excellent shielding effect against carrier movement under a high electric field, as described below.

When carriers such as electrons move, the deep unit carrier traps capture and strongly bind the carriers. Thereby, passage of the carrier can be prevented. In this way, it is considered that the cause of the side gate effect, which is thought to be caused by the interface between the substrate and the non-doped compound semiconductor layer thereon, can be shielded.

In order to form a good semiconductor device, the buffer layer of the land-1 compound semiconductor must be a single crystal, and the active layer of the compound semiconductor with good crystallinity must be grown on it.What is the low substrate temperature? , is the temperature at which a single crystal is grown by the MBE method while forming a large number of such deep unit carrier traps.

Non-doped GaAs buffer layer 22a at low substrate temperature
After growing non-doped aaAsJ!, as shown in FIG. 2(B), the substrate temperature is continuously increased. Then, a non-doped GaAs layer 22c is grown while keeping the substrate temperature constant at 680°C. GaAs layer 22b, 2
2c with a total thickness of 5,500 people. Next, while keeping the substrate temperature at 680°C, Si was
-3 doped n-type At, 3Ga.

7, the S layer 23 has a thickness of 400 mm, and Si is doped in the same way.

1000 n-type GaAs layers 24 are grown.

Non-doped GaAs layer 22c and n-type AIGaAS layer 23
A two-dimensional carrier (electron in this case) gas 25 is generated near the surface of the non-doped GaAs layer 22c due to the difference between the contact potential and the impurity concentration.

As shown in FIG. 2C, first, 0+ ions are implanted between the two transistors Tr1 and Tr2 to form an element isolation region 26. The element isolation region 26 penetrates through the active layers 23 and 24 and connects to the i-type GaAs layer 22 below.
c Next, a source electrode 27 and a drain electrode 28 are formed on the n-type GaAs layer 24, and the n-type GaAs layer 24 is recessed and etched to form a gate electrode 29. form. Source electrode 2
7. The drain electrode 28 is, for example, an n-type GaAs layer 24
Approximately 4,000 thick AuGe alloyed at 450℃ to
and Au layer, and the two gate electrodes are, for example, an A1 layer with a thickness of about 4000 nm.

On this structure, an interlayer insulating film such as S i O 2 and a wiring metal layer (not shown) for connecting between electrodes are formed to constitute an integrated circuit.

On the other hand, the temperature at which the GaAs layer 22c, the n-type AlGaAs layer 23, and the n-type GaAs layer 24 are grown by MBE is a non-doped GaAs buffer HI22a that actively creates crystal defects.
Unlike the growth method shown in FIG. 2, when a semiconductor layer with good crystallinity is grown by MBE, the temperature is not limited to 680°C, but can be selected from the range of 500 to 700°C.

FIG. 3 shows a cross-sectional view of a compound semiconductor device according to another embodiment. In FIG. 2(B), first, while the substrate temperature is continuously raised to a predetermined substrate temperature,
After growing the GaAs layer 22c by MBE at a predetermined substrate temperature, in the embodiment shown in FIG. 3, after growing the i-type GaAs layer 22a at a low substrate temperature of 200° The temperature was raised to 680℃, and the i-type GaAs
Layer 22c is grown by MBE to about 0.5 μm. Others are second
This is similar to the embodiment shown in the figure.

In the compound semiconductor device 1 having the configuration shown in FIG. 3, the source voltage and drain voltage of the first transistor Tri are o and iv, respectively, and the second transistor Tri
The dark value of the first transistor Tri was measured by changing the voltage applied to the S$ pole. Here, the element isolation width of the semiconductor device used in the measurement was 1 μm. The measurement results are shown in Figure 4.

In FIG. 4, the horizontal axis represents the voltage applied to the source electrode of the second transistor, and the vertical axis represents the dark value of the first transistor. As soon as the magnitude of the source voltage of the transistor increases from 0, the side gate effect fI! As you may have guessed, in the case of Figure 4, the source voltage of the second transistor is approximately -4
When compared with the conventional example, in which the dark value does not show any change up to V, and hardly any side gate effect is shown, it can be seen that the above embodiment can greatly reduce the side gate effect.

Note that no deterioration in performance as a single transistor was observed, and the effect of growing the non-doped GaAs layer 22a at 200°C is that the i-type G
It is thought that this could be prevented by forming the active layers 23 and 24 after growing the aAs layer 22c.

The depth of the element isolation region due to oxygen ion implantation is 2
Since the width of the element isolation region could be set to below the dimensional carrier gas 25, the width of the element isolation region could also be set to about 1 μm.

Furthermore, it is also possible to insert a p-type GaAs layer or a 1-GaAs layer into the i-type GaAs under the active layer, Iji22c, to prevent the short channel effect.
It is also possible to insert an i-type GaAs layer as a buffer layer between the 1 and I-type GaAs layers.

Although the case of HEMT has been described, it is obvious that the present invention is not limited to this. For example, a normal FET can be made. In this case, for example, a non-doped i-type GaAs layer is grown on a GaAs substrate by MBE at a low substrate temperature, an i-type GaAs layer is grown by raising the substrate temperature, and an n-type GaAs layer is further grown to form a channel. It can be an active layer.

The present invention has been described above according to several embodiments, but
It will be obvious to those skilled in the art that various combinations, changes, modifications, etc. can be made without departing from the spirit of the invention.

[Effects of the Invention] A semiconductor device with good element isolation in which the side gate effect is reduced in a limited element isolation region without deteriorating element performance can be obtained.

High degree of integration can be achieved when it is integrated into an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention. FIGS. 2(A), (B), and (C) are sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3 is a diagram of the principle of the present invention. A cross-sectional view of a semiconductor device according to another embodiment; FIG. 4 is a graph showing measurement data representing the degree of reduction in the side game effect according to a specific example of the configuration shown in FIG. 3; FIG. 5 is a cross-sectional view of a semiconductor device according to a conventional technique. , FIG. 6 is a graph showing measurement data representing the side gate effect of the semiconductor device according to the conventional configuration example shown in FIG. 5, and FIG. FIG. 3 is a cross-sectional view showing the configuration. In the figure, a semi-insulating semiconductor substrate, a non-doped compound semiconductor buffer layer 3.23.24 and a compound semiconductor active layer 6.26 grown by the MBE method at a low substrate temperature.
Element isolation regions 12, 22b, 22c compound semiconductor intermediate layer 25
Two-dimensional carrier gas 1.21 2.22a 2 Buffer layer 78.9 of non-doped compound semiconductor
Electrode Principle diagram of the present invention No. 1 Fig. 21 Semi-insulating semi-insulating doped substrate 22a Non-doped layer (A) Buffer layer growth at low temperature Example of the invention No. 2 Fig. 2b 22C Temperature raised growth Non-doped GaASN Cavity temperature growth Nondorf' GaAs layer n-AlGaAs layer n GaAS1! (B) Growth of intermediate layer and buffer layer at elevated temperature 26
0゛Implemented element isolation regions 27, 28.29 Electrode (C) 3, Formation of element isolation regions Embodiment of the present invention Fig. 2 (continued) Conventional semiconductor device 1 Fig. 5 Structure of Fig. 52 yρnide gate effect Fig. 6 Another embodiment of the present invention Fig. 3 Side gate effect tube according to the configuration example shown in Fig. 3 Fig. 4

Claims (1)

[Claims] (1) A step of molecular beam epitaxial growth of a non-doped compound semiconductor buffer layer (2) on a semi-insulating compound semiconductor substrate (1) at a low substrate temperature that reduces side gate effects; The temperature is raised continuously or stepwise to a predetermined temperature, and a compound semiconductor intermediate layer (12) is formed on the buffer layer (2).
) and a compound semiconductor active layer (3) by molecular beam epitaxial growth, and forming an element isolation region (6) penetrating the active layer (3) and reaching halfway into the intermediate layer (12) below. A method for manufacturing a compound semiconductor device, comprising the steps of: