JPH0244142B2 - - Google Patents

Info

Publication number
JPH0244142B2
JPH0244142B2 JP59138927A JP13892784A JPH0244142B2 JP H0244142 B2 JPH0244142 B2 JP H0244142B2 JP 59138927 A JP59138927 A JP 59138927A JP 13892784 A JP13892784 A JP 13892784A JP H0244142 B2 JPH0244142 B2 JP H0244142B2
Authority
JP
Japan
Prior art keywords
layer
silicon layer
insulating layer
silicon
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59138927A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6119147A (ja
Inventor
Toshiro Ogino
Katsumi Murase
Masahiro Sakagami
Yoshihito Amamya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP59138927A priority Critical patent/JPS6119147A/ja
Publication of JPS6119147A publication Critical patent/JPS6119147A/ja
Publication of JPH0244142B2 publication Critical patent/JPH0244142B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP59138927A 1984-07-06 1984-07-06 半導体装置の製造方法 Granted JPS6119147A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59138927A JPS6119147A (ja) 1984-07-06 1984-07-06 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59138927A JPS6119147A (ja) 1984-07-06 1984-07-06 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6119147A JPS6119147A (ja) 1986-01-28
JPH0244142B2 true JPH0244142B2 (sr) 1990-10-02

Family

ID=15233388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59138927A Granted JPS6119147A (ja) 1984-07-06 1984-07-06 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS6119147A (sr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2779186B2 (ja) * 1988-11-22 1998-07-23 株式会社日立製作所 半導体装置の製造方法
US5521108A (en) * 1993-09-15 1996-05-28 Lsi Logic Corporation Process for making a conductive germanium/silicon member with a roughened surface thereon suitable for use in an integrated circuit structure

Also Published As

Publication number Publication date
JPS6119147A (ja) 1986-01-28

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