JPH0244427U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a delay circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a signal processing circuit of a magnetic disk device, and FIG. 3 is a signal waveform diagram for explaining its operation. Fig. 4 is a connection diagram showing the specific configuration of the delay circuit, Figs. 5 to 7 are signal waveform diagrams to explain its operation, Fig. 8 is a block diagram showing a conventional delay circuit, and Fig. 9 is FIG. 10 is a block diagram showing another conventional delay circuit, and FIG. 11 is a signal waveform diagram for explaining the operation. 1, 5, 13...delay circuit, 11...differentiation circuit, 12...window circuit, 25,29...discharge current source, 27,31...inverting amplifier circuit, CA, CB
...Charge/discharge capacitor.

Claims (1)

[Scope of Claim for Utility Model Registration] A charging/discharging capacitor, a charging current source or a discharging current source for the charging/discharging capacitor, and a charging/discharging capacitor in which the charging/discharging capacitor and the charging current source or discharging current source are connected to an emitter. a transistor configured to apply a discharging current or a charging current to a transistor; and first and second transistor circuits having the following: After delaying the rise or fall of the input pulse signal with the first transistor circuit, A delay circuit characterized in that the second transistor circuit delays falling or rising.