JPH0244429U - - Google Patents
Info
- Publication number
- JPH0244429U JPH0244429U JP12365288U JP12365288U JPH0244429U JP H0244429 U JPH0244429 U JP H0244429U JP 12365288 U JP12365288 U JP 12365288U JP 12365288 U JP12365288 U JP 12365288U JP H0244429 U JPH0244429 U JP H0244429U
- Authority
- JP
- Japan
- Prior art keywords
- line
- fet
- inductance
- electrodes
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Waveguide Switches, Polarizers, And Phase Shifters (AREA)
- Electronic Switches (AREA)
Description
第１図はこの考案の一実施例によるＲＦスイツ
チのＦＥＴ近傍の構成図、第２図は従来のＲＦス
イツチのＦＥＴ近傍の構成図である。
図中、１は入力線路、２はＦＥＴ、２ａはＦＥ
Ｔ２のソース電極、２ｂはドレイン電極、２ｃは
ゲート電極、３は出力線路、４はインダクタンス
用線路、４ａは開放形インダクタンス用線路、４
ｂは付加回路、４ｃは金リボン、５はゲートバイ
アス回路である。なお、図中同一符号は同一、又
は相当部分を示す。
FIG. 1 is a block diagram of the vicinity of the FET of an RF switch according to an embodiment of this invention, and FIG. 2 is a block diagram of the vicinity of the FET of a conventional RF switch. In the figure, 1 is the input line, 2 is the FET, and 2a is the FE.
T2 source electrode, 2b drain electrode, 2c gate electrode, 3 output line, 4 inductance line, 4a open inductance line, 4
b is an additional circuit, 4c is a gold ribbon, and 5 is a gate bias circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
る入出力線路と、その入出力線路の接点に配置さ
れるＦＥＴと、そのＦＥＴのゲート電極に接続さ
れるゲートバイアス線路と、前記ＦＥＴのソース
電極とドレイン電極の間に接続されるインダクタ
ンス用線路とで構成されるＲＦスイツチにおいて
、上記誘電体基板上のインダクタンス用線路を開
放形に形成し、かつ、その近傍に付加回路を配置
して、前記付加回路を経由して金リボンでインダ
クタンス用線路を前記ＦＥＴに並列接続したこと
を特徴とするＲＦスイツチ。 An input/output line formed of a strip line on a dielectric substrate, an FET arranged at the contact point of the input/output line, a gate bias line connected to the gate electrode of the FET, and a source electrode and a drain of the FET. In an RF switch configured with an inductance line connected between electrodes, the inductance line on the dielectric substrate is formed into an open type, and an additional circuit is arranged near the inductance line, and the additional circuit is connected between the electrodes. An RF switch characterized in that an inductance line is connected in parallel to the FET via a gold ribbon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12365288U JPH0244429U (en) | 1988-09-21 | 1988-09-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12365288U JPH0244429U (en) | 1988-09-21 | 1988-09-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0244429U true JPH0244429U (en) | 1990-03-27 |
Family
ID=31372697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12365288U Pending JPH0244429U (en) | 1988-09-21 | 1988-09-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0244429U (en) |
-
1988
- 1988-09-21 JP JP12365288U patent/JPH0244429U/ja active Pending
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