JPH0244434B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an image signal correction device, and more particularly to an image signal correction device for white density and black density regions in an optical reading device for recorded information having halftones.

[Prior art]

An optical reading device for recorded information with halftones uses continuous tone photographic originals (hereinafter referred to as original images).
A laser beam is used to scan the plane, and the light reflected from the original image is converted into electricity to obtain a high voltage for the white of the photograph and a low voltage for the black.

Original pictures used, especially original pictures for news, have different shooting conditions such as weather, location, and time, so it is often not possible to shoot them under the best exposure conditions.

Therefore, many original news images do not have desirable density values in their white density and black density areas.

Generally, in a photograph printed on photographic paper to obtain good density, the white density will be around 0.1 and the black density will be around 2.0. However, for the above-mentioned reasons, the above-mentioned white and black density values cannot usually be obtained in original pictures for news purposes.

In the process of photoelectric conversion, everything is converted into an image signal with an output voltage that is inversely proportional to the density. The image signal is digitally converted to facilitate signal processing, but in this conversion process, the black and white density range of the original image is corrected to the above density value range.
This is extremely important for high-quality image reproduction.

In a conventional image signal correction device, an upper limit reference voltage and a lower limit reference voltage are fixed to set values in an analog-to-digital conversion circuit that converts an analog image signal read by scanning into a digital image signal, and the upper limit reference voltage is fixed to a set value. y between the reference voltage and the lower limit reference voltage
The analog image signal is divided into different judgment levels and converted into a digital code corresponding to the judgment level.

Therefore, if the highest voltage for white of the analog image signal is lower than the upper limit reference voltage, and if the lowest voltage for black is higher than the lower limit reference voltage,
It is not possible to obtain the y-step resolution that the analog-to-digital conversion circuit has.

Next, the digitally encoded image signal is corrected using corrected data for white and black density values. However, when the signal is not resolved to y levels in analog-to-digital conversion, the level resolution cannot be improved by correction.

That is, although the conventional image signal correction apparatus incorporates a high-precision analog-to-digital conversion circuit, it has the disadvantage that it can only output an image with a lower level resolution than the resolution it has.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image signal correction device that can obtain a level resolution equal to that of an analog-to-digital conversion circuit without being bothered by minute dust and scratches on an original image.

[Structure of the invention]

The image signal correction device of the present invention includes a white extraction circuit that extracts white data from each of a plurality of pixels obtained by scanning a specified white density region of an original image and outputs white extracted data, and a white extracted circuit that outputs white extracted data. a white level comparison circuit that compares the white data with a preset white reference value, selects all of the white data higher than the white reference value from the white extraction data, and outputs the selected white data as selected white data;
a black extraction circuit that extracts black data from each of a plurality of pixels obtained by scanning a designated black density area of the original image and outputs black extraction data; and a black reference value that presets the black extraction data. A black level comparison circuit selects all the black data that is lower than the black reference value from the black extraction data and outputs it as selected black data; an average value circuit that outputs correction data, white correction data, and black correction, and a determination level between an upper limit and a lower limit of a dynamic range is controlled by the white correction data and the black correction data, and grayscale information recorded on the original image. and an analog-to-digital conversion circuit that decomposes the photoelectrically converted image signal into multivalues according to the determination level.

[Explanation of Examples]

In the present invention, prior to scanning an original image, a white density area to be made white and a black density area to be made black are respectively designated on the original image, and each white and black density area is pre-scanned. Find the average value of the white data from the white density area obtained in the previous scan that is higher than the preset white reference value, and find the average value of the black data from the black density area that is lower than the preset black reference value. By using these average values as upper and lower limit reference voltages and performing analog-to-digital conversion, the voltage values for white and black of the image signal are corrected to predetermined voltage values for white and black, respectively.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the image signal correction device includes a white extraction circuit 1, a white level comparison circuit 2, a black extraction circuit 3, a black level comparison circuit 4,
It includes an average value circuit 5, a scanning circuit 6, and an analog-to-digital conversion circuit 7.

Below, the operation of the image signal correction device shown in FIG. 1 will be explained in detail with reference to FIGS. 2 to 7. 2 is a detailed block diagram of the white extraction circuit 1 in the embodiment shown in 1Q, FIG. 3 is a detailed block diagram of the average value circuit 5 in the embodiment shown in FIG.
FIG. 4 is a time chart for explaining the operation of the white extraction circuit shown in FIG. 2, FIG. 5 is an explanatory diagram of the operation of image signal extraction by the white extraction circuit shown in FIG. FIG. 7 is an apparent waveform diagram for explaining the operation of the embodiment shown in FIG. 1. FIG.

In FIG. 1, during pre-scanning prior to scanning the original image, the read preparation signal P is set to "high" and is supplied to the average value circuit 5.

The memory circuit 504 shown in FIG. 3 has a reflectance of 100%.
Reference white correction data H ₁₀₀ of all 8-bit white correction data H representing "high" is stored, and is read out while the read preparation signal P is "high".

In Fig. 1, the reference white correction data H ₁₀₀ is supplied to the digital-to-analog conversion circuit 11, and after converting into an analog voltage value, unnecessary frequency components are removed by the low-pass filter 12, and it is output as the upper limit reference voltage V _H. be done. The voltage value of the upper limit reference voltage V _H at this time is "V ₊ " volts, which corresponds to all the 8-bit digital codes shown in FIG. be.

The storage circuit 505 shown in FIG. 3 stores reference correction data Y0 of 8-bit black correction data Y, which is all "low" and represents a reflectance of ₀ %, and when the read preparation signal P is "high". The period is read.

In FIG. 1, reference black correction data Y ₀ is supplied to a digital-to-analog conversion circuit 21, converted into an analog voltage value, unnecessary frequency components are removed by a low-pass filter 22, and output as a lower limit reference voltage V _L. be done. The voltage value of the lower limit reference voltage V _L at this time is
All 8-bit digital codes shown in FIG. 6 are "V _- " volts corresponding to "low", and this value becomes the lower limit voltage of the analog-to-digital conversion circuit 7.

On the other hand, in FIG. 1, the scanning circuit 6 performs pre-scanning prior to scanning the original image while the reading preparation signal P is "high", and outputs an image signal A to be supplied to the analog-to-digital conversion circuit 7. The image signal A is a signal that has a high voltage for the white of the original image and a low voltage for the black for each pixel.

The analog-to-digital conversion circuit 7 sets the upper limit voltage to
Perform 8-bit multi-value conversion according to the voltage value of image signal A, setting V ₊ volts and the lower limit voltage to V _- volts,
Digital image signal in digital image signal B
Output B _b . Here, the digital image signal B consists of a corrected image signal B _a and a digital image signal B _b , and the corrected image signal B _a indicates an image signal subjected to signal correction, which will be described later.

While the reading preparation signal P is “high”, the bus switching gate 8 transfers the digital image signal B _b to the white extraction circuit 1.
and is supplied to the black extraction circuit 3.

The white extraction circuit 1, as shown in FIG. and memory circuit 1
13, which extracts density data corresponding to a plurality of pixels from a designated white density region of the original image and outputs white extracted data.

Prior to scanning the original image, a density area to be made white is specified in advance on the original image. That is, in this embodiment, as an example, as shown in FIG. A case will be explained in which a region consisting of 25 pixel groups consisting of pixels is specified.

In the following description, the operation of the white extraction circuit 1 shown in FIG. 2 will be described with reference to FIGS. 4 and 5.

The counter 101 is set to (n-1), counts the phase pulses PH from when the read preparation signal P becomes "high", and outputs the output signal a at the trailing edge of the (n-1)th phase pulse. goes "low" and remains "low" until the trailing edge of the next phase pulse.

The counter 104 is set to "5" corresponding to the number of scanning lines including the pixels to be extracted, and the inverted phase pulse whose phase is inverted by the inverter 102 and the counter 10 whose phase is inverted by the inverter 103 are set.
An inverted output signal a from 1 is supplied.

Counter 104 is activated when the inverted output signal is "high" and counts five inverted phase pulses. Therefore, the output signal b from the counter 104
As shown in Figure 4, becomes "low" at the leading edge of the n-th phase pulse and becomes "high" at the leading edge of the (n+5)th phase pulse, but when the output signal b becomes "low" The period includes phase pulses PH for five scanning lines including pixels to be extracted.

The OR circuit 105 performs the OR of the output signal b of the counter 104 and the inverted phase pulse PH, and outputs five extracted phase pulses d starting from the n-th pulse.

Next, the counter 106 is set to (m-1), which corresponds to the number of pixels in the main scanning direction from the main scanning start point, and is activated every time the extraction phase pulse d is supplied to count the pixel clock S. , extracted phase pulse d
A "low" extraction start position designation signal e is generated at the trailing edge of the signal e and disappears after (m-1) counts.

“+V” is applied to the D input of flip-flop 107.
A voltage is supplied thereto, which is set when the extraction start position designation signal e disappears, and the output signal from the Q output is set to "high", and is reset by the reset signal R.
However, the reset signal R is a signal that remains "low" during a period when the image signal A is not generated in the period T of one scanning line.

The "high" output signal from the Q output of flip-flop 107 is output from the D output of flip-flop 108.
At the leading edge of the next pixel clock S applied to the input,
The flip-flop 108 is set, a "high" extracted pixel position signal f is outputted from the Q output, and it is reset with a reset signal R.

Next, the logical product of the extracted pixel position signal f and the pixel clock S is taken by the logical product circuit 109, and the extracted pixel clock h from the m-th pixel clock from the main scanning start point until the reset signal R is generated is: The extracted pixel position signal f is output every "high" period.

The counter 110 is set to "5", which is the number of extracted pixels in the main scanning direction, and the extracted pixel position signal f is "high".
It is activated when the pixel clock h is counted, and becomes "high" when it counts five pixels, and outputs an output signal k that is converted to "low" by the next phase pulse PH. feed the input.

The flip-flop 111 has a voltage of "+V" supplied to its D input, is set when the output signal k becomes "high", is reset by a reset signal R, and outputs a "low" extraction end position signal r. Output.

Next, the NAND of the extraction pixel clock h and the extraction end position signal r is taken by the NAND circuit 112, and a write signal w having five pixel clocks is output, and the digital image signal _B of the storage circuit 113 is included,
Each corresponding to the write signal w instructs writing of 8-bit pixel data.

The storage circuit 113 is composed of 25 8-bit words, and when it has finished storing white data for 25 pixels with 8 bits per pixel and the read request signal U from the average value circuit 5 is "high", the stored white data is stored. The data is read out and supplied to the white level comparison circuit 2 as white extraction data E. At the same time, a white data sending signal _W1 is sent to the average value circuit 5. White data sending signal W ₁
continues to be sent until the average value circuit 5 completes processing of the white extraction data E and the read request signal U changes from "low" to "high".

In FIG. 1, a preset white reference value F is supplied to a white level comparison circuit 2 after being digitally encoded in 8 bits. However, the white reference value F
is set to a value lower than the output voltage value corresponding to the designated white density. The white level comparison circuit 2 compares the white reference value F and the white data for each pixel of the white extraction data F, selects all white data higher than the white reference value F, outputs it as selected white data M, and outputs it as selected white data M to the average value circuit 5. supply to.

Next, the black extraction circuit 3 specifies a density area on the original image that is desired to be black, extracts density data corresponding to each of a plurality of pixels from the area, and extracts black extraction data G.
The circuit configuration and operation are the same as those of the white extraction circuit 1 described above, except that the set values of counters 101 and 106 change depending on the position of the designated black density area. However, the white extraction data E of the above-mentioned white extraction circuit 1 should be read as black extraction data G, the white data as black data, and the white data sending signal _W1 as black data sending signal _W2 .

The black extraction data G output from the black extraction circuit 3 is supplied to the black level comparison circuit 4. A preset black reference value L is supplied to the black level comparison circuit 4 after being digitally encoded into 8 bits. however,
The black reference value L is set to a value higher than the output voltage corresponding to the designated black density.

The black level comparison circuit 4 compares the black reference value L and the black data for each pixel of the black extraction data G, selects all black data lower than the black reference value L, outputs it as selected black data N, and outputs it as selected black data N to the average value circuit. Supply to 5.

As shown in FIG. 3, the average value circuit 5 includes an addition circuit 501, storage circuits 502, 504, and 50.
5. A division circuit 503 is provided, and the average value of each of the selected white data M and the selected black data N is calculated,
8-bit white correction data H and black correction data Y
Output.

When the average value circuit 3 has no input data to be calculated, it supplies a "high" read request signal U from the division circuit 503 to the white extraction circuit 1 and the black extraction circuit 3 to request data.

In this state, as shown in FIG.
supplied to

The addition circuit 501 and the storage circuit 502 cumulatively add the selected white data M for each white data per pixel, and at the same time count the number of pixels to be added. When the addition is completed, the addition result and the added pixel are divided by the division circuit 50.
Supply to 3. The division circuit 503 performs division using the addition result as a dividend and the number of pixels to be added as a divisor, and outputs only the quotient as 8-bit white correction data H, with the remainder being rounded down.

During this time, the memory circuit 504 receives a white data sending signal.
Since W ₁ is supplied to instruct data writing, the white correction data H from the division circuit 503 is stored in the storage circuit 504 .

The average value of the selected black data N obtained by level-sorting the black extraction data G from the black extraction circuit 3 is also calculated in the same manner as above, and the calculated black correction data Y is stored in the storage circuit 5.
05.

The white correction data H and black correction data Y obtained in this way are white extraction data E and black extraction data G, respectively, which are composed of a plurality of pixel density data.
If the data contains abnormal output voltage values due to minute scratches or dust on the original image, pixel data with density values close to the pre-specified white density and black density with those abnormal data removed. Since it is an average value of only 100%, density data for desired white and black densities can be obtained.

In FIG. 1, when the pre-scanning of the original image is completed, the reading preparation signal P becomes "low", and the white correction data H and the black correction data Y are read out from the storage circuits 504 and 505 of the average value circuit 5, respectively.

The white correction data H is converted into an analog voltage value by the digital-to-analog conversion circuit 11 and then sent to the low-pass filter 12.
After that, it is output as the upper limit reference voltage _VH of "Vw" volts shown in FIG.

The black correction data Y is converted into an analog voltage value by the digital-to-analog conversion circuit 21 and then sent to the low-pass filter 22.
After that, it is output as the lower limit reference voltage V _L of "V _B " volts shown in FIG.

The upper limit reference voltage V _H and the lower limit reference voltage V _L are supplied to the analog-to-digital conversion circuit 7 .

Next, the scanning circuit 6 scans the original image, outputs an image signal A corresponding to the density information recorded on the original image, and supplies it to the analog-to-digital conversion circuit 7.

The analog-to-digital conversion circuit 7 converts the upper limit reference voltage _VH of " _VW " volts in response to the voltage value of the image signal A.
According to the determination level between the upper and lower limit voltages regulated by the lower limit reference voltage V _L of volts and “V _B ”, the data is converted into 8-bit digitally encoded data, and then sent to the corrected image signal via the bus switching gate 8. B _a
Output as .

FIGS. 6 and 7 show waveform diagrams of the above operation. In FIG. 6, the vertical axis shows the input voltage of the analog-to-digital conversion circuit 7, and the horizontal axis shows the period T of one scan.

Now, when the image signal A shown in Fig. 6 is converted into an analog-digital signal with "V ₊ " volts indicated by the dotted line in the figure as the upper limit reference voltage V _H and "V _- " volts as the lower limit reference voltage V _L , the analog-digital conversion is performed. It is clear that the 256-step resolution of circuit 7 cannot be obtained, and when the digital image signal obtained in this way is recorded and reproduced, the density difference between white and black cannot be obtained and an image with good contrast cannot be obtained. do not have.

When the image signal A is digitally converted with the "Vw" volts shown by the dashed line in FIG. 6 as the upper limit reference voltage _VH and the " _VB " volts as the lower limit reference voltage _VL , the hatched "A" The part is white, “ro”
The portions marked with "C" and "C" are black, but the resolution of the analog-to-digital conversion circuit 7 can be fully obtained in other portions.

Note that the portions "A", "B", and "C" are portions that were determined not to be reproduced when specifying specific density areas in the white and black density areas on the original image. Therefore, when the corrected image signal B _a is recorded and reproduced, an image with good contrast can be obtained.

FIG. 7 shows the apparent image signal A corresponding to the judgment classification of the analog-to-digital conversion circuit 7 when the upper limit reference voltage V _H is set to "V _W " volts and the lower limit reference voltage V _L is set to "V _B " volts. This is what is shown.

〔Effect of the invention〕

As described above, the image signal correction device of the present invention adds a white extraction circuit, a black extraction circuit, a white level comparison circuit, a black level comparison circuit, and an averaging circuit, fixes the upper limit reference voltage and the lower limit reference voltage, and uses analog Instead of digital conversion, among white data and black data from multiple pixels corresponding to specified white and black density areas on the original image, white data higher than the set white reference value and white data higher than the set black reference value are used. By performing analog-to-digital conversion using the average value of each low black data as the upper and lower limit reference voltages, it is possible to obtain a resolution equal to that of the analog-to-digital conversion circuit without worrying about minute scratches and dust on the original image. This has the effect of improving image quality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a detailed block diagram of the white extraction circuit in the embodiment shown in FIG. 1, FIG. 3 is a detailed block diagram of the average value circuit in the embodiment shown in FIG. 1, and FIG. 4 is a detailed block diagram of the white extraction circuit in the embodiment shown in FIG. A time chart for explaining the operation of the extraction circuit, FIG. 5 is an explanatory diagram of the image signal extraction operation of the white extraction circuit shown in FIG. 2, and FIG. 6 is for explaining the operation of the embodiment shown in FIG. 1. waveform diagram, 7th
This figure is an apparent waveform diagram for explaining the operation of the embodiment shown in FIG. 1. In the figure, 1...white extraction circuit, 2...white level comparison circuit, 3...black extraction circuit, 4...black level comparison circuit, 5...average value circuit, 7...analog-digital conversion circuit, A... ...Picture signal, B...Digital picture signal, Ba...Corrected picture signal, E...White extraction data, F...White reference value, G...Black extraction data,
L...Black reference value, M...Selected white data, N...Selected black data, H...White correction data, Y...Black correction data, V _H ...Upper limit reference voltage, V _L ...Lower limit reference voltage .

Claims (1)

[Claims] 1. A white extraction circuit that extracts white data from each of a plurality of pixels obtained by scanning a designated white density region of an original image and outputs white extraction data, and a white reference value that presets the white extraction data. a white level comparison circuit that compares and selects all the white data higher than the white reference value from the white extraction data and outputs it as selected white data; a black extraction circuit that extracts black data from each pixel and outputs black extraction data; and a black extraction circuit that compares the black extraction data with a preset black reference value and extracts all the black data that is lower than the black reference value. a black level comparison circuit that selects data from the selected data and outputs it as selected black data; an average value circuit that calculates an average value from the selected white data and the selected black data and outputs it as white correction data and black correction data; An analog/digital system in which a judgment level between an upper limit and a lower limit of a dynamic range is controlled by the correction data and the black correction data, and an image signal obtained by photoelectrically converting the gradation information recorded on the original image is multivalued decomposed according to the judgment level. An image signal modification device comprising: a conversion circuit.