JPH0244444A - Memory managing system - Google Patents

Memory managing system

Info

Publication number
JPH0244444A
JPH0244444A JP63196718A JP19671888A JPH0244444A JP H0244444 A JPH0244444 A JP H0244444A JP 63196718 A JP63196718 A JP 63196718A JP 19671888 A JP19671888 A JP 19671888A JP H0244444 A JPH0244444 A JP H0244444A
Authority
JP
Japan
Prior art keywords
area
memory
address
user
monitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63196718A
Other languages
Japanese (ja)
Inventor
Hisashi Shiraishi
久 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63196718A priority Critical patent/JPH0244444A/en
Publication of JPH0244444A publication Critical patent/JPH0244444A/en
Pending legal-status Critical Current

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  • Memory System (AREA)

Abstract

PURPOSE:To prevent a system from being stopped due to abnormality by managing a direct address by a memory managing monitor, and making access to a memory via a monitor by informing an indirect address to a user. CONSTITUTION:When the memory managing monitor 2 provides a page correspondence null area managing table 8 to the user 1 for a memory acquiring request (1) from the user 1 and informs an area address to the user 1, the user 1 manages an informed indirect address. The user 1 informs the indirect address to the memory managing monitor 2 when write (2) on an area is generated, and the monitor performs the write by converting the address from the indirect address to the direct address. When a state impossible to make access by an access guard processing 10 due to the fact that a designated indirect address is a null area, etc., the abnormality is informed to the user 1. Even when read-in or reference is performed, the access is performed via the monitor by informing the indirect address to the memory managing monitor 2. In such a way, it is possible to prevent the system from being stopped due to the abnormality.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、定ブロック長のメモリ作業エリアの管理方式
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for managing memory work areas of fixed block length.

〔従来の技術〕[Conventional technology]

従来、メモリの管理モニタは、ハードウェアの提供する
直接アドレスを多数のメモリ利用者に通知し、利用者各
自が通知されたメモリに対して直接アクセスしている。
Conventionally, a memory management monitor notifies a large number of memory users of a direct address provided by hardware, and each user directly accesses the notified memory.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のメモリ管理は、直接アドレスで多数の利
用者に管理がまかされているなめ、メモリ破壊や二重開
放により、システムの停止へつながるという欠点がある
The above-mentioned conventional memory management has the drawback that the management is entrusted to a large number of users using direct addresses, which can lead to system stoppage due to memory corruption or double opening.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、メモリ確保要求に対して、空きエリア
の払い出しおよび前記エリアの間接アドレスを通知する
処理と、払い出しな領域への書き込み、読み出し、参照
を確保時通知された間接アドレス指定により行なう処理
と、返却要求時、間接アドレスから前記エリアを空きチ
ェインへ接続して論理的に開放する処理と、空きエリア
チェック用管理テーブルによる空きエリアに対する開放
要求および空きエリアに対するアクセスをガードする処
理と、メモリ領域へのアクセス時、指定間接アドレスの
持つブロック長を越えて他のブロックへアクセスするこ
とをガードする処理とを有することを特徴とするメモリ
管理方式が得られる。
According to the present invention, in response to a memory reservation request, processing of allocating a free area and notifying an indirect address of the area, and writing, reading, and referencing to the allocated area are performed by specifying the indirect address notified at the time of allocation. processing; processing for connecting the area from an indirect address to a free chain and logically releasing it when a return request is made; and processing for guarding release requests and accesses to the free area using a management table for checking free areas; A memory management method is obtained which is characterized by having a process of guarding against accessing another block beyond the block length of a designated indirect address when accessing a memory area.

〔実施例〕〔Example〕

次に、本発明の一実施例を示した図面を参照して、本発
明をより詳細に説明する。
Next, the present invention will be described in more detail with reference to the drawings showing one embodiment of the present invention.

第1図を参照すると、本発明の一実施例において、利用
者1からのメモリ確保要求■に対して、メモリ管理モニ
タ2はページ対応空き領域管理テーブル8を利用者1へ
払い出す(メモリ確保処理3)。このとき、利用者1へ
は該領域アドレス(ページ番号やページ内ブロック番号
)を通知する。利用者1は、通知された間接アドレスを
管理する。
Referring to FIG. 1, in one embodiment of the present invention, in response to the memory reservation request ■ from the user 1, the memory management monitor 2 issues the page-based free space management table 8 to the user 1 (memory reservation request). Processing 3). At this time, the user 1 is notified of the area address (page number and block number within the page). User 1 manages the notified indirect address.

利用者1は、該領域への書き込み■が発生したとき、間
接アドレスをメモリ管理モニタへ通知して(メモリアク
セス処理4)、モニタ2が間接アドレスから直接アドレ
スに変換(アドレス変換処理6)して書き込みを行なう
、指定間接アドレスがアクセスガード処理10により空
き領域等でアクセスできない状態であれば、利用者1へ
異常を通知する。
When a write to the area occurs, user 1 notifies the memory management monitor of the indirect address (memory access processing 4), and monitor 2 converts the indirect address to a direct address (address conversion processing 6). If the specified indirect address to which writing is to be performed is in a state where it cannot be accessed due to an empty area or the like due to the access guard processing 10, the user 1 is notified of the abnormality.

読み込みおよび参照についても、メモリ管理モニタ2に
対して間接アドレスを通知してモニタを通してアクセス
する。
For reading and reference, the indirect address is notified to the memory management monitor 2 and access is made through the monitor.

利用者において、利用していた領域をモニタへ返却時■
についても、間接アドレスをモニタへ通知し、間接アド
レスから空き領域管理テーブル上の該領域を空きチェイ
ン9へつなぎ込む(メモリ解放処理5)、アクセスガー
ド処理によりすでに開放されていれば異常を利用者へ通
知する。
When a user returns the area they were using to the monitor■
, the indirect address is notified to the monitor, and the corresponding area on the free area management table is connected to the free chain 9 from the indirect address (memory release processing 5). Notify.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、メモリ管理モニ
タが直接アドレスを管理し、利用者へは間接アドレスを
通知し、メモリへのアクセスをモニタを介して行なうこ
とにより、従来のようなトラブルを防ぐ効果がある。
As explained above, according to the present invention, the memory management monitor manages addresses directly, notifies the user of indirect addresses, and accesses the memory via the monitor, thereby avoiding the troubles encountered in the past. It has the effect of preventing

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の構成を示す図である。 1・・・利用者、2・・・メモリ管理モニタ、3・・・
メモリ確保処理、4・・・メモリアクセス処理、5・・
・メモリ開放処理、6・・・直接アドレス←→間接アド
レス変換処理、7・・・メモリ領域、8・・・ページ対
応空き領域管理テーブル、9・・・空きエリアチェック
用管理テーブル、10・・・アクセスガード処理。 代理人 弁理士  内 原  晋 tl)。
FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. 1... User, 2... Memory management monitor, 3...
Memory reservation processing, 4...Memory access processing, 5...
・Memory release processing, 6... Direct address ←→ indirect address conversion processing, 7... Memory area, 8... Free area management table for pages, 9... Management table for checking free areas, 10...・Access guard processing. Agent: Susumu Uchihara, patent attorney.

Claims (1)

【特許請求の範囲】 メモリ確保要求に対して、空きエリアの払い出しおよび
前記エリアの間接アドレスを通知する処理と、 払い出した領域への書き込み、読み出し、参照を確保時
通知された間接アドレス指定により行なう処理と、 返却要求時、間接アドレスから前記エリアを空きチェイ
ンへ接続して論理的に開放する処理と、空きエリアチェ
ック用管理テーブルによる空きエリアに対する開放要求
および空きエリアに対するアクセスをガードする処理と
、 メモリ領域へのアクセス時、指定間接アドレスの持つブ
ロック長を越えて他のブロックへアクセスすることをガ
ードする処理とを 有することを特徴とするメモリ管理方式。
[Scope of Claims] In response to a memory allocation request, a process of allocating a free area and notifying an indirect address of the area, and writing, reading, and referencing to the allocated area are performed by specifying the indirect address notified at the time of allocation. processing; processing for connecting the area from an indirect address to an empty chain and logically releasing it when a return request is made; processing for guarding a release request for and access to an empty area using a management table for checking an empty area; 1. A memory management system comprising: when accessing a memory area, guarding against accessing another block beyond the block length of a designated indirect address.
JP63196718A 1988-08-05 1988-08-05 Memory managing system Pending JPH0244444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63196718A JPH0244444A (en) 1988-08-05 1988-08-05 Memory managing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63196718A JPH0244444A (en) 1988-08-05 1988-08-05 Memory managing system

Publications (1)

Publication Number Publication Date
JPH0244444A true JPH0244444A (en) 1990-02-14

Family

ID=16362441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63196718A Pending JPH0244444A (en) 1988-08-05 1988-08-05 Memory managing system

Country Status (1)

Country Link
JP (1) JPH0244444A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61112257A (en) * 1984-07-12 1986-05-30 テキサス インスツルメンツ インコ−ポレイテツド Computer memory system
JPS63109553A (en) * 1986-10-28 1988-05-14 Nec Corp Memory management system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61112257A (en) * 1984-07-12 1986-05-30 テキサス インスツルメンツ インコ−ポレイテツド Computer memory system
JPS63109553A (en) * 1986-10-28 1988-05-14 Nec Corp Memory management system

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