JPH0244600A - Semiconductor non-volatile storage device - Google Patents

Abstract

PURPOSE:To control to minimize the space increase of a storage cell and to execute an unvolatile storage for the short period of time by holding data to be written at a holding means for the specific period of time in order to correspond respectively to cells executing the unvolatile storage and connecting the holding means through a connection means. CONSTITUTION:A capacity 21 as the temporary storage means 2 of a semiconductor unvolatile storage device is connected to the gate of MIS transistor Tr31 in which the connection means is constituted. The control gate of a floating gate MISTr41 as an unvolatile storage means is connected to the drain of the MISTr31 constituting the storage means and the drain of the MISTr31 is connected to a capacity 32. A temporary storage is executed by charging or discharging the capacity 32, a high voltage is impressed on one end A of the capacity 32 which is not connected to the drain of the MISTr31, which the connection point B of the drain of the MISTr31 and the capacity 32 is charged, it is made into a potential same as a source potential, when it is discharged, it is made into the potential close to a high voltage being impressed on one end A of the capacity 32.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a semiconductor memory device, and particularly to a rewritable semiconductor nonvolatile memory device.

[Summary of the Invention] The present invention comprises means for temporarily storing memory cells for a certain period of time in a semiconductor nonvolatile memory device, means for nonvolatile storage, and means for connecting the two means. With this configuration, writing is performed in the temporal storage means in a short period of time, and then all bits are simultaneously transferred from the temporal storage means to the non-volatile storage means via the connection means. This enables non-volatile storage of a large number of pits in a short period of time.

[Conventional technology]

Rewritable semiconductor non-volatile memory devices have the ability to retain their stored data even when the power supply is cut off. EEPROM, which has become rewritable, and SRAM and EEP
NVRAM (NOVR) in which the ROM corresponds to one bit at a time
AM) etc. were known. Incidentally, FIG. 2 is a block diagram showing a memory cell of a conventional semiconductor woodworking volatile memory device, where 1 is a memory cell and 4 is a nonvolatile memory means.

[Problems to be Solved by the Invention] In systems using semiconductor nonvolatile memory devices, there is often a demand for writing a large amount of data in a nonvolatile manner in a short time. For such a request, 1, for example, 6
When considering a 4-bit EEPROM, if the configuration is 8 bits x 819 GB and it takes 10 milliseconds to rewrite 1 byte, all bits can be rewritten.

It will take more than 81.92 seconds. Furthermore, even if there is a page mode rewrite function installed in some recent models, if the 64-bit EEFROM has 256 pages, it will take about 2.56 seconds or more. As described above, conventional semiconductor non-volatile memory devices have the disadvantage that it takes a very long time to rewrite a large amount of data.

In addition, in the case of conventional NVRAM, one SRAM cell corresponds to one nonvolatile memory cell, and although the rewrite time λ is short, the area of the cell is very large. However, there were drawbacks such as the system becoming larger and being disadvantageous in terms of cost. This invention was made to solve these conventional drawbacks, and aims to provide a semiconductor non-volatile memory device that takes less time to rewrite all bits and is also advantageous in terms of cost. .

[Means for Solving the Problems] In order to solve the above problems, the present invention temporarily stores (retains) data to be written for at least a certain period of time so as to correspond to each cell that performs nonvolatile storage. ), and by connecting via the connecting means, it is possible to perform non-volatile storage in a short time while minimizing the increase in the area of the memory cell.

[Function] In the memory cell configured as described above, when writing, the means for temporarily storing (retaining) the write data is used for tens of thousands of minutes of the time required for non-volatile storage. After completion of temporary writing to all bits, which is written in a time of 1 to 1/100,000th (per byte), the connecting means is connected from the temporal storage means to the non-volatile storage means. All bits are non-volatilely stored simultaneously through the memory.

[Embodiment 1] FIG. 1 is a block diagram showing the principle of the present invention, in which 1 is a memory cell, 2 is a temporary storage means, 3 is a connection means, and 4 is a nonvolatile storage means.

FIG. 3 shows a first embodiment of the present invention, in which a capacitor ff121 serving as a -time storage means is connected to the gate of a MISI disk 31 constituting a connecting means. The control gate of the floating gate MrSl-transistor 41 serving as non-volatile storage means is connected to the drain of the MIS transistor 31 constituting the connection means. Also.

The train of the MrS) run disk 31 is connected to a capacitor 32. First, temporary storage is performed by charging or discharging the capacitor fi21.Next, when a high voltage is applied to one end A of the capacitor 32 that is not connected to the drain of the MISh transistor 31, the M
When the capacitor ff121 is charged, the connection point B between the drain of the IS transistor 31 and the capacitor M132 is as follows.
When the capacitor ff121 is discharged to the same potential as the source of the MIS transistor 31, the capacitor 3
The potential is close to the high voltage applied to one end A of 2.

The connection point B is connected to the control gate of the floating gate MIS transistor 41, and the potential at the connection point B is transmitted to the control gate.

FIG. 4 is a timing diagram of the first embodiment, with curve a
represents the potential of A, or the potential of C, and TI is
This is the period when 21 of the potential of A is high voltage, and T2
indicates a period in which both the potential of A and the potential of C are high voltages. When a voltage is applied at the timing shown in FIG. 4, the connection point B is at the same potential as the source of the MIS transistor 31. In the case where the information It will be done.

When rewriting is performed in the above procedure, for example λ6
Considering a semiconductor non-volatile memory device according to the present invention having memory cells of 4 bits (8 bits x 8192 bytes), it takes -250 + 1 per byte to perform temporal storage.
Even though it took f3' to do all the bits.

It takes 250+1 seconds x 8192 = 2.05 milliseconds, after which all bits are simultaneously written from the -time storage means to the non-volatile storage means.

This operation takes about 10 milliseconds, which is the same time as one non-volatile write, so it takes about 12 milliseconds in total to finish rewriting all bits to +34.

FIG. 5 shows a second embodiment of the present invention, in which the write terminal of the floating gate MIS transistor 41 is connected to the connection point A in the first embodiment, and the floating gate MIS transistor 41 is connected to the connection point A in the first embodiment.
The control gate No. 1 is connected to the terminal C, and by applying the same potential to the terminal C as the write terminal C in the first embodiment, the same operation as in the first embodiment is performed. It is.

FIG. 6 shows a third embodiment of the present invention, in which the drain of the floating gate MIS transistor 41 of the first embodiment and the capacitor fi21 are connected via an MIS transistor 51, and the floating gate M.I.
The information stored in the S transistor 41 is
121 has been added.

[Effects of the Invention j As explained above, this invention has the effect that all bits can be rewritten in a short time without requiring a large memory cell area even in a large-capacity semiconductor nonvolatile memory device. be.

The above effect is not limited to the one using the floating gate type MISI-LAN disk as the nonvolatile storage means as explained in this embodiment, but the same effect can be obtained in the nonvolatile storage method using other principles. In addition, when using the connection means, it is possible to connect not only one-way from the time storage means to the non-volatile storage means, but also to connect from the non-volatile storage means to the temporary storage means. Needless to say, it has a similar effect. (See Figure 5) ・Non-volatile storage means・Capacity・MISI-Randisk・Capacitor・Floating goo 1-Ml5I-Ransistor

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor nonvolatile memory device according to the present invention, FIG. 2 is a block diagram of a conventional semiconductor nonvolatile memory device, and FIG. 3 is a circuit diagram showing a first embodiment of the present invention. FIG. 4 is a voltage timing diagram of the first embodiment according to the present invention. FIG. 5 is a circuit diagram showing a second embodiment of the present invention;
FIG. 6 is a circuit diagram showing a third embodiment of the present invention. Applicant Seiko Electronics Co., Ltd. Agent Patent Attorney Toshinosuke Hayashi 1...Memory cell 2...-1 means for marking time 3...Connection means Section 3 MIS transistor 3rd complete circuit diagram Figure 6

Claims (2)

[Claims] (1) In a rewritable semiconductor non-volatile memory device, the memory consists of means for temporarily storing data for at least a certain period of time, means for non-volatile memory, and means for connecting the two means respectively. A semiconductor nonvolatile memory device having cells. (2) The semiconductor non-volatile memory device according to claim 1, wherein the means for temporarily storing data for a certain period of time comprises at least a capacitor.