JPH0245855A - Data transferring control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology and Problems to be Solved by the Invention Means for Solving the Problems Action Examples Effects of the Invention [Summary] Transfer control device in a computer system (channels), input/output control units, and devices, especially magnetic disks, semiconductor disks, and magnetic disks that define the number of bytes of the data section in each record by the count section (C) of its header. Regarding the data transfer control method in the truncation operation between the input/output control device and the device, which is the data transfer operation performed between the cache, etc., the data transfer control time for each device related to the input/output control device is shortened. , a promise to improve the processing efficiency of the input/output control device, and control data transfer between the transfer control device and the device based on input/output commands issued by the central processing unit (CPTL). an input/output device comprising a means for detecting a data transfer stop command from the transfer control device when the data transfer is stopped, and a means for writing a specified number of remaining bytes of data to the device after receiving the data transfer stop instruction. In the control device,
The remaining specified number of bytes of data to be written to the device after the data transfer stop instruction from the transfer control device is separated from the data transfer means between the transfer control device and the input/output control device and the device. After detecting a data transfer stop command from the transfer control device, the remaining prescribed number of bytes of data is transferred at the maximum transfer capacity between the human output control device and the device. Configure to transfer at speed.

[Industrial application field]

The present invention relates to a transfer control device (channel), an input/output control device, and a device in a computer system.

In particular, magnetic disks and semiconductor disks in which the number of bytes of the data section in each record is defined by the count section (C) of the header of the record.

The present invention relates to a data transfer control method in a truncation operation between an input/output control device and a device, which is a data transfer operation performed between a magnetic disk cache and the like.

With the diversification of data processing in recent computer systems, the functions of input/output control devices have also become more complex, and control information exchanged with devices.

The amount of data is increasing, and the amount of time connected to a specific device is also increasing.

On the other hand, the number of devices connected to the input/output connection device is increasing, and being tied to one device for a long time is a factor that reduces the processing efficiency of the input/output control device, which has a limited processing capacity. It is becoming more and more common.

Due to these circumstances, the above transfer control device (channel)
Transfer of dummy data between the input/output control device and the device after receiving an instruction to stop data transfer from
There is a need for a data transfer control method that performs the truncation operation in a short time, reduces the time that the input/output control device is tied to one device as much as possible, and improves the processing efficiency of the input/output control device.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram explaining a conventional data transfer control system, and (a
) shows an overview of the configuration of a conventional computer system, and (b)
shows an overview of the data transfer circuit (at the time of writing) of the input/output control device.

Usually magnetic disk devices, semiconductor disk devices.

In a magnetic disk cache, etc., a plurality of records for storing data are set in one track during format writing during initialization, and each record has a count part (C) and a key part (KEY).

It consists of a data section (DATA), and the count section (C) defines the data length (number of bytes) of the data section (DATA) of the record.

However, since software does not necessarily use all the data parts (DATA) of each record, when a write operation is performed from software, the number of bytes (channel command) specified by the input/output command issued by the software When a transfer stop instruction is received from the transfer control device (channel) 12 at the time when the byte count part (BC) of the word (CCW) has been transferred, the input/output control device 3
The device 4 disconnects from the transfer control device (channel) 12 and autonomously sets the remaining data length specified by the count section (C) of the record as dummy data (usually all "00"). Write to.

In this case, the in-collect length check is suppressed. However, when writing all the byte lengths specified by the count section (C), the check is made to take advantage of the operation.

This is to guarantee the number of recorded bytes of data from the software perspective (that is, to guarantee the in-collect length check when all records are read), and normally in the main system, stop operation, input/output In the control system,
This is called a truncation action.

At the time of reading, only the data up to the point where the transfer stop instruction is received from the transfer control device 12 is read, and the subsequent data is ignored. Therefore, in this case as well, the in-collect length check is suppressed in the same way as when writing. Then, the check is activated only when the entire number of bytes specified by the counting section (C) is read.

The specific operation of the above write operation will be explained in more detail with reference to this figure.

First, in (a) of the figure, the central processing unit (CPU) 11 of the main unit 1 executes specific software,
By issuing an input/output command, the transfer control device (channel) 12 reads a channel command word (CCW) from a main memory (MS) (not shown), and communicates it with the device 4 via the input/output control device 3. Execute input/output processing between.

At this time, when the transfer control device (channel) 12 recognizes that data as many as the byte count (BC) indicated by the channel command word (CCW) has been transferred, the input/output control device 3, a transfer stop instruction (STOP) is sent.

The input/output control device 3 receives the transfer stop instruction (STOP) via the channel interface control circuit 31,
When recognized by the transfer stop signal extraction circuit 34a, 1. Set flip-flop (FF) 34b and select “*5TOP
It operates to energize the J signal and inhibit the AND gate circuit 32a of the transfer control circuit 32.

At this time, the middle [
Since the header of a specific record, that is, the count part (C) and key part (KEY) are read by the "Search II) command", the number of bytes of the record to be transferred is determined by the transfer control circuit 32. Transfer byte counter 32
c, and the transfer speed oscillator (circuit) 35
With a fixed clock from a, the transfer byte counter 3
Until 2c becomes 0, the inhibited output of the AND gate circuit 32a, ie, the °OO° signal, is transferred to the device 4 as the dummy data.

Therefore, in the conventional method, even if the data transfer operation from the transfer control device (channel) 12 is completed, the device 4
The transfer of dummy data to the transfer control device continues based on the clock {circle around (2)} instructed by the transfer speed oscillator (circuit) 35a while the transfer capability (transfer speed between higher-level devices) of the transfer control device is maintained.

Therefore, even if the above-mentioned transfer stop instruction (STOP) is output at the beginning of the transfer of a long data byte, the input/output control device 3
At the data transfer rate between the device 4 and the device 4, a transfer time is required to write the remaining bytes of dummy data.

This means that when data of a certain length is transferred, no matter which part of the data the 5TOP instruction is issued, the control time of the input/output control device 3 for that data transfer is constant. , and how many input/output control devices 3. Even if the device 4 has the transfer capability (transfer speed), it depends on the transfer capability of the upper transfer control device (channel) to which it is connected, and there is a problem that the transfer control time for the dummy data cannot be shortened. Ta.

In view of the above conventional drawbacks, the present invention provides a transfer control device (channel device) and an input/output control device in a computer system,
Data transfer performed between devices, especially magnetic disks, semiconductor disks, magnetic disk caches, etc., in which the number of bytes of the data section in each record is specified by the count section (C) of the header of the record. In the data transfer control method in the truncation operation between the input/output control device and the device, the remaining data is sent after the data transfer stop instruction (STOP) issued by the transfer control device (channel) to the human output control device. The object of the present invention is to provide a data transfer control method for an input/output control device that allows high-speed transfer between devices.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle structure of the data transfer control system of the present invention.

The above problems are solved by a data transfer control system configured as follows.

When data transfer is being controlled between the transfer control device 12 and the device 4 based on input/output commands issued by the central processing unit (CPU) 11, data transfer from the transfer control device 12 is stopped. In the input/output control device 3, which includes a means 34 for detecting a command and a means 32 for writing a specified number of bytes of data remaining in the device 4 after receiving the instruction to stop the data transfer, The control means 35 separates the data transfer of the remaining predetermined number of bytes from the data transfer means with the transfer control device 12 and transfers the data between the input/output control device 3 and the device 4 at the maximum transfer capacity. After detecting the data transfer stop command from the transfer control device 12, the remaining specified number of bytes of data is transferred at the maximum transfer speed between the input/output control device 3 and the device 4.

[Effect]

That is, according to the present invention, a transfer control device (channel) and an input/output control device in a computer system.

Data transfer performed between devices, especially magnetic disks, semiconductor disks, magnetic disk caches, etc., in which the number of bytes of the data section in each record is specified by the count section (C) of the header of the record. In the pig transfer control method in the truncation operation between the input/output control device and the device, after receiving the ST command from the transfer control device (channel), the transfer that was previously performed with the transfer control device Transfer the remaining data (dummy data) by switching the speed to the maximum transfer speed of the input/output control device and controlled device.
Write).

That is, in data transfer (write) between a transfer control device and a device via an input/output control device, when the input/output control device receives a data transfer stop command from the transfer control device, A transfer speed switching instruction after the data transfer is stopped is given to the transfer speed switching circuit from the channel interface control circuit.

As a result, the transfer speed switching circuit switches the transfer speed between the transfer control devices that has been performed up to now to the maximum transfer speed that can be performed between the devices under the control, and transfers the remaining bytes of dummy data. , and causes the device to function to write at the switched transfer speed.

Therefore, the transfer time of dummy data to the device after the data transfer stop instruction from the transfer control circuit (channel) is determined by the input/output control device without depending on the transfer capability of the upper transfer control device (channel).

By using the maximum transfer capacity of the device, the data transfer control time of the input/output control device can be shortened, and the processing efficiency of the input/output control device can be improved.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing the principle configuration of the data transfer control system of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention, where (a) shows an example of the configuration, (bl), (b2) is a diagram showing an example of a stopping operation, and the transfer speed switching circuit 35 shown in FIGS. 1 and 2 is a necessary means to implement the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

Hereinafter, the data transfer system of the present invention will be explained with reference to FIG. 2 while referring to FIG.

Even if the present invention is implemented, the basic operation of input/output processing for devices such as semiconductor disk drives and magnetic disk drives will not be particularly different from conventional methods, so the explanation will be omitted here. ) 12 will be mainly described with reference to dummy data write control after a transfer stop instruction is issued.

First, data transfer between the transfer control device (channel) 12 and the device 4 in write mode is performed by the transfer control device (channel) 12 and the device 4.
Transfer data from the channel) 12 is received by the channel interface control circuit 31 of the input/output control device 3,
Data buffer circuit 31a.

Transfer control circuit 32. The data is transferred to the device 4 via the data buffer circuit 33a and the device interface control circuit 33.

During this data transfer, the transfer control device (channel)
When 12 issues a data transfer stop (STOP) command, the transfer stop (STOP) definition signal (usually commanded by a command out signal in a known input/output interface) is turned on on the dotted control line ■. and give commands.

In the input/output control device 3, the channel interface control circuit 31 detects this stop command, and the transfer stop signal cutting circuit 34a cuts out the pulse.

The extracted stop instruction pulse is sent to a flip-flop (FF) (hereinafter referred to as 5) in order to give a stop control instruction to each control circuit.
(referred to as TOP FF) 34b. This 5TO
The PFF 34b is reset before data transfer is started, and becomes in the state of '5TOP=0' and 'main 5TOP=1', and the above stop instruction pulse sets °5TOP=1.
”, the state of '*5top=o' is stored.

Depending on the "on"/"off" state of the 5TOP FF, the frequency of the control clock (2) for operating each control circuit is switched.

When there is no stop instruction from the transfer control device (channel) 12, the 5TOP FF 34b is the above “5TOP・0”.
, '*si.

P = 1'', the inter-channel transfer speed oscillator 35a is selected by the oscillator switching gate 35c, and the frequency of the control clock ■ is set to the inter-channel transfer speed. 5TOP FP 34b is °5TOP・1°, “*sr
.

P=0'', the inter-device maximum transfer speed oscillator 35b is selected by the oscillator switching gate 35d, and the control clock frequency is switched to match the maximum transfer speed between the input/output control device 3 and the device 4.

Each clock frequency (2) is ORed by an OR gate 35e, and sent to each data transfer control circuit for control.

In other words, during normal data transfer, the transfer control circuit operates with a control clock synchronized with the inter-channel data transfer speed, and after receiving a stop instruction from the transfer control device (channel) 12, the transfer control circuit operates at the maximum transfer speed between devices. 32 transfer byte counter 32c is set to a specified number of bytes (normally, the transfer byte counter 32c is set to the number of transfer bytes specified by the count section (C) of each record, is decremented according to the number of bytes of transfer data, and the value is 0", the transfer ends).

When data is transferred to the device 4 after receiving the transfer stop command from the transfer control device (channel) 12, the transfer control circuit 32 generates dummy data and sends it to the device 4, as described above.

Normally, this dummy data is data of 000, but in this embodiment, dummy data of 00 is also generated. That is, the above 5TOP FF34b
However, the above transfer stop command '5TOP=1', '*
By entering the state of s'rop=O'', the AND gate 32a of the transfer control circuit 32 is inhibited, and by outputting the °0'' signal to the AND gate 32b, the transfer byte counter 32c after the transfer is stopped. The dummy data (°00” data) is sent to the device 4 until “00” becomes “0”.
' is written.

As described above, each transfer control circuit when writing this dummy data is separated from the transfer control speed between the transfer control devices (channels) 12 described above and synchronized with the maximum transfer speed between devices.

FIG. 2(h) shows that the device 4 is, for example, a semiconductor disk device, and the input/output control device 3. The transfer capacity of the disk 4 is 6 MB/sec, and the transfer capacity of the transfer control device (channel) 12 on the main body side is 3 MB/s.
It shows a stop operation executed in the case of an information processing system with ec.

Data transfer with the normal transfer control device (channel) 12 is set to the above-mentioned 3 MB/sec in accordance with the upper transfer control device (channel) 12.
Data transfer between channel) 12 and device 4 takes place.

Here, when the transfer control device (channel) 12 issues a transfer stop instruction, the device, that is, the semiconductor disk control device (input/output control device) 3, transfers 3 MB/sec between the transfer control devices. speed.

Then, the transfer speed is switched to 6 MB/see, which is the maximum transfer capacity of the self-device and the semiconductor disk device 4, and the writing operation of the remaining specified bytes continues until the transfer byte counter 32c described above reaches 0. When this happens, the main transfer operation ends.

According to this embodiment, when the total number of transferred bytes is N, and the above-mentioned transfer stop instruction is issued after N bytes have been transferred,
The remaining data for N2 will be written to device 4 as dummy data.

In this case, in the conventional method shown in figure (bl), the time required for the entire data transfer is N x 3 MB/5ec= (N, +Nz)
This will require a time of 3 MB/see.

However, according to the present invention, as shown in figure (b2),
The total time required is (N+ X 3 MB/5ec) + (Nz X 6
MB/5ec), the data transfer time for N2 minutes can be reduced to 172.

As described above, the present invention provides a transfer control device (channel device), an input/output control device, and a device in a computer system, and in particular, the count section (C) of the header for each record.
A magnetic disk in which the number of bytes of the data section in the record is defined by

In the data transfer control method for the truncation operation between the input/output control device and the device, which is the data transfer operation performed between semiconductor disks, magnetic disk caches, etc., after receiving a transfer stop command from the transfer control device, Switch the transfer speed that had been performed with the transfer control device to the maximum transfer speed of the input/output control device and controlled device, and transfer the specified number of bytes of data after receiving the transfer stop instruction. It is distinctive in that it is designed to do this.

〔Effect of the invention〕

As described above in detail, the data transfer control method according to the present invention is applicable to a transfer control device (channel device) and a human output control device in a computer system.

Data transmitted between devices, especially magnetic disks, semiconductor disks, magnetic disk caches, etc., which defines the number of bytes of the data section in each record by the count section (C) of the header of each record. In the data transfer control method for the truncation operation between the input/output control device and the device in the transfer operation, it is performed between the transfer control device and the device based on the input/output command issued by the central processing unit (CPU). Means for detecting a data transfer stop command from the transfer control device when controlling data transfer, and means for writing a specified number of remaining bytes of data to the device after receiving the data transfer stop instruction. In the input/output control device equipped with the above-mentioned input/output control device, the data transfer of the remaining specified number of bytes to be written to the device after the data transfer stop instruction from the transfer control device is separated from the data transfer means with the transfer control device, The input/output control device is provided with a control means for transferring data at the maximum transfer capacity between the devices, and after detecting a data transfer stop command from the transfer control device, the input/output control device transfers the remaining prescribed number of bytes of data. Since the data is transferred at the maximum transfer speed between the transfer control circuit (channel) and the device (4), the transfer time of dummy data to the device after the transfer stop instruction from the transfer control circuit (channel) is determined by the upper transfer control. Device(
input/output control device without depending on the transfer capacity of the channel).

By using the maximum transfer capacity of the device, the data transfer control time of the input/output control device can be shortened, and the processing efficiency of the input/output control device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the data transfer control system of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram explaining a conventional data transfer control method. It is. In the drawings, 1 is a main unit, and 11 is a central processing unit (CPU). 12 is a transfer control device (channel); 3 is an input/output control device or a semiconductor disk control device. Place. 31 is a channel interface control circuit. 32 is a transfer control circuit; 32a and 32b are AND gates; 32c is a transfer byte counter. 33 is a device interface control circuit. 34 is a transfer stop determination circuit. 34a is a transfer stop signal extraction circuit. 34b is a flip-flop (FF) (STOP FF
). 35 is a transfer speed switching circuit. 35a is an inter-channel transfer speed oscillator. 35b is the maximum transfer speed oscillator between devices. 35c, 35d are oscillator switching gates 35e are OR gates. 4 is a device, or ① is a control line. ■ is the clock frequency. are shown respectively. Semiconductor disk device. Or control clock.

Claims (1)

[Claims] When controlling data transfer between a transfer control device (12) and a device (4) based on an input/output command issued by a central processing unit (CPU) (11). means (34) for detecting a data transfer stop command from the transfer control device (12); and means for writing a specified number of remaining bytes of data into the device (4) after receiving the data transfer stop command. (32), the remaining specified number of bytes of data to be written to the device (4) is transferred from the data transfer means with the transfer control device (12). Disconnect the input/output control device (
3) and a control means (35) that transfers data at the maximum transfer capacity between the devices (4), and after detecting a data transfer stop command from the transfer control device (12), transfers the remaining specified number of bytes of data. , input/output controller (3) and device (4)
) is a data transfer control method characterized by transferring data at the maximum transfer speed between.